diff -Nru a/CREDITS b/CREDITS
--- a/CREDITS	2005-01-30 22:22:39 -08:00
+++ b/CREDITS	2005-02-04 17:23:03 -08:00
@@ -1811,7 +1811,8 @@
 
 N: Greg Kroah-Hartman
 E: greg@kroah.com
-W: http://www.kroah.com/linux-usb/
+E: gregkh@suse.de
+W: http://www.kroah.com/linux/
 D: USB Serial Converter driver framework, USB Handspring Visor driver
 D: ConnectTech WHITEHeat USB driver, Generic USB Serial driver
 D: USB I/O Edgeport driver, USB Serial IrDA driver
@@ -1819,6 +1820,7 @@
 D: bits and pieces of USB core code.
 D: PCI Hotplug core, PCI Hotplug Compaq driver modifications
 D: portions of the Linux Security Module (LSM) framework
+D: parts of the driver core, debugfs.
 
 N: Russell Kroll
 E: rkroll@exploits.org
@@ -2023,12 +2025,14 @@
 
 N: Michal Ludvig
 E: michal@logix.cz
+E: michal.ludvig@asterisk.co.nz
 W: http://www.logix.cz/michal
 P: 1024D/C45B2218 1162 6471 D391 76E0 9F99  29DA 0C3A 2509 C45B 2218
 D: VIA PadLock driver
 D: Netfilter pkttype module
-S: Prague 4
-S: Czech Republic
+S: Asterisk Ltd.
+S: Auckland
+S: New Zealand
 
 N: Tuomas J. Lukka
 E: Tuomas.Lukka@Helsinki.FI
diff -Nru a/Documentation/atomic_ops.txt b/Documentation/atomic_ops.txt
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/Documentation/atomic_ops.txt	2005-02-06 21:18:55 -08:00
@@ -0,0 +1,456 @@
+		Semantics and Behavior of Atomic and
+		         Bitmask Operations
+
+			  David S. Miller	 
+
+	This document is intended to serve as a guide to Linux port
+maintainers on how to implement atomic counter, bitops, and spinlock
+interfaces properly.
+
+	The atomic_t type should be defined as a signed integer.
+Also, it should be made opaque such that any kind of cast to a normal
+C integer type will fail.  Something like the following should
+suffice:
+
+	typedef struct { volatile int counter; } atomic_t;
+
+	The first operations to implement for atomic_t's are the
+initializers and plain reads.
+
+	#define ATOMIC_INIT(i)		{ (i) }
+	#define atomic_set(v, i)	((v)->counter = (i))
+
+The first macro is used in definitions, such as:
+
+static atomic_t my_counter = ATOMIC_INIT(1);
+
+The second interface can be used at runtime, as in:
+
+	struct foo { atomic_t counter; };
+	...
+
+	struct foo *k;
+
+	k = kmalloc(sizeof(*k), GFP_KERNEL);
+	if (!k)
+		return -ENOMEM;
+	atomic_set(&k->counter, 0);
+
+Next, we have:
+
+	#define atomic_read(v)	((v)->counter)
+
+which simply reads the current value of the counter.
+
+Now, we move onto the actual atomic operation interfaces.
+
+	void atomic_add(int i, atomic_t *v);
+	void atomic_sub(int i, atomic_t *v);
+	void atomic_inc(atomic_t *v);
+	void atomic_dec(atomic_t *v);
+
+These four routines add and subtract integral values to/from the given
+atomic_t value.  The first two routines pass explicit integers by
+which to make the adjustment, whereas the latter two use an implicit
+adjustment value of "1".
+
+One very important aspect of these two routines is that they DO NOT
+require any explicit memory barriers.  They need only perform the
+atomic_t counter update in an SMP safe manner.
+
+Next, we have:
+
+	int atomic_inc_return(atomic_t *v);
+	int atomic_dec_return(atomic_t *v);
+
+These routines add 1 and subtract 1, respectively, from the given
+atomic_t and return the new counter value after the operation is
+performed.
+
+Unlike the above routines, it is required that explicit memory
+barriers are performed before and after the operation.  It must be
+done such that all memory operations before and after the atomic
+operation calls are strongly ordered with respect to the atomic
+operation itself.
+
+For example, it should behave as if a smp_mb() call existed both
+before and after the atomic operation.
+
+If the atomic instructions used in an implementation provide explicit
+memory barrier semantics which satisfy the above requirements, that is
+fine as well.
+
+Let's move on:
+
+	int atomic_add_return(int i, atomic_t *v);
+	int atomic_sub_return(int i, atomic_t *v);
+
+These behave just like atomic_{inc,dec}_return() except that an
+explicit counter adjustment is given instead of the implicit "1".
+This means that like atomic_{inc,dec}_return(), the memory barrier
+semantics are required.
+
+Next:
+
+	int atomic_inc_and_test(atomic_t *v);
+	int atomic_dec_and_test(atomic_t *v);
+
+These two routines increment and decrement by 1, respectively, the
+given atomic counter.  They return a boolean indicating whether the
+resulting counter value was zero or not.
+
+It requires explicit memory barrier semantics around the operation as
+above.
+
+	int atomic_sub_and_test(int i, atomic_t *v);
+
+This is identical to atomic_dec_and_test() except that an explicit
+decrement is given instead of the implicit "1".  It requires explicit
+memory barrier semantics around the operation.
+
+	int atomic_add_negative(int i, atomic_t *v);
+
+The given increment is added to the given atomic counter value.  A
+boolean is return which indicates whether the resulting counter value
+is negative.  It requires explicit memory barrier semantics around the
+operation.
+
+If a caller requires memory barrier semantics around an atomic_t
+operation which does not return a value, a set of interfaces are
+defined which accomplish this:
+
+	void smb_mb__before_atomic_dec(void);
+	void smb_mb__after_atomic_dec(void);
+	void smb_mb__before_atomic_inc(void);
+	void smb_mb__after_atomic_dec(void);
+
+For example, smb_mb__before_atomic_dec() can be used like so:
+
+	obj->dead = 1;
+	smb_mb__before_atomic_dec();
+	atomic_dec(&obj->ref_count);
+
+It makes sure that all memory operations preceeding the atomic_dec()
+call are strongly ordered with respect to the atomic counter
+operation.  In the above example, it guarentees that the assignment of
+"1" to obj->dead will be globally visible to other cpus before the
+atomic counter decrement.
+
+Without the explicitl smb_mb__before_atomic_dec() call, the
+implementation could legally allow the atomic counter update visible
+to other cpus before the "obj->dead = 1;" assignment.
+
+The other three interfaces listed are used to provide explicit
+ordering with respect to memory operations after an atomic_dec() call
+(smb_mb__after_atomic_dec()) and around atomic_inc() calls
+(smb_mb__{before,after}_atomic_inc()).
+
+A missing memory barrier in the cases where they are required by the
+atomic_t implementation above can have disasterous results.  Here is
+an example, which follows a pattern occuring frequently in the Linux
+kernel.  It is the use of atomic counters to implement reference
+counting, and it works such that once the counter falls to zero it can
+be guarenteed that no other entity can be accessing the object:
+
+static void obj_list_add(struct obj *obj)
+{
+	obj->active = 1;
+	list_add(&obj->list);
+}
+
+static void obj_list_del(struct obj *obj)
+{
+	list_del(&obj->list);
+	obj->active = 0;
+}
+
+static void obj_destroy(struct obj *obj)
+{
+	BUG_ON(obj->active);
+	kfree(obj);
+}
+
+struct obj *obj_list_peek(struct list_head *head)
+{
+	if (!list_empty(head)) {
+		struct obj *obj;
+
+		obj = list_entry(head->next, struct obj, list);
+		atomic_inc(&obj->refcnt);
+		return obj;
+	}
+	return NULL;
+}
+
+void obj_poke(void)
+{
+	struct obj *obj;
+
+	spin_lock(&global_list_lock);
+	obj = obj_list_peek(&global_list);
+	spin_unlock(&global_list_lock);
+
+	if (obj) {
+		obj->ops->poke(obj);
+		if (atomic_dec_and_test(&obj->refcnt))
+			obj_destroy(obj);
+	}
+}
+
+void obj_timeout(struct obj *obj)
+{
+	spin_lock(&global_list_lock);
+	obj_list_del(obj);
+	spin_unlock(&global_list_lock);
+
+	if (atomic_dec_and_test(&obj->refcnt))
+		obj_destroy(obj);
+}
+
+(This is a simplification of the ARP queue management in the
+ generic neighbour discover code of the networking.  Olaf Kirch
+ found a bug wrt. memory barriers in kfree_skb() that exposed
+ the atomic_t memory barrier requirements quite clearly.)
+
+Given the above scheme, it must be the case that the obj->active
+update done by the obj list deletion be visible to other processors
+before the atomic counter decrement is performed.
+
+Otherwise, the counter could fall to zero, yet obj->active would still
+be set, thus triggering the assertion in obj_destroy().  The error
+sequence looks like this:
+
+	cpu 0				cpu 1
+	obj_poke()			obj_timeout()
+	obj = obj_list_peek();
+	... gains ref to obj, refcnt=2
+					obj_list_del(obj);
+					obj->active = 0 ...
+					... visibility delayed ...
+					atomic_dec_and_test()
+					... refcnt drops to 1 ...
+	atomic_dec_and_test()
+	... refcount drops to 0 ...
+	obj_destroy()
+	BUG() triggers since obj->active
+	still seen as one
+					obj->active update visibility occurs
+
+With the memory barrier semantics required of the atomic_t operations
+which return values, the above sequence of memory visibility can never
+happen.  Specifically, in the above case the atomic_dec_and_test()
+counter decrement would not become globally visible until the
+obj->active update does.
+
+As a historical note, 32-bit Sparc used to only allow usage of
+24-bits of it's atomic_t type.  This was because it used 8 bits
+as a spinlock for SMP safety.  Sparc32 lacked a "compare and swap"
+type instruction.  However, 32-bit Sparc has since been moved over
+to a "hash table of spinlocks" scheme, that allows the full 32-bit
+counter to be realized.  Essentially, an array of spinlocks are
+indexed into based upon the address of the atomic_t being operated
+on, and that lock protects the atomic operation.  Parisc uses the
+same scheme.
+
+Another note is that the atomic_t operations returning values are
+extremely slow on an old 386.
+
+We will now cover the atomic bitmask operations.  You will find that
+their SMP and memory barrier semantics are similar in shape and scope
+to the atomic_t ops above.
+
+Native atomic bit operations are defined to operate on objects aligned
+to the size of an "unsigned long" C data type, and are least of that
+size.  The endianness of the bits within each "unsigned long" are the
+native endianness of the cpu.
+
+	void set_bit(unsigned long nr, volatils unsigned long *addr);
+	void clear_bit(unsigned long nr, volatils unsigned long *addr);
+	void change_bit(unsigned long nr, volatils unsigned long *addr);
+
+These routines set, clear, and change, respectively, the bit number
+indicated by "nr" on the bit mask pointed to by "ADDR".
+
+They must execute atomically, yet there are no implicit memory barrier
+semantics required of these interfaces.
+
+	int test_and_set_bit(unsigned long nr, volatils unsigned long *addr);
+	int test_and_clear_bit(unsigned long nr, volatils unsigned long *addr);
+	int test_and_change_bit(unsigned long nr, volatils unsigned long *addr);
+
+Like the above, except that these routines return a boolean which
+indicates whether the changed bit was set _BEFORE_ the atomic bit
+operation.
+
+WARNING! It is incredibly important that the value be a boolean,
+ie. "0" or "1".  Do not try to be fancy and save a few instructions by
+declaring the above to return "long" and just returning something like
+"old_val & mask" because that will not work.
+
+For one thing, this return value gets truncated to int in many code
+paths using these interfaces, so on 64-bit if the bit is set in the
+upper 32-bits then testers will never see that.
+
+One great example of where this problem crops up are the thread_info
+flag operations.  Routines such as test_and_set_ti_thread_flag() chop
+the return value into an int.  There are other places where things
+like this occur as well.
+
+These routines, like the atomic_t counter operations returning values,
+require explicit memory barrier semantics around their execution.  All
+memory operations before the atomic bit operation call must be made
+visible globally before the atomic bit operation is made visible.
+Likewise, the atomic bit operation must be visible globally before any
+subsequent memory operation is made visible.  For example:
+
+	obj->dead = 1;
+	if (test_and_set_bit(0, &obj->flags))
+		/* ... */;
+	obj->killed = 1;
+
+The implementation of test_and_set_bit() must guarentee that
+"obj->dead = 1;" is visible to cpus before the atomic memory operation
+done by test_and_set_bit() becomes visible.  Likewise, the atomic
+memory operation done by test_and_set_bit() must become visible before
+"obj->killed = 1;" is visible.
+
+Finally there is the basic operation:
+
+	int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
+
+Which returns a boolean indicating if bit "nr" is set in the bitmask
+pointed to by "addr".
+
+If explicit memory barriers are required around clear_bit() (which
+does not return a value, and thus does not need to provide memory
+barrier semantics), two interfaces are provided:
+
+	void smp_mb__before_clear_bit(void);
+	void smp_mb__after_clear_bit(void);
+
+They are used as follows, and are akin to their atomic_t operation
+brothers:
+
+	/* All memory operations before this call will
+	 * be globally visible before the clear_bit().
+	 */
+	smp_mb__before_clear_bit();
+	clear_bit( ... );
+
+	/* The clear_bit() will be visible before all
+	 * subsequent memory operations.
+	 */
+	 smp_mb__after_clear_bit();
+
+Finally, there are non-atomic versions of the bitmask operations
+provided.  They are used in contexts where some other higher-level SMP
+locking scheme is being used to protect the bitmask, and thus less
+expensive non-atomic operations may be used in the implementation.
+They have names similar to the above bitmask operation interfaces,
+except that two underscores are prefixed to the interface name.
+
+	void __set_bit(unsigned long nr, volatile unsigned long *addr);
+	void __clear_bit(unsigned long nr, volatile unsigned long *addr);
+	void __change_bit(unsigned long nr, volatile unsigned long *addr);
+	int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
+	int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
+	int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
+
+These non-atomic variants also do not require any special memory
+barrier semantics.
+
+The routines xchg() and cmpxchg() need the same exact memory barriers
+as the atomic and bit operations returning values.
+
+Spinlocks and rwlocks have memory barrier expectations as well.
+The rule to follow is simple:
+
+1) When acquiring a lock, the implementation must make it globally
+   visible before any subsequent memory operation.
+
+2) When releasing a lock, the implementation must make it such that
+   all previous memory operations are globally visible before the
+   lock release.
+
+Which finally brings us to _atomic_dec_and_lock().  There is an
+architecture-neutral version implemented in lib/dec_and_lock.c,
+but most platforms will wish to optimize this in assembler.
+
+	int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
+
+Atomically decrement the given counter, and if will drop to zero
+atomically acquire the given spinlock and perform the decrement
+of the counter to zero.  If it does not drop to zero, do nothing
+with the spinlock.
+
+It is actually pretty simple to get the memory barrier correct.
+Simply satisfy the spinlock grab requirements, which is make
+sure the spinlock operation is globally visible before any
+subsequent memory operation.
+
+We can demonstrate this operation more clearly if we define
+an abstract atomic operation:
+
+	long cas(long *mem, long old, long new);
+
+"cas" stands for "compare and swap".  It atomically:
+
+1) Compares "old" with the value currently at "mem".
+2) If they are equal, "new" is written to "mem".
+3) Regardless, the current value at "mem" is returned.
+
+As an example usage, here is what an atomic counter update
+might look like:
+
+void example_atomic_inc(long *counter)
+{
+	long old, new, ret;
+
+	while (1) {
+		old = *counter;
+		new = old + 1;
+
+		ret = cas(counter, old, new);
+		if (ret == old)
+			break;
+	}
+}
+
+Let's use cas() in order to build a pseudo-C atomic_dec_and_lock():
+
+int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
+{
+	long old, new, ret;
+	int went_to_zero;
+
+	went_to_zero = 0;
+	while (1) {
+		old = atomic_read(atomic);
+		new = old - 1;
+		if (new == 0) {
+			went_to_zero = 1;
+			spin_lock(lock);
+		}
+		ret = cas(atomic, old, new);
+		if (ret == old)
+			break;
+		if (went_to_zero) {
+			spin_unlock(lock);
+			went_to_zero = 0;
+		}
+	}
+
+	return went_to_zero;
+}
+
+Now, as far as memory barriers go, as long as spin_lock()
+strictly orders all subsequent memory operations (including
+the cas()) with respect to itself, things will be fine.
+
+Said another way, _atomic_dec_and_lock() must guarentee that
+a counter dropping to zero is never made visible before the
+spinlock being acquired.
+
+Note that this also means that for the case where the counter
+is not dropping to zero, there are no memory ordering
+requirements.
diff -Nru a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
--- a/Documentation/filesystems/proc.txt	2004-10-28 00:39:48 -07:00
+++ b/Documentation/filesystems/proc.txt	2005-02-02 12:43:48 -08:00
@@ -1709,12 +1709,13 @@
 
 Writing to this file results in a flush of the routing cache.
 
-gc_elasticity, gc_interval, gc_min_interval, gc_tresh, gc_timeout,
-gc_thresh, gc_thresh1, gc_thresh2, gc_thresh3
---------------------------------------------------------------
+gc_elasticity, gc_interval, gc_min_interval_ms, gc_timeout, gc_thresh
+---------------------------------------------------------------------
 
 Values to  control  the  frequency  and  behavior  of  the  garbage collection
-algorithm for the routing cache.
+algorithm for the routing cache. gc_min_interval is deprecated and replaced
+by gc_min_interval_ms.
+
 
 max_size
 --------
diff -Nru a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
--- a/Documentation/kernel-parameters.txt	2005-02-02 16:21:28 -08:00
+++ b/Documentation/kernel-parameters.txt	2005-02-02 22:19:14 -08:00
@@ -1363,9 +1363,6 @@
 	tipar.delay=	[HW,PPT]
 			Set inter-bit delay in microseconds (default 10).
 
-	tiusb=		[HW,USB] Texas Instruments' USB GraphLink (aka SilverLink)
-			Format: <timeout>
- 
 	tmc8xx=		[HW,SCSI]
 			See header of drivers/scsi/seagate.c.
 
diff -Nru a/Documentation/nommu-mmap.txt b/Documentation/nommu-mmap.txt
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/Documentation/nommu-mmap.txt	2005-02-08 05:51:44 -08:00
@@ -0,0 +1,141 @@
+			 =============================
+			 NO-MMU MEMORY MAPPING SUPPORT
+			 =============================
+
+The kernel has limited support for memory mapping under no-MMU conditions, such
+as are used in uClinux environments. From the userspace point of view, memory
+mapping is made use of in conjunction with the mmap() system call, the shmat()
+call and the execve() system call. From the kernel's point of view, execve()
+mapping is actually performed by the binfmt drivers, which call back into the
+mmap() routines to do the actual work.
+
+Memory mapping behaviour also involves the way fork(), vfork(), clone() and
+ptrace() work. Under uClinux there is no fork(), and clone() must be supplied
+the CLONE_VM flag.
+
+The behaviour is similar between the MMU and no-MMU cases, but not identical;
+and it's also much more restricted in the latter case:
+
+ (*) Anonymous mapping, MAP_PRIVATE
+
+	In the MMU case: VM regions backed by arbitrary pages; copy-on-write
+	across fork.
+
+	In the no-MMU case: VM regions backed by arbitrary contiguous runs of
+	pages.
+
+ (*) Anonymous mapping, MAP_SHARED
+
+	These behave very much like private mappings, except that they're
+	shared across fork() or clone() without CLONE_VM in the MMU case. Since
+	the no-MMU case doesn't support these, behaviour is identical to
+	MAP_PRIVATE there.
+
+ (*) File, MAP_PRIVATE, PROT_READ / PROT_EXEC, !PROT_WRITE
+
+	In the MMU case: VM regions backed by pages read from file; changes to
+	the underlying file are reflected in the mapping; copied across fork.
+
+	In the no-MMU case: VM regions backed by arbitrary contiguous runs of
+	pages into which the appropriate bit of the file is read; any remaining
+	bit of the mapping is cleared; such mappings are shared if possible;
+	writes to the file do not affect the mapping; writes to the mapping are
+	visible in other processes (no MMU protection), but should not happen.
+
+ (*) File, MAP_PRIVATE, PROT_READ / PROT_EXEC, PROT_WRITE
+
+	In the MMU case: like the non-PROT_WRITE case, except that the pages in
+	question get copied before the write actually happens. From that point
+	on writes to that page in the file no longer get reflected into the
+	mapping's backing pages.
+
+	In the no-MMU case: works exactly as for the non-PROT_WRITE case.
+
+ (*) Regular file / blockdev, MAP_SHARED, PROT_READ / PROT_EXEC / PROT_WRITE
+
+	In the MMU case: VM regions backed by pages read from file; changes to
+	pages written back to file; writes to file reflected into pages backing
+	mapping; shared across fork.
+
+	In the no-MMU case: not supported.
+
+ (*) Memory backed regular file, MAP_SHARED, PROT_READ / PROT_EXEC / PROT_WRITE
+
+	In the MMU case: As for ordinary regular files.
+
+	In the no-MMU case: The filesystem providing the memory-backed file
+	(such as ramfs or tmpfs) may choose to honour an open, truncate, mmap
+	sequence by providing a contiguous sequence of pages to map. In that
+	case, a shared-writable memory mapping will be possible. It will work
+	as for the MMU case. If the filesystem does not provide any such
+	support, then the mapping request will be denied.
+
+ (*) Memory backed chardev, MAP_SHARED, PROT_READ / PROT_EXEC / PROT_WRITE
+
+	In the MMU case: As for ordinary regular files.
+
+	In the no-MMU case: The character device driver may choose to honour
+	the mmap() by providing direct access to the underlying device if it
+	provides memory or quasi-memory that can be accessed directly. Examples
+	of such are frame buffers and flash devices. If the driver does not
+	provide any such support, then the mapping request will be denied.
+
+
+============================
+FURTHER NOTES ON NO-MMU MMAP
+============================
+
+ (*) A request for a private mapping of less than a page in size may not return
+     a page-aligned buffer. This is because the kernel calls kmalloc() to
+     allocate the buffer, not get_free_page().
+
+ (*) A list of all the mappings on the system is visible through /proc/maps in
+     no-MMU mode.
+
+ (*) Supplying MAP_FIXED or a requesting a particular mapping address will
+     result in an error.
+
+ (*) Files mapped privately must have a read method provided by the driver or
+     filesystem so that the contents can be read into the memory allocated. An
+     error will result if they don't. This is most likely to be encountered
+     with character device files, pipes, fifos and sockets.
+
+
+============================================
+PROVIDING SHAREABLE CHARACTER DEVICE SUPPORT
+============================================
+
+To provide shareable character device support, a driver must provide a
+file->f_op->get_unmapped_area() operation. The mmap() routines will call this
+to get a proposed address for the mapping. This may return an error if it
+doesn't wish to honour the mapping because it's too long, at a weird offset,
+under some unsupported combination of flags or whatever.
+
+The vm_ops->close() routine will be invoked when the last mapping on a chardev
+is removed. An existing mapping will be shared, partially or not, if possible
+without notifying the driver.
+
+It is permitted also for the file->f_op->get_unmapped_area() operation to
+return -ENOSYS. This will be taken to mean that this operation just doesn't
+want to handle it, despite the fact it's got an operation. For instance, it
+might try directing the call to a secondary driver which turns out not to
+implement it. Such is the case for the framebuffer driver which attempts to
+direct the call to the device-specific driver.
+
+
+==============================================
+PROVIDING SHAREABLE MEMORY-BACKED FILE SUPPORT
+==============================================
+
+Provision of shared mappings on memory backed files is similar to the provision
+of support for shared mapped character devices. The main difference is that the
+filesystem providing the service will probably allocate a contiguous collection
+of pages and permit mappings to be made on that.
+
+It is recommended that a truncate operation applied to such a file that
+increases the file size, if that file is empty, be taken as a request to gather
+enough pages to honour a mapping. This is required to support POSIX shared
+memory.
+
+Memory backed devices are indicated by the mapping's backing device info having
+the memory_backed flag set.
diff -Nru a/Documentation/usb/silverlink.txt b/Documentation/usb/silverlink.txt
--- a/Documentation/usb/silverlink.txt	2004-09-26 06:16:15 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------
-Readme for Linux device driver for the Texas Instruments SilverLink cable
-and direct USB cable provided by some TI's handhelds.
--------------------------------------------------------------------------
-
-Author: Romain Liévin & Julien Blache
-Homepage: http://lpg.ticalc.org/prj_usb
-
-INTRODUCTION:
-
-This is a driver for the TI-GRAPH LINK USB (aka SilverLink) cable, a cable 
-designed by TI for connecting their TI8x/9x calculators to a computer 
-(PC or Mac usually). It has been extended to support the USB port offered by
-some latest TI handhelds (TI84+ and TI89 Titanium).
-
-If you need more information, please visit the 'SilverLink drivers' homepage 
-at the above URL.
-
-WHAT YOU NEED:
-
-A TI calculator of course and a program capable to communicate with your 
-calculator.
-TiLP will work for sure (since I am his developer !). yal92 may be able to use
-it by changing tidev for tiglusb (may require some hacking...).
-
-HOW TO USE IT:
-
-You must have first compiled USB support, support for your specific USB host
-controller (UHCI or OHCI).
-
-Next, (as root) from your appropriate modules directory (lib/modules/2.5.XX):
-
-       insmod usb/usbcore.o
-       insmod usb/usb-uhci.o  <OR>  insmod usb/ohci-hcd.o
-       insmod tiglusb.o
-
-If it is not already there (it usually is), create the device:
-
-       mknod /dev/tiglusb0 c 115 16
-
-You will have to set permissions on this device to allow you to read/write
-from it:
-
-       chmod 666 /dev/tiglusb0
-       
-Now you are ready to run a linking program such as TiLP. Be sure to configure 
-it properly (RTFM).
-       
-MODULE PARAMETERS:
-
-  You can set these with:  insmod tiglusb NAME=VALUE
-  There is currently no way to set these on a per-cable basis.
-
-  NAME: timeout
-  TYPE: integer
-  DEFAULT: 15
-  DESC: Timeout value in tenth of seconds. If no data is available once this 
-       time has expired then the driver will return with a timeout error.
-
-QUIRKS:
-
-The following problem seems to be specific to the link cable since it appears 
-on all platforms (Linux, Windows, Mac OS-X). 
-
-In some very particular cases, the driver returns with success but
-without any data. The application should retry a read operation at least once.
-
-HOW TO CONTACT US:
-
-You can email me at roms@lpg.ticalc.org. Please prefix the subject line
-with "TIGLUSB: " so that I am certain to notice your message.
-You can also mail JB at jb@jblache.org: he has written the first release of 
-this driver but he better knows the Mac OS-X driver.
-
-CREDITS:
-
-The code is based on dabusb.c, printer.c and scanner.c !
-The driver has been developed independently of Texas Instruments Inc.
diff -Nru a/MAINTAINERS b/MAINTAINERS
--- a/MAINTAINERS	2005-02-01 08:48:42 -08:00
+++ b/MAINTAINERS	2005-02-04 09:47:42 -08:00
@@ -749,7 +749,7 @@
 
 DRIVER CORE, KOBJECTS, AND SYSFS
 P:	Greg Kroah-Hartman
-M:	greg@kroah.com
+M:	gregkh@suse.de
 L:	linux-kernel@vger.kernel.org
 S:	Supported
 
@@ -1744,13 +1744,14 @@
 
 PCI SUBSYSTEM
 P:	Greg Kroah-Hartman
-M:	greg@kroah.com
+M:	gregkh@suse.de
 L:	linux-kernel@vger.kernel.org
+L:	linux-pci@atrey.karlin.mff.cuni.cz
 S:	Supported
 
 PCI HOTPLUG CORE
 P:	Greg Kroah-Hartman
-M:	greg@kroah.com
+M:	gregkh@suse.de
 S:	Supported
 
 PCI HOTPLUG COMPAQ DRIVER
@@ -2184,13 +2185,6 @@
 M:	hch@infradead.org
 S:	Maintained
 
-TI GRAPH LINK USB (SilverLink) CABLE DRIVER
-P:	Romain Lievin
-M:	roms@lpg.ticalc.org
-P:	Julien Blache
-M:	jb@technologeek.org
-S:	Maintained
-
 TI PARALLEL LINK CABLE DRIVER
 P:     Romain Lievin
 M:     roms@lpg.ticalc.org
@@ -2392,11 +2386,10 @@
 
 USB SERIAL DRIVER
 P:	Greg Kroah-Hartman
-M:	greg@kroah.com
+M:	gregkh@suse.de
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
-S:	Maintained
-W:	http://www.kroah.com/linux-usb/
+S:	Supported
 
 USB SERIAL BELKIN F5U103 DRIVER
 P:	William Greathouse
@@ -2458,7 +2451,7 @@
 
 USB SUBSYSTEM
 P:	Greg Kroah-Hartman
-M:	greg@kroah.com
+M:	gregkh@suse.de
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
 W:	http://www.linux-usb.org
diff -Nru a/Makefile b/Makefile
--- a/Makefile	2005-02-02 17:50:51 -08:00
+++ b/Makefile	2005-02-10 05:39:34 -08:00
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 11
-EXTRAVERSION =-rc3
+EXTRAVERSION = -rc3-bk7
 NAME=Woozy Numbat
 
 # *DOCUMENTATION*
diff -Nru a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
--- a/arch/arm/kernel/calls.S	2005-01-31 16:00:00 -08:00
+++ b/arch/arm/kernel/calls.S	2005-02-02 16:00:00 -08:00
@@ -134,7 +134,7 @@
 		.long	sys_ipc
 		.long	sys_fsync
 		.long	sys_sigreturn_wrapper
-/* 120 */	.long	sys_clone_wapper
+/* 120 */	.long	sys_clone_wrapper
 		.long	sys_setdomainname
 		.long	sys_newuname
 		.long	sys_ni_syscall
@@ -254,7 +254,7 @@
 		.long	sys_fremovexattr
 		.long	sys_tkill
 		.long	sys_sendfile64
-/* 240 */	.long	sys_futex
+/* 240 */	.long	sys_futex_wrapper
 		.long	sys_sched_setaffinity
 		.long	sys_sched_getaffinity
 		.long	sys_io_setup
diff -Nru a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
--- a/arch/arm/kernel/entry-common.S	2005-01-31 16:00:00 -08:00
+++ b/arch/arm/kernel/entry-common.S	2005-02-02 16:00:00 -08:00
@@ -11,6 +11,7 @@
 
 #include <asm/thread_info.h>
 #include <asm/ptrace.h>
+#include <asm/unistd.h>
 
 #include "entry-header.S"
 
@@ -190,13 +191,14 @@
 		.type	sys_syscall, #function
 sys_syscall:
 		eor	scno, r0, #OS_NUMBER << 20
-		cmp	scno, #NR_syscalls	@ check range
-		stmleia	sp, {r5, r6}		@ shuffle args
-		movle	r0, r1
-		movle	r1, r2
-		movle	r2, r3
-		movle	r3, r4
-		ldrle	pc, [tbl, scno, lsl #2]
+		cmp	scno, #__NR_syscall - __NR_SYSCALL_BASE
+		cmpne	scno, #NR_syscalls	@ check range
+		stmloia	sp, {r5, r6}		@ shuffle args
+		movlo	r0, r1
+		movlo	r1, r2
+		movlo	r2, r3
+		movlo	r3, r4
+		ldrlo	pc, [tbl, scno, lsl #2]
 		b	sys_ni_syscall
 
 sys_fork_wrapper:
@@ -211,7 +213,7 @@
 		add	r3, sp, #S_OFF
 		b	sys_execve
 
-sys_clone_wapper:
+sys_clone_wrapper:
 		add	ip, sp, #S_OFF
 		str	ip, [sp, #4]
 		b	sys_clone
@@ -235,6 +237,10 @@
 sys_sigaltstack_wrapper:
 		ldr	r2, [sp, #S_OFF + S_SP]
 		b	do_sigaltstack
+
+sys_futex_wrapper:
+		str	r5, [sp, #4]		@ push sixth arg
+		b	sys_futex
 
 /*
  * Note: off_4k (r5) is always units of 4K.  If we can't do the requested
diff -Nru a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
--- a/arch/arm/mach-pxa/lubbock.c	2004-11-22 11:09:18 -08:00
+++ b/arch/arm/mach-pxa/lubbock.c	2005-02-06 14:53:57 -08:00
@@ -29,12 +29,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <asm/hardware/sa1111.h>
+
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/mmc.h>
-#include <asm/hardware/sa1111.h>
 
 #include "generic.h"
 
diff -Nru a/arch/arm/mm/tlb-v4.S b/arch/arm/mm/tlb-v4.S
--- a/arch/arm/mm/tlb-v4.S	2003-09-19 06:48:38 -07:00
+++ b/arch/arm/mm/tlb-v4.S	2005-02-04 19:55:45 -08:00
@@ -44,7 +44,7 @@
 	mov	pc, lr
 
 /*
- *	v4_flush_kerm_tlb_range(start, end)
+ *	v4_flush_kern_tlb_range(start, end)
  *
  *	Invalidate a range of TLB entries in the specified kernel
  *	address range.
diff -Nru a/arch/arm/mm/tlb-v4wb.S b/arch/arm/mm/tlb-v4wb.S
--- a/arch/arm/mm/tlb-v4wb.S	2003-09-19 06:48:38 -07:00
+++ b/arch/arm/mm/tlb-v4wb.S	2005-02-04 19:55:54 -08:00
@@ -47,7 +47,7 @@
 	mov	pc, lr
 
 /*
- *	v4_flush_kerm_tlb_range(start, end)
+ *	v4_flush_kern_tlb_range(start, end)
  *
  *	Invalidate a range of TLB entries in the specified kernel
  *	address range.
diff -Nru a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
--- a/arch/frv/kernel/entry.S	2005-01-15 14:01:52 -08:00
+++ b/arch/frv/kernel/entry.S	2005-02-04 07:30:45 -08:00
@@ -782,13 +782,12 @@
 ###############################################################################
 #
 # the return path for a newly forked child process
-# - __switch_to() saved the old current pointer in GR27 for us
+# - __switch_to() saved the old current pointer in GR8 for us
 #
 ###############################################################################
 	.globl		ret_from_fork
 ret_from_fork:
 	LEDS		0x6100
-	ori.p		gr27,0,gr8
 	call		schedule_tail
 
 	# fork & co. return 0 to child
diff -Nru a/arch/frv/kernel/irq-routing.c b/arch/frv/kernel/irq-routing.c
--- a/arch/frv/kernel/irq-routing.c	2005-01-04 18:48:04 -08:00
+++ b/arch/frv/kernel/irq-routing.c	2005-02-04 04:36:46 -08:00
@@ -82,7 +82,7 @@
 			int status = 0;
 
 //			if (!(action->flags & SA_INTERRUPT))
-//				sti();
+//				local_irq_enable();
 
 			do {
 				status |= action->flags;
@@ -92,7 +92,7 @@
 
 			if (status & SA_SAMPLE_RANDOM)
 				add_interrupt_randomness(irq);
-			cli();
+			local_irq_disable();
 		}
 	}
 }
diff -Nru a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
--- a/arch/frv/kernel/irq.c	2005-01-20 21:00:22 -08:00
+++ b/arch/frv/kernel/irq.c	2005-02-04 04:36:25 -08:00
@@ -316,16 +316,16 @@
 			do_softirq();
 
 #ifdef CONFIG_PREEMPT
-	cli();
+	local_irq_disable();
 	while (--current->preempt_count == 0) {
-		if (!(__frame->psr & PSR_S)
-		    || (current->need_resched == 0)
-		    || in_interrupt())
+		if (!(__frame->psr & PSR_S) ||
+		    current->need_resched == 0 ||
+		    in_interrupt())
 			break;
 		current->preempt_count++;
-		sti();
+		local_irq_enable();
 		preempt_schedule();
-		cli();
+		local_irq_disable();
 	}
 #endif
 
diff -Nru a/arch/frv/kernel/pm.c b/arch/frv/kernel/pm.c
--- a/arch/frv/kernel/pm.c	2005-01-04 18:48:04 -08:00
+++ b/arch/frv/kernel/pm.c	2005-02-05 15:25:44 -08:00
@@ -36,7 +36,7 @@
 
 int pm_do_suspend(void)
 {
-	cli();
+	local_irq_disable();
 
 	__set_LEDS(0xb1);
 
@@ -45,7 +45,7 @@
 
 	__set_LEDS(0xb2);
 
-	sti();
+	local_irq_enable();
 
 	return 0;
 }
@@ -84,7 +84,7 @@
 
 int pm_do_bus_sleep(void)
 {
-	cli();
+	local_irq_disable();
 
 	/*
          * Here is where we need some platform-dependent setup
@@ -113,7 +113,7 @@
 	 */
 	__power_switch_wake_cleanup();
 
-	sti();
+	local_irq_enable();
 
 	return 0;
 }
@@ -134,7 +134,7 @@
 #define CTL_PM_P0 4
 #define CTL_PM_CM 5
 
-static int user_atoi(char *ubuf, int len)
+static int user_atoi(char *ubuf, size_t len)
 {
 	char buf[16];
 	unsigned long ret;
@@ -191,7 +191,7 @@
 	pm_send_all(PM_SUSPEND, (void *)3);
 
 	/* now change cmode */
-	cli();
+	local_irq_disable();
 	frv_dma_pause_all();
 
 	frv_change_cmode(new_cmode);
@@ -203,7 +203,7 @@
 	determine_clocks(1);
 #endif
 	frv_dma_resume_all();
-	sti();
+	local_irq_enable();
 
 	/* tell all the drivers we're resuming */
 	pm_send_all(PM_RESUME, (void *)0);
diff -Nru a/arch/frv/kernel/semaphore.c b/arch/frv/kernel/semaphore.c
--- a/arch/frv/kernel/semaphore.c	2005-01-04 18:48:04 -08:00
+++ b/arch/frv/kernel/semaphore.c	2005-02-04 04:34:46 -08:00
@@ -43,17 +43,18 @@
 	struct task_struct *tsk = current;
 	struct sem_waiter waiter;
 
-	semtrace(sem,"Entering __down");
+	semtrace(sem, "Entering __down");
 
 	/* set up my own style of waitqueue */
-	waiter.task	= tsk;
+	waiter.task = tsk;
+	get_task_struct(tsk);
 
 	list_add_tail(&waiter.list, &sem->wait_list);
 
 	/* we don't need to touch the semaphore struct anymore */
 	spin_unlock_irqrestore(&sem->wait_lock, flags);
 
-	/* wait to be given the lock */
+	/* wait to be given the semaphore */
 	set_task_state(tsk, TASK_UNINTERRUPTIBLE);
 
 	for (;;) {
@@ -64,7 +65,7 @@
 	}
 
 	tsk->state = TASK_RUNNING;
-	semtrace(sem,"Leaving __down");
+	semtrace(sem, "Leaving __down");
 }
 
 EXPORT_SYMBOL(__down);
@@ -83,6 +84,7 @@
 
 	/* set up my own style of waitqueue */
 	waiter.task = tsk;
+	get_task_struct(tsk);
 
 	list_add_tail(&waiter.list, &sem->wait_list);
 
@@ -91,7 +93,7 @@
 
 	spin_unlock_irqrestore(&sem->wait_lock, flags);
 
-	/* wait to be given the lock */
+	/* wait to be given the semaphore */
 	ret = 0;
 	for (;;) {
 		if (list_empty(&waiter.list))
@@ -116,6 +118,8 @@
 	}
 
 	spin_unlock_irqrestore(&sem->wait_lock, flags);
+	if (ret == -EINTR)
+		put_task_struct(current);
 	goto out;
 }
 
@@ -127,14 +131,24 @@
  */
 void __up(struct semaphore *sem)
 {
+	struct task_struct *tsk;
 	struct sem_waiter *waiter;
 
 	semtrace(sem,"Entering __up");
 
 	/* grant the token to the process at the front of the queue */
 	waiter = list_entry(sem->wait_list.next, struct sem_waiter, list);
+
+	/* We must be careful not to touch 'waiter' after we set ->task = NULL.
+	 * It is an allocated on the waiter's stack and may become invalid at
+	 * any time after that point (due to a wakeup from another source).
+	 */
 	list_del_init(&waiter->list);
-	wake_up_process(waiter->task);
+	tsk = waiter->task;
+	mb();
+	waiter->task = NULL;
+	wake_up_process(tsk);
+	put_task_struct(tsk);
 
 	semtrace(sem,"Leaving __up");
 }
diff -Nru a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
--- a/arch/frv/kernel/switch_to.S	2005-01-04 18:48:04 -08:00
+++ b/arch/frv/kernel/switch_to.S	2005-02-04 07:31:14 -08:00
@@ -43,20 +43,22 @@
 
 ###############################################################################
 #
-# struct task_struct *__switch_to(struct thread_struct *prev, struct thread_struct *next)
+# struct task_struct *__switch_to(struct thread_struct *prev_thread,
+#				  struct thread_struct *next_thread,
+#				  struct task_struct *prev)
 #
 ###############################################################################
 	.globl		__switch_to
 __switch_to:
 	# save outgoing process's context
-	sethi.p		%hi(__switch_back),gr11
-	setlo		%lo(__switch_back),gr11
-	movsg		lr,gr10
+	sethi.p		%hi(__switch_back),gr13
+	setlo		%lo(__switch_back),gr13
+	movsg		lr,gr12
 
 	stdi		gr28,@(gr8,#__THREAD_FRAME)
 	sti		sp  ,@(gr8,#__THREAD_SP)
 	sti		fp  ,@(gr8,#__THREAD_FP)
-	stdi		gr10,@(gr8,#__THREAD_LR)
+	stdi		gr12,@(gr8,#__THREAD_LR)
 	stdi		gr16,@(gr8,#__THREAD_GR(16))
 	stdi		gr18,@(gr8,#__THREAD_GR(18))
 	stdi		gr20,@(gr8,#__THREAD_GR(20))
@@ -68,14 +70,14 @@
 	ldi.p		@(gr8,#__THREAD_USER),gr8
 	call		save_user_regs
 	or		gr22,gr22,gr8
-
+	
 	# retrieve the new context
 	sethi.p		%hi(__kernel_frame0_ptr),gr6
 	setlo		%lo(__kernel_frame0_ptr),gr6
 	movsg		psr,gr4
 
 	lddi.p		@(gr9,#__THREAD_FRAME),gr10
-	or		gr29,gr29,gr27		; ret_from_fork needs to know old current
+	or		gr10,gr10,gr27		; save prev for the return value
 
 	ldi		@(gr11,#4),gr19		; get new_current->thread_info
 
@@ -88,8 +90,8 @@
 	andi		gr4,#~PSR_ET,gr5
 	movgs		gr5,psr
 
-	or.p		gr10,gr0,gr28
-	or		gr11,gr0,gr29
+	or.p		gr10,gr0,gr28		; set __frame
+	or		gr11,gr0,gr29		; set __current
 	or.p		gr12,gr0,sp
 	or		gr13,gr0,fp
 	or		gr19,gr0,gr15		; set __current_thread_info
@@ -108,14 +110,17 @@
 111:
 
 	# jump to __switch_back or ret_from_fork as appropriate
+	# - move prev to GR8
 	movgs		gr4,psr
-	jmpl		@(gr18,gr0)
+	jmpl.p		@(gr18,gr0)
+	or		gr27,gr27,gr8
 
 ###############################################################################
 #
 # restore incoming process's context
 # - on entry:
 #   - SP, FP, LR, GR15, GR28 and GR29 will have been set up appropriately
+#   - GR8 will point to the outgoing task_struct
 #   - GR9 will point to the incoming thread_struct
 #
 ###############################################################################
@@ -128,12 +133,16 @@
 	lddi		@(gr9,#__THREAD_GR(26)),gr26
 
 	# fall through into restore_user_regs()
-	ldi		@(gr9,#__THREAD_USER),gr8
+	ldi.p		@(gr9,#__THREAD_USER),gr8
+	or		gr8,gr8,gr9
 
 ###############################################################################
 #
 # restore extra general regs and FP/Media regs
-# - void restore_user_regs(const struct user_context *target)
+# - void *restore_user_regs(const struct user_context *target, void *retval)
+# - on entry:
+#   - GR8 will point to the user context to swap in
+#   - GR9 will contain the value to be returned in GR8 (prev task on context switch)
 #
 ###############################################################################
 	.globl		restore_user_regs
@@ -245,6 +254,7 @@
 	lddi		@(gr8,#__FPMEDIA_FNER(0)),gr4
 	movsg		fner0,gr4
 	movsg		fner1,gr5
+	or.p		gr9,gr9,gr8
 	bralr
 
 	# the FR451 also has ACC8-11/ACCG8-11 regs (but not 4-7...)
diff -Nru a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
--- a/arch/frv/kernel/vmlinux.lds.S	2005-01-04 18:48:03 -08:00
+++ b/arch/frv/kernel/vmlinux.lds.S	2005-02-04 04:35:19 -08:00
@@ -1,4 +1,4 @@
-/* ld script to make FRV Linux kernel -*- c -*-
+/* ld script to make FRV Linux kernel
  * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>;
  */
 OUTPUT_FORMAT("elf32-frv", "elf32-frv", "elf32-frv")
diff -Nru a/arch/i386/crypto/aes.c b/arch/i386/crypto/aes.c
--- a/arch/i386/crypto/aes.c	2004-08-06 08:02:25 -07:00
+++ b/arch/i386/crypto/aes.c	2005-02-06 22:11:37 -08:00
@@ -93,12 +93,12 @@
 
 u32 ft_tab[4][256];
 u32 fl_tab[4][256];
-u32 ls_tab[4][256];
-u32 im_tab[4][256];
+static u32 ls_tab[4][256];
+static u32 im_tab[4][256];
 u32 il_tab[4][256];
 u32 it_tab[4][256];
 
-void gen_tabs(void)
+static void gen_tabs(void)
 {
 	u32 i, w;
 	u8 pow[512], log[256];
diff -Nru a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c	2004-10-27 15:20:19 -07:00
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c	2005-02-05 12:51:44 -08:00
@@ -160,7 +160,10 @@
 		printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
 
 	/* Multiplier. */
-	mult = msr_lo >> 24;
+	if (c->x86_model < 2)
+		mult = msr_lo >> 27;
+	else
+		mult = msr_lo >> 24;
 
 	dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
 
diff -Nru a/arch/i386/kernel/time_hpet.c b/arch/i386/kernel/time_hpet.c
--- a/arch/i386/kernel/time_hpet.c	2004-11-02 06:40:42 -08:00
+++ b/arch/i386/kernel/time_hpet.c	2005-02-04 17:23:42 -08:00
@@ -81,6 +81,11 @@
 	cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 	       HPET_TN_SETVAL | HPET_TN_32BIT;
 	hpet_writel(cfg, HPET_T0_CFG);
+	/*
+	 * Some systems seems to need two writes to HPET_T0_CMP,
+	 * to get interrupts working
+	 */
+	hpet_writel(tick, HPET_T0_CMP);
 	hpet_writel(tick, HPET_T0_CMP);
 
 	/*
diff -Nru a/arch/i386/lib/usercopy.c b/arch/i386/lib/usercopy.c
--- a/arch/i386/lib/usercopy.c	2004-08-26 23:31:38 -07:00
+++ b/arch/i386/lib/usercopy.c	2005-02-04 20:12:12 -08:00
@@ -514,6 +514,7 @@
 
 unsigned long __copy_to_user_ll(void __user *to, const void *from, unsigned long n)
 {
+	BUG_ON((long) n < 0);
 #ifndef CONFIG_X86_WP_WORKS_OK
 	if (unlikely(boot_cpu_data.wp_works_ok == 0) &&
 			((unsigned long )to) < TASK_SIZE) {
@@ -573,6 +574,7 @@
 unsigned long
 __copy_from_user_ll(void *to, const void __user *from, unsigned long n)
 {
+	BUG_ON((long)n < 0);
 	if (movsl_is_ok(to, from, n))
 		__copy_user_zeroing(to, from, n);
 	else
@@ -597,6 +599,7 @@
 copy_to_user(void __user *to, const void *from, unsigned long n)
 {
 	might_sleep();
+	BUG_ON((long) n < 0);
 	if (access_ok(VERIFY_WRITE, to, n))
 		n = __copy_to_user(to, from, n);
 	return n;
@@ -623,6 +626,7 @@
 copy_from_user(void *to, const void __user *from, unsigned long n)
 {
 	might_sleep();
+	BUG_ON((long) n < 0);
 	if (access_ok(VERIFY_READ, from, n))
 		n = __copy_from_user(to, from, n);
 	else
diff -Nru a/arch/ia64/Kconfig b/arch/ia64/Kconfig
--- a/arch/ia64/Kconfig	2005-01-18 12:06:17 -08:00
+++ b/arch/ia64/Kconfig	2005-01-28 15:32:25 -08:00
@@ -158,14 +158,6 @@
 	depends on ITANIUM
 	default y
 
-config ITANIUM_BSTEP_SPECIFIC
-	bool "Itanium B-step specific code"
-	depends on ITANIUM
-	help
-	  Select this option to build a kernel for an Itanium prototype system
-	  with a B-step CPU.  You have a B-step CPU if the "revision" field in
-	  /proc/cpuinfo has a value in the range from 1 to 4.
-
 # align cache-sensitive data to 128 bytes
 config IA64_L1_CACHE_SHIFT
 	int
diff -Nru a/arch/ia64/Makefile b/arch/ia64/Makefile
--- a/arch/ia64/Makefile	2005-01-07 16:15:52 -08:00
+++ b/arch/ia64/Makefile	2005-01-28 15:32:45 -08:00
@@ -46,8 +46,6 @@
 	cflags-$(CONFIG_MCKINLEY)	+= -mtune=mckinley
 endif
 
-cflags-$(CONFIG_ITANIUM_BSTEP_SPECIFIC)	+= -mb-step
-
 CFLAGS += $(cflags-y)
 head-y := arch/ia64/kernel/head.o arch/ia64/kernel/init_task.o
 
diff -Nru a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
--- a/arch/ia64/configs/bigsur_defconfig	2004-11-30 08:48:16 -08:00
+++ b/arch/ia64/configs/bigsur_defconfig	2005-01-28 15:32:47 -08:00
@@ -73,7 +73,6 @@
 CONFIG_IA64_PAGE_SIZE_16KB=y
 # CONFIG_IA64_PAGE_SIZE_64KB is not set
 CONFIG_IA64_BRL_EMU=y
-# CONFIG_ITANIUM_BSTEP_SPECIFIC is not set
 CONFIG_IA64_L1_CACHE_SHIFT=6
 # CONFIG_NUMA is not set
 # CONFIG_VIRTUAL_MEM_MAP is not set
diff -Nru a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c
--- a/arch/ia64/ia32/ia32_signal.c	2005-01-04 18:48:19 -08:00
+++ b/arch/ia64/ia32/ia32_signal.c	2005-01-25 12:23:45 -08:00
@@ -1,7 +1,7 @@
 /*
  * IA32 Architecture-specific signal handling support.
  *
- * Copyright (C) 1999, 2001-2002 Hewlett-Packard Co
+ * Copyright (C) 1999, 2001-2002, 2005 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 2000 VA Linux Co
@@ -970,11 +970,10 @@
 }
 
 asmlinkage long
-sys32_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6, int arg7,
-		 unsigned long stack)
+sys32_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5,
+		 int arg6, int arg7, struct pt_regs regs)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
-	unsigned long esp = (unsigned int) regs->r12;
+	unsigned long esp = (unsigned int) regs.r12;
 	struct sigframe_ia32 __user *frame = (struct sigframe_ia32 __user *)(esp - 8);
 	sigset_t set;
 	int eax;
@@ -993,7 +992,7 @@
 	recalc_sigpending();
 	spin_unlock_irq(&current->sighand->siglock);
 
-	if (restore_sigcontext_ia32(regs, &frame->sc, &eax))
+	if (restore_sigcontext_ia32(&regs, &frame->sc, &eax))
 		goto badframe;
 	return eax;
 
@@ -1003,11 +1002,10 @@
 }
 
 asmlinkage long
-sys32_rt_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6, int arg7,
-		    unsigned long stack)
+sys32_rt_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4,
+		    int arg5, int arg6, int arg7, struct pt_regs regs)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
-	unsigned long esp = (unsigned int) regs->r12;
+	unsigned long esp = (unsigned int) regs.r12;
 	struct rt_sigframe_ia32 __user *frame = (struct rt_sigframe_ia32 __user *)(esp - 4);
 	sigset_t set;
 	int eax;
@@ -1023,7 +1021,7 @@
 	recalc_sigpending();
 	spin_unlock_irq(&current->sighand->siglock);
 
-	if (restore_sigcontext_ia32(regs, &frame->uc.uc_mcontext, &eax))
+	if (restore_sigcontext_ia32(&regs, &frame->uc.uc_mcontext, &eax))
 		goto badframe;
 
 	/* It is more difficult to avoid calling this function than to
diff -Nru a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c
--- a/arch/ia64/ia32/sys_ia32.c	2005-01-25 13:50:22 -08:00
+++ b/arch/ia64/ia32/sys_ia32.c	2005-01-31 14:15:33 -08:00
@@ -6,7 +6,7 @@
  * Copyright (C) 1999		Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 1997,1998	Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  * Copyright (C) 1997		David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2000-2003 Hewlett-Packard Co
+ * Copyright (C) 2000-2003, 2005 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 2004		Gordon Jin <gordon.jin@intel.com>
  *
@@ -1436,7 +1436,7 @@
 }
 
 static unsigned int
-ia32_peek (struct pt_regs *regs, struct task_struct *child, unsigned long addr, unsigned int *val)
+ia32_peek (struct task_struct *child, unsigned long addr, unsigned int *val)
 {
 	size_t copied;
 	unsigned int ret;
@@ -1446,7 +1446,7 @@
 }
 
 static unsigned int
-ia32_poke (struct pt_regs *regs, struct task_struct *child, unsigned long addr, unsigned int val)
+ia32_poke (struct task_struct *child, unsigned long addr, unsigned int val)
 {
 
 	if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val))
@@ -1751,25 +1751,16 @@
 	return 0;
 }
 
-/*
- *  Note that the IA32 version of `ptrace' calls the IA64 routine for
- *    many of the requests.  This will only work for requests that do
- *    not need access to the calling processes `pt_regs' which is located
- *    at the address of `stack'.  Once we call the IA64 `sys_ptrace' then
- *    the address of `stack' will not be the address of the `pt_regs'.
- */
 asmlinkage long
-sys32_ptrace (int request, pid_t pid, unsigned int addr, unsigned int data,
-	      long arg4, long arg5, long arg6, long arg7, long stack)
+sys32_ptrace (int request, pid_t pid, unsigned int addr, unsigned int data)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
 	struct task_struct *child;
 	unsigned int value, tmp;
 	long i, ret;
 
 	lock_kernel();
 	if (request == PTRACE_TRACEME) {
-		ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack);
+		ret = sys_ptrace(request, pid, addr, data);
 		goto out;
 	}
 
@@ -1786,7 +1777,7 @@
 		goto out_tsk;
 
 	if (request == PTRACE_ATTACH) {
-		ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack);
+		ret = sys_ptrace(request, pid, addr, data);
 		goto out_tsk;
 	}
 
@@ -1797,7 +1788,7 @@
 	switch (request) {
 	      case PTRACE_PEEKTEXT:
 	      case PTRACE_PEEKDATA:	/* read word at location addr */
-		ret = ia32_peek(regs, child, addr, &value);
+		ret = ia32_peek(child, addr, &value);
 		if (ret == 0)
 			ret = put_user(value, (unsigned int __user *) compat_ptr(data));
 		else
@@ -1806,7 +1797,7 @@
 
 	      case PTRACE_POKETEXT:
 	      case PTRACE_POKEDATA:	/* write the word at location addr */
-		ret = ia32_poke(regs, child, addr, data);
+		ret = ia32_poke(child, addr, data);
 		goto out_tsk;
 
 	      case PTRACE_PEEKUSR:	/* read word at addr in USER area */
@@ -1882,7 +1873,7 @@
 	      case PTRACE_KILL:
 	      case PTRACE_SINGLESTEP:	/* execute chile for one instruction */
 	      case PTRACE_DETACH:	/* detach a process */
-		ret = sys_ptrace(request, pid, addr, data, arg4, arg5, arg6, arg7, stack);
+		ret = sys_ptrace(request, pid, addr, data);
 		break;
 
 	      default:
@@ -1905,9 +1896,9 @@
 
 asmlinkage long
 sys32_sigaltstack (ia32_stack_t __user *uss32, ia32_stack_t __user *uoss32,
-		   long arg2, long arg3, long arg4, long arg5, long arg6, long arg7, long stack)
+		   long arg2, long arg3, long arg4, long arg5, long arg6,
+		   long arg7, struct pt_regs pt)
 {
-	struct pt_regs *pt = (struct pt_regs *) &stack;
 	stack_t uss, uoss;
 	ia32_stack_t buf32;
 	int ret;
@@ -1928,7 +1919,7 @@
 	}
 	set_fs(KERNEL_DS);
 	ret = do_sigaltstack(uss32 ? (stack_t __user *) &uss : NULL,
-			     (stack_t __user *) &uoss, pt->r12);
+			     (stack_t __user *) &uoss, pt.r12);
  	current->sas_ss_size = buf32.ss_size;
 	set_fs(old_fs);
 out:
diff -Nru a/arch/ia64/kernel/asm-offsets.c b/arch/ia64/kernel/asm-offsets.c
--- a/arch/ia64/kernel/asm-offsets.c	2005-01-06 16:19:39 -08:00
+++ b/arch/ia64/kernel/asm-offsets.c	2005-01-26 09:59:15 -08:00
@@ -193,9 +193,17 @@
 	DEFINE(IA64_CLONE_VM, CLONE_VM);
 
 	BLANK();
-	DEFINE(IA64_CPUINFO_NSEC_PER_CYC_OFFSET, offsetof (struct cpuinfo_ia64, nsec_per_cyc));
-	DEFINE(IA64_TIMESPEC_TV_NSEC_OFFSET, offsetof (struct timespec, tv_nsec));
-
+	DEFINE(IA64_CPUINFO_NSEC_PER_CYC_OFFSET,
+	       offsetof (struct cpuinfo_ia64, nsec_per_cyc));
+	DEFINE(IA64_CPUINFO_PTCE_BASE_OFFSET,
+	       offsetof (struct cpuinfo_ia64, ptce_base));
+	DEFINE(IA64_CPUINFO_PTCE_COUNT_OFFSET,
+	       offsetof (struct cpuinfo_ia64, ptce_count));
+	DEFINE(IA64_CPUINFO_PTCE_STRIDE_OFFSET,
+	       offsetof (struct cpuinfo_ia64, ptce_stride));
+	BLANK();
+	DEFINE(IA64_TIMESPEC_TV_NSEC_OFFSET,
+	       offsetof (struct timespec, tv_nsec));
 
 	DEFINE(CLONE_SETTLS_BIT, 19);
 #if CLONE_SETTLS != (1<<19)
@@ -203,19 +211,16 @@
 #endif
 
 	BLANK();
-	/* used by arch/ia64/kernel/mca_asm.S */
-	DEFINE(IA64_CPUINFO_PERCPU_PADDR, offsetof (struct cpuinfo_ia64, percpu_paddr));
-	DEFINE(IA64_CPUINFO_PAL_PADDR, offsetof (struct cpuinfo_ia64, pal_paddr));
-	DEFINE(IA64_CPUINFO_PA_MCA_INFO, offsetof (struct cpuinfo_ia64, ia64_pa_mca_data));
-	DEFINE(IA64_MCA_PROC_STATE_DUMP, offsetof (struct ia64_mca_cpu_s, ia64_mca_proc_state_dump));
-	DEFINE(IA64_MCA_STACK, offsetof (struct ia64_mca_cpu_s, ia64_mca_stack));
-	DEFINE(IA64_MCA_STACKFRAME, offsetof (struct ia64_mca_cpu_s, ia64_mca_stackframe));
-	DEFINE(IA64_MCA_BSPSTORE, offsetof (struct ia64_mca_cpu_s, ia64_mca_bspstore));
-	DEFINE(IA64_INIT_STACK, offsetof (struct ia64_mca_cpu_s, ia64_init_stack));
-
-	/* used by head.S */
-	DEFINE(IA64_CPUINFO_NSEC_PER_CYC_OFFSET, offsetof (struct cpuinfo_ia64, nsec_per_cyc));
-
+	DEFINE(IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET,
+	       offsetof (struct ia64_mca_cpu, proc_state_dump));
+	DEFINE(IA64_MCA_CPU_STACK_OFFSET,
+	       offsetof (struct ia64_mca_cpu, stack));
+	DEFINE(IA64_MCA_CPU_STACKFRAME_OFFSET,
+	       offsetof (struct ia64_mca_cpu, stackframe));
+	DEFINE(IA64_MCA_CPU_RBSTORE_OFFSET,
+	       offsetof (struct ia64_mca_cpu, rbstore));
+	DEFINE(IA64_MCA_CPU_INIT_STACK_OFFSET,
+	       offsetof (struct ia64_mca_cpu, init_stack));
 	BLANK();
 	/* used by fsys_gettimeofday in arch/ia64/kernel/fsys.S */
 	DEFINE(IA64_TIME_INTERPOLATOR_ADDRESS_OFFSET, offsetof (struct time_interpolator, addr));
diff -Nru a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c
--- a/arch/ia64/kernel/efi.c	2005-01-22 15:59:24 -08:00
+++ b/arch/ia64/kernel/efi.c	2005-01-26 10:01:27 -08:00
@@ -415,8 +415,8 @@
  * Abstraction Layer chapter 11 in ADAG
  */
 
-static efi_memory_desc_t *
-pal_code_memdesc (void)
+void *
+efi_get_pal_addr (void)
 {
 	void *efi_map_start, *efi_map_end, *p;
 	efi_memory_desc_t *md;
@@ -474,51 +474,31 @@
 			md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
 			vaddr & mask, (vaddr & mask) + IA64_GRANULE_SIZE);
 #endif
-		return md;
+		return __va(md->phys_addr);
 	}
-
+	printk(KERN_WARNING "%s: no PAL-code memory-descriptor found",
+	       __FUNCTION__);
 	return NULL;
 }
 
 void
-efi_get_pal_addr (void)
-{
-	efi_memory_desc_t *md = pal_code_memdesc();
-	u64 vaddr, mask;
-	struct cpuinfo_ia64 *cpuinfo;
-
-	if (md != NULL) {
-
-		vaddr = PAGE_OFFSET + md->phys_addr;
-		mask  = ~((1 << IA64_GRANULE_SHIFT) - 1);
-
-		cpuinfo = (struct cpuinfo_ia64 *)__va(ia64_get_kr(IA64_KR_PA_CPU_INFO));
-		cpuinfo->pal_base = vaddr & mask;
-		cpuinfo->pal_paddr = pte_val(mk_pte_phys(md->phys_addr, PAGE_KERNEL));
-	}
-}
-
-void
 efi_map_pal_code (void)
 {
-	efi_memory_desc_t *md = pal_code_memdesc();
-	u64 vaddr, mask, psr;
-
-	if (md != NULL) {
+	void *pal_vaddr = efi_get_pal_addr ();
+	u64 psr;
 
-		vaddr = PAGE_OFFSET + md->phys_addr;
-		mask  = ~((1 << IA64_GRANULE_SHIFT) - 1);
+	if (!pal_vaddr)
+		return;
 
-		/*
-		 * Cannot write to CRx with PSR.ic=1
-		 */
-		psr = ia64_clear_ic();
-		ia64_itr(0x1, IA64_TR_PALCODE, vaddr & mask,
-			pte_val(pfn_pte(md->phys_addr >> PAGE_SHIFT, PAGE_KERNEL)),
-			IA64_GRANULE_SHIFT);
-		ia64_set_psr(psr);		/* restore psr */
-		ia64_srlz_i();
-	}
+	/*
+	 * Cannot write to CRx with PSR.ic=1
+	 */
+	psr = ia64_clear_ic();
+	ia64_itr(0x1, IA64_TR_PALCODE, GRANULEROUNDDOWN((unsigned long) pal_vaddr),
+		 pte_val(pfn_pte(__pa(pal_vaddr) >> PAGE_SHIFT, PAGE_KERNEL)),
+		 IA64_GRANULE_SHIFT);
+	ia64_set_psr(psr);		/* restore psr */
+	ia64_srlz_i();
 }
 
 void __init
diff -Nru a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
--- a/arch/ia64/kernel/entry.S	2005-01-22 14:32:20 -08:00
+++ b/arch/ia64/kernel/entry.S	2005-01-28 15:15:49 -08:00
@@ -558,7 +558,7 @@
 .mem.offset 0,0; st8.spill [r2]=r8		// store return value in slot for r8
 .mem.offset 8,0; st8.spill [r3]=r10		// clear error indication in slot for r10
 	br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
-.ret3:	br.cond.sptk ia64_leave_syscall
+.ret3:	br.cond.sptk .work_pending_syscall_end
 
 strace_error:
 	ld8 r3=[r2]				// load pt_regs.r8
@@ -621,10 +621,7 @@
 	PT_REGS_UNWIND_INFO(0)
 	cmp.ge p6,p7=r8,r0			// syscall executed successfully?
 	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
-	adds r3=PT(R10)+16,sp			// r3 = &pt_regs.r10
-	;;
-.mem.offset 0,0; (p6) st8.spill [r2]=r8	// store return value in slot for r8 and set unat bit
-.mem.offset 8,0; (p6) st8.spill [r3]=r0	// clear error indication in slot for r10 and set unat bit
+	mov r10=r0				// clear error indication in r10
 (p7)	br.cond.spnt handle_syscall_error	// handle potential syscall failure
 END(ia64_ret_from_syscall)
 	// fall through
@@ -709,27 +706,23 @@
 	ld8 r19=[r2],PT(B6)-PT(LOADRS)		// load ar.rsc value for "loadrs"
 	mov b7=r0		// clear b7
 	;;
-	ld8 r23=[r3],PT(R9)-PT(AR_BSPSTORE)	// load ar.bspstore (may be garbage)
-	ld8 r18=[r2],PT(R8)-PT(B6)		// load b6
+	ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE)	// load ar.bspstore (may be garbage)
+	ld8 r18=[r2],PT(R9)-PT(B6)		// load b6
 (p6)	and r15=TIF_WORK_MASK,r31		// any work other than TIF_SYSCALL_TRACE?
 	;;
 	mov r16=ar.bsp				// M2  get existing backing store pointer
 (p6)	cmp4.ne.unc p6,p0=r15, r0		// any special work pending?
-(p6)	br.cond.spnt .work_pending
+(p6)	br.cond.spnt .work_pending_syscall
 	;;
 	// start restoring the state saved on the kernel stack (struct pt_regs):
-	ld8.fill r8=[r2],16
-	ld8.fill r9=[r3],16
+	ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
+	ld8 r11=[r3],PT(CR_IIP)-PT(R11)
 	mov f6=f0		// clear f6
 	;;
 	invala			// M0|1 invalidate ALAT
 	rsm psr.i | psr.ic	// M2 initiate turning off of interrupt and interruption collection
 	mov f9=f0		// clear f9
 
-	ld8.fill r10=[r2],16
-	ld8.fill r11=[r3],16
-	mov f7=f0		// clear f7
-	;;
 	ld8 r29=[r2],16		// load cr.ipsr
 	ld8 r28=[r3],16			// load cr.iip
 	mov f8=f0		// clear f8
@@ -760,7 +753,7 @@
 	;;
 	srlz.d			// M0  ensure interruption collection is off
 	ld8.fill r13=[r3],16
-	nop.i 0
+	mov f7=f0		// clear f7
 	;;
 	ld8.fill r12=[r2]	// restore r12 (sp)
 	ld8.fill r15=[r3]	// restore r15
@@ -770,8 +763,8 @@
 (pUStk) st1 [r14]=r17
 	mov b6=r18		// I0  restore b6
 	;;
-	shr.u r18=r19,16	// I0|1 get byte size of existing "dirty" partition
 	mov r14=r0		// clear r14
+	shr.u r18=r19,16	// I0|1 get byte size of existing "dirty" partition
 (pKStk) br.cond.dpnt.many skip_rbs_switch
 
 	mov.m ar.ccv=r0		// clear ar.ccv
@@ -987,7 +980,7 @@
 	shladd in0=loc1,3,r17
 	mov in1=0
 	;;
-	.align 32
+	TEXT_ALIGN(32)
 rse_clear_invalid:
 #ifdef CONFIG_ITANIUM
 	// cycle 0
@@ -1083,6 +1076,12 @@
 	 * On exit:
 	 *	p6 = TRUE if work-pending-check needs to be redone
 	 */
+.work_pending_syscall:
+	add r2=-8,r2
+	add r3=-8,r3
+	;;
+	st8 [r2]=r8
+	st8 [r3]=r10
 .work_pending:
 	tbit.nz p6,p0=r31,TIF_SIGDELAYED		// signal delayed from  MCA/INIT/NMI/PMI context?
 (p6)	br.cond.sptk.few .sigdelayed
@@ -1104,13 +1103,13 @@
 	;;
 (pKStk)	st4 [r20]=r0		// preempt_count() <- 0
 #endif
-(pLvSys)br.cond.sptk.many .work_processed_syscall	// re-check
+(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
 	br.cond.sptk.many .work_processed_kernel	// re-check
 
 .notify:
 (pUStk)	br.call.spnt.many rp=notify_resume_user
 .ret10:	cmp.ne p6,p0=r0,r0				// p6 <- 0
-(pLvSys)br.cond.sptk.many .work_processed_syscall	// don't re-check
+(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
 	br.cond.sptk.many .work_processed_kernel	// don't re-check
 
 // There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where
@@ -1121,9 +1120,17 @@
 .sigdelayed:
 	br.call.sptk.many rp=do_sigdelayed
 	cmp.eq p6,p0=r0,r0				// p6 <- 1, always re-check
-(pLvSys)br.cond.sptk.many .work_processed_syscall	// re-check
+(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
 	br.cond.sptk.many .work_processed_kernel	// re-check
 
+.work_pending_syscall_end:
+	adds r2=PT(R8)+16,r12
+	adds r3=PT(R10)+16,r12
+	;;
+	ld8 r8=[r2]
+	ld8 r10=[r3]
+	br.cond.sptk.many .work_processed_syscall	// re-check
+
 END(ia64_leave_kernel)
 
 ENTRY(handle_syscall_error)
@@ -1135,17 +1142,11 @@
 	 */
 	PT_REGS_UNWIND_INFO(0)
 	ld8 r3=[r2]		// load pt_regs.r8
-	sub r9=0,r8		// negate return value to get errno
 	;;
-	mov r10=-1		// return -1 in pt_regs.r10 to indicate error
 	cmp.eq p6,p7=r3,r0	// is pt_regs.r8==0?
-	adds r3=16,r2		// r3=&pt_regs.r10
-	;;
-(p6)	mov r9=r8
-(p6)	mov r10=0
 	;;
-.mem.offset 0,0; st8.spill [r2]=r9	// store errno in pt_regs.r8 and set unat bit
-.mem.offset 8,0; st8.spill [r3]=r10	// store error indication in pt_regs.r10 and set unat bit
+(p7)	mov r10=-1
+(p7)	sub r8=0,r8		// negate return value to get errno
 	br.cond.sptk ia64_leave_syscall
 END(handle_syscall_error)
 
diff -Nru a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
--- a/arch/ia64/kernel/head.S	2005-01-11 15:45:50 -08:00
+++ b/arch/ia64/kernel/head.S	2005-01-28 15:50:13 -08:00
@@ -5,7 +5,7 @@
  * to set up the kernel's global pointer and jump to the kernel
  * entry point.
  *
- * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
+ * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *	Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 1999 VA Linux Systems
@@ -232,21 +232,6 @@
 	;;
 (isBP)	st8 [r2]=r28		// save the address of the boot param area passed by the bootloader
 
-#ifdef CONFIG_IA64_EARLY_PRINTK
-	.rodata
-alive_msg:
-	stringz "I'm alive and well\n"
-alive_msg_end:
-	.previous
-
-	alloc r2=ar.pfs,0,0,2,0
-	movl out0=alive_msg
-	movl out1=alive_msg_end-alive_msg-1
-	;;
-	br.call.sptk.many rp=early_printk
-1:	// force new bundle
-#endif /* CONFIG_IA64_EARLY_PRINTK */
-
 #ifdef CONFIG_SMP
 (isAP)	br.call.sptk.many rp=start_secondary
 .ret0:
@@ -267,7 +252,9 @@
 	;;
 	ld8 out0=[r3]
 	br.call.sptk.many b0=console_print
-self:	br.sptk.many self		// endless loop
+
+self:	hint @pause
+	br.sptk.many self		// endless loop
 END(_start)
 
 GLOBAL_ENTRY(ia64_save_debug_regs)
diff -Nru a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
--- a/arch/ia64/kernel/ivt.S	2005-01-22 14:19:19 -08:00
+++ b/arch/ia64/kernel/ivt.S	2005-02-02 15:06:25 -08:00
@@ -548,7 +548,7 @@
 #endif
 	mov pr=r31,-1				// restore pr
 	rfi
-END(idirty_bit)
+END(dirty_bit)
 
 	.org ia64_ivt+0x2400
 /////////////////////////////////////////////////////////////////////////////////////////
diff -Nru a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
--- a/arch/ia64/kernel/mca.c	2005-01-22 13:48:51 -08:00
+++ b/arch/ia64/kernel/mca.c	2005-02-02 12:21:18 -08:00
@@ -67,6 +67,7 @@
 
 #include <asm/delay.h>
 #include <asm/machvec.h>
+#include <asm/meminit.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
@@ -86,6 +87,12 @@
 ia64_mca_sal_to_os_state_t	ia64_sal_to_os_handoff_state;
 ia64_mca_os_to_sal_state_t	ia64_os_to_sal_handoff_state;
 u64				ia64_mca_serialize;
+DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
+DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
+DEFINE_PER_CPU(u64, ia64_mca_pal_pte);	    /* PTE to map PAL code */
+DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
+
+unsigned long __per_cpu_mca[NR_CPUS];
 
 /* In mca_asm.S */
 extern void			ia64_monarch_init_handler (void);
@@ -1194,6 +1201,53 @@
 	.name =		"cpe_poll"
 };
 #endif /* CONFIG_ACPI */
+
+/* Do per-CPU MCA-related initialization.  */
+
+void __devinit
+ia64_mca_cpu_init(void *cpu_data)
+{
+	void *pal_vaddr;
+
+	if (smp_processor_id() == 0) {
+		void *mca_data;
+		int cpu;
+
+		mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
+					 * NR_CPUS);
+		for (cpu = 0; cpu < NR_CPUS; cpu++) {
+			__per_cpu_mca[cpu] = __pa(mca_data);
+			mca_data += sizeof(struct ia64_mca_cpu);
+		}
+	}
+
+        /*
+         * The MCA info structure was allocated earlier and its
+         * physical address saved in __per_cpu_mca[cpu].  Copy that
+         * address * to ia64_mca_data so we can access it as a per-CPU
+         * variable.
+         */
+	__get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
+
+	/*
+	 * Stash away a copy of the PTE needed to map the per-CPU page.
+	 * We may need it during MCA recovery.
+	 */
+	__get_cpu_var(ia64_mca_per_cpu_pte) =
+		pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
+
+        /*
+         * Also, stash away a copy of the PAL address and the PTE
+         * needed to map it.
+         */
+        pal_vaddr = efi_get_pal_addr();
+	if (!pal_vaddr)
+		return;
+	__get_cpu_var(ia64_mca_pal_base) =
+		GRANULEROUNDDOWN((unsigned long) pal_vaddr);
+	__get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
+							      PAGE_KERNEL));
+}
 
 /*
  * ia64_mca_init
diff -Nru a/arch/ia64/kernel/mca_asm.S b/arch/ia64/kernel/mca_asm.S
--- a/arch/ia64/kernel/mca_asm.S	2005-01-06 16:20:34 -08:00
+++ b/arch/ia64/kernel/mca_asm.S	2005-02-08 09:57:59 -08:00
@@ -101,6 +101,11 @@
 	ld8	tmp=[sal_to_os_handoff];;				\
 	st8     [os_to_sal_handoff]=tmp;;
 
+#define GET_IA64_MCA_DATA(reg)						\
+	GET_THIS_PADDR(reg, ia64_mca_data)				\
+	;;								\
+	ld8 reg=[reg]
+
 	.global ia64_os_mca_dispatch
 	.global ia64_os_mca_dispatch_end
 	.global ia64_sal_to_os_handoff_state
@@ -144,24 +149,26 @@
 	// The following code purges TC and TR entries. Then reload all TC entries.
 	// Purge percpu data TC entries.
 begin_tlb_purge_and_reload:
-	GET_PERCPU_PADDR(r2)	// paddr of percpu_paddr in cpuinfo struct
-	;;
-	mov	r17=r2
-	;;
-	adds r17=8,r17
+
+#define O(member)	IA64_CPUINFO_##member##_OFFSET
+
+	GET_THIS_PADDR(r2, cpu_info)	// load phys addr of cpu_info into r2
 	;;
-	ld8 r18=[r17],8		// r18=ptce_base
-  	;;
-	ld4 r19=[r17],4		// r19=ptce_count[0]
+	addl r17=O(PTCE_STRIDE),r2
+	addl r2=O(PTCE_BASE),r2
 	;;
-	ld4 r20=[r17],4		// r20=ptce_count[1]
+	ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));;	// r18=ptce_base
+	ld4 r19=[r2],4					// r19=ptce_count[0]
+	ld4 r21=[r17],4					// r21=ptce_stride[0]
 	;;
-	ld4 r21=[r17],4		// r21=ptce_stride[0]
+	ld4 r20=[r2]					// r20=ptce_count[1]
+	ld4 r22=[r17]					// r22=ptce_stride[1]
 	mov r24=0
 	;;
-	ld4 r22=[r17],4		// r22=ptce_stride[1]
 	adds r20=-1,r20
 	;;
+#undef O
+
 2:
 	cmp.ltu p6,p7=r24,r19
 (p7)	br.cond.dpnt.few 4f
@@ -201,9 +208,9 @@
 	srlz.d
 	;;
 	// 3. Purge ITR for PAL code.
-	adds r17=40,r23
+	GET_THIS_PADDR(r2, ia64_mca_pal_base)
 	;;
-	ld8 r16=[r17]
+	ld8 r16=[r2]
 	mov r18=IA64_GRANULE_SHIFT<<2
 	;;
 	ptr.i r16,r18
@@ -246,16 +253,15 @@
 	srlz.d
 	;;
 	// 2. Reload DTR register for PERCPU data.
-	GET_PERCPU_PADDR(r2)		// paddr of percpu_paddr in cpuinfo struct
+	GET_THIS_PADDR(r2, ia64_mca_per_cpu_pte)
 	;;
-	mov r17=r2
 	movl r16=PERCPU_ADDR		// vaddr
 	movl r18=PERCPU_PAGE_SHIFT<<2
 	;;
 	mov cr.itir=r18
 	mov cr.ifa=r16
 	;;
-	ld8 r18=[r17]			// pte
+	ld8 r18=[r2]			// load per-CPU PTE
 	mov r16=IA64_TR_PERCPU_DATA;
 	;;
 	itr.d dtr[r16]=r18
@@ -263,13 +269,13 @@
 	srlz.d
 	;;
 	// 3. Reload ITR for PAL code.
-	GET_CPUINFO_PAL_PADDR(r2)	// paddr of pal_paddr in cpuinfo struct
+	GET_THIS_PADDR(r2, ia64_mca_pal_pte)
 	;;
-	mov r17=r2
+	ld8 r18=[r2]			// load PAL PTE
 	;;
-	ld8 r18=[r17],8			// pte
+	GET_THIS_PADDR(r2, ia64_mca_pal_base)
 	;;
-	ld8 r16=[r17]			// vaddr
+	ld8 r16=[r2]			// load PAL vaddr
 	mov r19=IA64_GRANULE_SHIFT<<2
 	;;
 	mov cr.itir=r19
@@ -308,14 +314,18 @@
 done_tlb_purge_and_reload:
 
 	// Setup new stack frame for OS_MCA handling
-	GET_MCA_BSPSTORE(r2)		// paddr of bspstore save area
-	GET_MCA_STACKFRAME(r3);;	// paddr of stack frame save area
+	GET_IA64_MCA_DATA(r2)
+	;;
+	add r3 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
+	add r2 = IA64_MCA_CPU_RBSTORE_OFFSET, r2
+	;;
 	rse_switch_context(r6,r3,r2);;	// RSC management in this new context
-	GET_MCA_STACK(r2);;		// paddr of stack save area
-					// stack size must be same as C array
-	addl	r2=8*1024-16,r2;;	// stack base @ bottom of array
-	mov	r12=r2			// allow 16 bytes of scratch
-					// (C calling convention)
+
+	GET_IA64_MCA_DATA(r2)
+	;;
+	add r2 = IA64_MCA_CPU_STACK_OFFSET+IA64_MCA_STACK_SIZE-16, r2
+	;;
+	mov r12=r2		// establish new stack-pointer
 
         // Enter virtual mode from physical mode
 	VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
@@ -331,7 +341,10 @@
 ia64_os_mca_virtual_end:
 
 	// restore the original stack frame here
-	GET_MCA_STACKFRAME(r2);;	// phys addr of MCA save area
+	GET_IA64_MCA_DATA(r2)
+	;;
+	add r2 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
+	;;
 	movl    r4=IA64_PSR_MC
 	;;
 	rse_return_context(r4,r3,r2)	// switch from interrupt context for RSE
@@ -372,8 +385,10 @@
 ia64_os_mca_proc_state_dump:
 // Save bank 1 GRs 16-31 which will be used by c-language code when we switch
 //  to virtual addressing mode.
-	GET_MCA_DUMP_PADDR(r2);;  // phys addr of MCA save area
-
+	GET_IA64_MCA_DATA(r2)
+	;;
+	add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
+	;;
 // save ar.NaT
 	mov		r5=ar.unat                  // ar.unat
 
@@ -603,7 +618,9 @@
 ia64_os_mca_proc_state_restore:
 
 // Restore bank1 GR16-31
-	GET_MCA_DUMP_PADDR(r2);;		// phys addr of proc state dump area
+	GET_IA64_MCA_DATA(r2)
+	;;
+	add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
 
 restore_GRs:                                    // restore bank-1 GRs 16-31
 	bsw.1;;
diff -Nru a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h
--- a/arch/ia64/kernel/minstate.h	2004-12-10 13:31:49 -08:00
+++ b/arch/ia64/kernel/minstate.h	2005-01-26 10:01:31 -08:00
@@ -37,10 +37,10 @@
  * go virtual and don't want to destroy the iip or ipsr.
  */
 #define MINSTATE_START_SAVE_MIN_PHYS								\
-(pKStk) mov r3=ar.k3;;										\
-(pKStk) addl r3=IA64_CPUINFO_PA_MCA_INFO,r3;;							\
+(pKStk) mov r3=IA64_KR(PER_CPU_DATA);;								\
+(pKStk) addl r3=THIS_CPU(ia64_mca_data),r3;;							\
 (pKStk) ld8 r3 = [r3];;										\
-(pKStk) addl r3=IA64_INIT_STACK,r3;;								\
+(pKStk) addl r3=IA64_MCA_CPU_INIT_STACK_OFFSET,r3;;						\
 (pKStk) addl sp=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3;						\
 (pUStk)	mov ar.rsc=0;		/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */	\
 (pUStk)	addl r22=IA64_RBS_OFFSET,r1;		/* compute base of register backing store */	\
diff -Nru a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
--- a/arch/ia64/kernel/perfmon.c	2004-12-28 13:20:10 -08:00
+++ b/arch/ia64/kernel/perfmon.c	2005-01-25 12:23:45 -08:00
@@ -5,13 +5,13 @@
  * The initial version of perfmon.c was written by
  * Ganesh Venkitachalam, IBM Corp.
  *
- * Then it was modified for perfmon-1.x by Stephane Eranian and 
+ * Then it was modified for perfmon-1.x by Stephane Eranian and
  * David Mosberger, Hewlett Packard Co.
- * 
+ *
  * Version Perfmon-2.x is a rewrite of perfmon-1.x
- * by Stephane Eranian, Hewlett Packard Co. 
+ * by Stephane Eranian, Hewlett Packard Co.
  *
- * Copyright (C) 1999-2003  Hewlett Packard Co
+ * Copyright (C) 1999-2003, 2005  Hewlett Packard Co
  *               Stephane Eranian <eranian@hpl.hp.com>
  *               David Mosberger-Tang <davidm@hpl.hp.com>
  *
@@ -4778,10 +4778,8 @@
  * system-call entry point (must return long)
  */
 asmlinkage long
-sys_perfmonctl (int fd, int cmd, void __user *arg, int count, long arg5, long arg6, long arg7,
-		long arg8, long stack)
+sys_perfmonctl (int fd, int cmd, void __user *arg, int count)
 {
-	struct pt_regs *regs = (struct pt_regs *)&stack;
 	struct file *file = NULL;
 	pfm_context_t *ctx = NULL;
 	unsigned long flags = 0UL;
@@ -4905,7 +4903,7 @@
 	if (unlikely(ret)) goto abort_locked;
 
 skip_fd:
-	ret = (*func)(ctx, args_k, count, regs);
+	ret = (*func)(ctx, args_k, count, ia64_task_regs(current));
 
 	call_made = 1;
 
@@ -6671,8 +6669,7 @@
 }
 #else  /* !CONFIG_PERFMON */
 asmlinkage long
-sys_perfmonctl (int fd, int cmd, void *arg, int count, long arg5, long arg6, long arg7,
-		long arg8, long stack)
+sys_perfmonctl (int fd, int cmd, void *arg, int count)
 {
 	return -ENOSYS;
 }
diff -Nru a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
--- a/arch/ia64/kernel/ptrace.c	2005-01-22 13:20:22 -08:00
+++ b/arch/ia64/kernel/ptrace.c	2005-01-28 15:43:34 -08:00
@@ -1,11 +1,10 @@
 /*
  * Kernel support for the ptrace() and syscall tracing interfaces.
  *
- * Copyright (C) 1999-2004 Hewlett-Packard Co
+ * Copyright (C) 1999-2005 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
- * Derived from the x86 and Alpha versions.  Most of the code in here
- * could actually be factored into a common set of routines.
+ * Derived from the x86 and Alpha versions.
  */
 #include <linux/config.h>
 #include <linux/kernel.h>
@@ -40,9 +39,11 @@
  *	ri (restart instruction; two bits)
  *	is (instruction set; one bit)
  */
-#define IPSR_WRITE_MASK \
-	(IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
-#define IPSR_READ_MASK	IPSR_WRITE_MASK
+#define IPSR_MASK (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS	\
+		   | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
+
+#define MASK(nbits)	((1UL << (nbits)) - 1)	/* mask with NBITS bits set */
+#define PFM_MASK	MASK(38)
 
 #define PTRACE_DEBUG	0
 
@@ -68,23 +69,24 @@
 unsigned long
 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
 {
-#	define GET_BITS(first, last, unat)						\
-	({										\
-		unsigned long bit = ia64_unat_pos(&pt->r##first);			\
-		unsigned long mask = ((1UL << (last - first + 1)) - 1) << first;	\
-		unsigned long dist;							\
-		if (bit < first)							\
-			dist = 64 + bit - first;					\
-		else									\
-			dist = bit - first;						\
-		ia64_rotr(unat, dist) & mask;						\
+#	define GET_BITS(first, last, unat)				\
+	({								\
+		unsigned long bit = ia64_unat_pos(&pt->r##first);	\
+		unsigned long nbits = (last - first + 1);		\
+		unsigned long mask = MASK(nbits) << first;		\
+		unsigned long dist;					\
+		if (bit < first)					\
+			dist = 64 + bit - first;			\
+		else							\
+			dist = bit - first;				\
+		ia64_rotr(unat, dist) & mask;				\
 	})
 	unsigned long val;
 
 	/*
-	 * Registers that are stored consecutively in struct pt_regs can be handled in
-	 * parallel.  If the register order in struct_pt_regs changes, this code MUST be
-	 * updated.
+	 * Registers that are stored consecutively in struct pt_regs
+	 * can be handled in parallel.  If the register order in
+	 * struct_pt_regs changes, this code MUST be updated.
 	 */
 	val  = GET_BITS( 1,  1, scratch_unat);
 	val |= GET_BITS( 2,  3, scratch_unat);
@@ -106,23 +108,24 @@
 unsigned long
 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
 {
-#	define PUT_BITS(first, last, nat)						\
-	({										\
-		unsigned long bit = ia64_unat_pos(&pt->r##first);			\
-		unsigned long mask = ((1UL << (last - first + 1)) - 1) << first;	\
-		long dist;								\
-		if (bit < first)							\
-			dist = 64 + bit - first;					\
-		else									\
-			dist = bit - first;						\
-		ia64_rotl(nat & mask, dist);						\
+#	define PUT_BITS(first, last, nat)				\
+	({								\
+		unsigned long bit = ia64_unat_pos(&pt->r##first);	\
+		unsigned long nbits = (last - first + 1);		\
+		unsigned long mask = MASK(nbits) << first;		\
+		long dist;						\
+		if (bit < first)					\
+			dist = 64 + bit - first;			\
+		else							\
+			dist = bit - first;				\
+		ia64_rotl(nat & mask, dist);				\
 	})
 	unsigned long scratch_unat;
 
 	/*
-	 * Registers that are stored consecutively in struct pt_regs can be handled in
-	 * parallel.  If the register order in struct_pt_regs changes, this code MUST be
-	 * updated.
+	 * Registers that are stored consecutively in struct pt_regs
+	 * can be handled in parallel.  If the register order in
+	 * struct_pt_regs changes, this code MUST be updated.
 	 */
 	scratch_unat  = PUT_BITS( 1,  1, nat);
 	scratch_unat |= PUT_BITS( 2,  3, nat);
@@ -185,10 +188,12 @@
 }
 
 /*
- * This routine is used to read an rnat bits that are stored on the kernel backing store.
- * Since, in general, the alignment of the user and kernel are different, this is not
- * completely trivial.  In essence, we need to construct the user RNAT based on up to two
- * kernel RNAT values and/or the RNAT value saved in the child's pt_regs.
+ * This routine is used to read an rnat bits that are stored on the
+ * kernel backing store.  Since, in general, the alignment of the user
+ * and kernel are different, this is not completely trivial.  In
+ * essence, we need to construct the user RNAT based on up to two
+ * kernel RNAT values and/or the RNAT value saved in the child's
+ * pt_regs.
  *
  * user rbs
  *
@@ -221,24 +226,28 @@
  *					+--------+
  *						  <--- child_stack->ar_bspstore
  *
- * The way to think of this code is as follows: bit 0 in the user rnat corresponds to some
- * bit N (0 <= N <= 62) in one of the kernel rnat value.  The kernel rnat value holding
- * this bit is stored in variable rnat0.  rnat1 is loaded with the kernel rnat value that
+ * The way to think of this code is as follows: bit 0 in the user rnat
+ * corresponds to some bit N (0 <= N <= 62) in one of the kernel rnat
+ * value.  The kernel rnat value holding this bit is stored in
+ * variable rnat0.  rnat1 is loaded with the kernel rnat value that
  * form the upper bits of the user rnat value.
  *
  * Boundary cases:
  *
- * o when reading the rnat "below" the first rnat slot on the kernel backing store,
- *   rnat0/rnat1 are set to 0 and the low order bits are merged in from pt->ar_rnat.
+ * o when reading the rnat "below" the first rnat slot on the kernel
+ *   backing store, rnat0/rnat1 are set to 0 and the low order bits are
+ *   merged in from pt->ar_rnat.
  *
- * o when reading the rnat "above" the last rnat slot on the kernel backing store,
- *   rnat0/rnat1 gets its value from sw->ar_rnat.
+ * o when reading the rnat "above" the last rnat slot on the kernel
+ *   backing store, rnat0/rnat1 gets its value from sw->ar_rnat.
  */
 static unsigned long
 get_rnat (struct task_struct *task, struct switch_stack *sw,
-	  unsigned long *krbs, unsigned long *urnat_addr, unsigned long *urbs_end)
+	  unsigned long *krbs, unsigned long *urnat_addr,
+	  unsigned long *urbs_end)
 {
-	unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr, umask = 0, mask, m;
+	unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr;
+	unsigned long umask = 0, mask, m;
 	unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
 	long num_regs, nbits;
 	struct pt_regs *pt;
@@ -251,11 +260,12 @@
 		nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
 	else
 		nbits = 63;
-	mask = (1UL << nbits) - 1;
+	mask = MASK(nbits);
 	/*
-	 * First, figure out which bit number slot 0 in user-land maps to in the kernel
-	 * rnat.  Do this by figuring out how many register slots we're beyond the user's
-	 * backingstore and then computing the equivalent address in kernel space.
+	 * First, figure out which bit number slot 0 in user-land maps
+	 * to in the kernel rnat.  Do this by figuring out how many
+	 * register slots we're beyond the user's backingstore and
+	 * then computing the equivalent address in kernel space.
 	 */
 	num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
 	slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
@@ -265,7 +275,7 @@
 
 	if (ubspstore + 63 > urnat_addr) {
 		/* some bits need to be merged in from pt->ar_rnat */
-		umask = ((1UL << ia64_rse_slot_num(ubspstore)) - 1) & mask;
+		umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
 		urnat = (pt->ar_rnat & umask);
 		mask &= ~umask;
 		if (!mask)
@@ -323,12 +333,13 @@
 			return;
 		nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
 	}
-	mask = (1UL << nbits) - 1;
+	mask = MASK(nbits);
 
 	/*
-	 * First, figure out which bit number slot 0 in user-land maps to in the kernel
-	 * rnat.  Do this by figuring out how many register slots we're beyond the user's
-	 * backingstore and then computing the equivalent address in kernel space.
+	 * First, figure out which bit number slot 0 in user-land maps
+	 * to in the kernel rnat.  Do this by figuring out how many
+	 * register slots we're beyond the user's backingstore and
+	 * then computing the equivalent address in kernel space.
 	 */
 	num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
 	slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
@@ -338,7 +349,7 @@
 
 	if (ubspstore + 63 > urnat_addr) {
 		/* some bits need to be place in pt->ar_rnat: */
-		umask = ((1UL << ia64_rse_slot_num(ubspstore)) - 1) & mask;
+		umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
 		pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
 		mask &= ~umask;
 		if (!mask)
@@ -364,25 +375,28 @@
 }
 
 static inline int
-on_kernel_rbs (unsigned long addr, unsigned long bspstore, unsigned long urbs_end)
+on_kernel_rbs (unsigned long addr, unsigned long bspstore,
+	       unsigned long urbs_end)
 {
-	return (addr >= bspstore
-		&& addr <= (unsigned long) ia64_rse_rnat_addr((unsigned long *) urbs_end));
+	unsigned long *rnat_addr = ia64_rse_rnat_addr((unsigned long *)
+						      urbs_end);
+	return (addr >= bspstore && addr <= (unsigned long) rnat_addr);
 }
 
 /*
- * Read a word from the user-level backing store of task CHILD.  ADDR is the user-level
- * address to read the word from, VAL a pointer to the return value, and USER_BSP gives
- * the end of the user-level backing store (i.e., it's the address that would be in ar.bsp
- * after the user executed a "cover" instruction).
+ * Read a word from the user-level backing store of task CHILD.  ADDR
+ * is the user-level address to read the word from, VAL a pointer to
+ * the return value, and USER_BSP gives the end of the user-level
+ * backing store (i.e., it's the address that would be in ar.bsp after
+ * the user executed a "cover" instruction).
  *
- * This routine takes care of accessing the kernel register backing store for those
- * registers that got spilled there.  It also takes care of calculating the appropriate
- * RNaT collection words.
+ * This routine takes care of accessing the kernel register backing
+ * store for those registers that got spilled there.  It also takes
+ * care of calculating the appropriate RNaT collection words.
  */
 long
-ia64_peek (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
-	   unsigned long addr, long *val)
+ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
+	   unsigned long user_rbs_end, unsigned long addr, long *val)
 {
 	unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
 	struct pt_regs *child_regs;
@@ -394,10 +408,13 @@
 	child_regs = ia64_task_regs(child);
 	bspstore = (unsigned long *) child_regs->ar_bspstore;
 	krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
-	if (on_kernel_rbs(addr, (unsigned long) bspstore, (unsigned long) urbs_end)) {
+	if (on_kernel_rbs(addr, (unsigned long) bspstore,
+			  (unsigned long) urbs_end))
+	{
 		/*
-		 * Attempt to read the RBS in an area that's actually on the kernel RBS =>
-		 * read the corresponding bits in the kernel RBS.
+		 * Attempt to read the RBS in an area that's actually
+		 * on the kernel RBS => read the corresponding bits in
+		 * the kernel RBS.
 		 */
 		rnat_addr = ia64_rse_rnat_addr(laddr);
 		ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
@@ -410,18 +427,23 @@
 
 		if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
 			/*
-			 * It is implementation dependent whether the data portion of a
-			 * NaT value gets saved on a st8.spill or RSE spill (e.g., see
-			 * EAS 2.6, 4.4.4.6 Register Spill and Fill).  To get consistent
-			 * behavior across all possible IA-64 implementations, we return
-			 * zero in this case.
+			 * It is implementation dependent whether the
+			 * data portion of a NaT value gets saved on a
+			 * st8.spill or RSE spill (e.g., see EAS 2.6,
+			 * 4.4.4.6 Register Spill and Fill).  To get
+			 * consistent behavior across all possible
+			 * IA-64 implementations, we return zero in
+			 * this case.
 			 */
 			*val = 0;
 			return 0;
 		}
 
 		if (laddr < urbs_end) {
-			/* the desired word is on the kernel RBS and is not a NaT */
+			/*
+			 * The desired word is on the kernel RBS and
+			 * is not a NaT.
+			 */
 			regnum = ia64_rse_num_regs(bspstore, laddr);
 			*val = *ia64_rse_skip_regs(krbs, regnum);
 			return 0;
@@ -435,43 +457,51 @@
 }
 
 long
-ia64_poke (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
-	   unsigned long addr, long val)
+ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
+	   unsigned long user_rbs_end, unsigned long addr, long val)
 {
-	unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end = (long *) user_rbs_end;
+	unsigned long *bspstore, *krbs, regnum, *laddr;
+	unsigned long *urbs_end = (long *) user_rbs_end;
 	struct pt_regs *child_regs;
 
 	laddr = (unsigned long *) addr;
 	child_regs = ia64_task_regs(child);
 	bspstore = (unsigned long *) child_regs->ar_bspstore;
 	krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
-	if (on_kernel_rbs(addr, (unsigned long) bspstore, (unsigned long) urbs_end)) {
+	if (on_kernel_rbs(addr, (unsigned long) bspstore,
+			  (unsigned long) urbs_end))
+	{
 		/*
-		 * Attempt to write the RBS in an area that's actually on the kernel RBS
-		 * => write the corresponding bits in the kernel RBS.
+		 * Attempt to write the RBS in an area that's actually
+		 * on the kernel RBS => write the corresponding bits
+		 * in the kernel RBS.
 		 */
 		if (ia64_rse_is_rnat_slot(laddr))
-			put_rnat(child, child_stack, krbs, laddr, val, urbs_end);
+			put_rnat(child, child_stack, krbs, laddr, val,
+				 urbs_end);
 		else {
 			if (laddr < urbs_end) {
 				regnum = ia64_rse_num_regs(bspstore, laddr);
 				*ia64_rse_skip_regs(krbs, regnum) = val;
 			}
 		}
-	} else if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val)) {
+	} else if (access_process_vm(child, addr, &val, sizeof(val), 1)
+		   != sizeof(val))
 		return -EIO;
-	}
 	return 0;
 }
 
 /*
- * Calculate the address of the end of the user-level register backing store.  This is the
- * address that would have been stored in ar.bsp if the user had executed a "cover"
- * instruction right before entering the kernel.  If CFMP is not NULL, it is used to
- * return the "current frame mask" that was active at the time the kernel was entered.
+ * Calculate the address of the end of the user-level register backing
+ * store.  This is the address that would have been stored in ar.bsp
+ * if the user had executed a "cover" instruction right before
+ * entering the kernel.  If CFMP is not NULL, it is used to return the
+ * "current frame mask" that was active at the time the kernel was
+ * entered.
  */
 unsigned long
-ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt, unsigned long *cfmp)
+ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt,
+		       unsigned long *cfmp)
 {
 	unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
 	long ndirty;
@@ -491,9 +521,11 @@
 }
 
 /*
- * Synchronize (i.e, write) the RSE backing store living in kernel space to the VM of the
- * CHILD task.  SW and PT are the pointers to the switch_stack and pt_regs structures,
- * respectively.  USER_RBS_END is the user-level address at which the backing store ends.
+ * Synchronize (i.e, write) the RSE backing store living in kernel
+ * space to the VM of the CHILD task.  SW and PT are the pointers to
+ * the switch_stack and pt_regs structures, respectively.
+ * USER_RBS_END is the user-level address at which the backing store
+ * ends.
  */
 long
 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
@@ -507,7 +539,8 @@
 		ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
 		if (ret < 0)
 			return ret;
-		if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val))
+		if (access_process_vm(child, addr, &val, sizeof(val), 1)
+		    != sizeof(val))
 			return -EIO;
 	}
 	return 0;
@@ -521,13 +554,14 @@
 
 	if (ptrace_check_attach(thread, 0) < 0)
 		/*
-		 * If the thread is not in an attachable state, we'll ignore it.
-		 * The net effect is that if ADDR happens to overlap with the
-		 * portion of the thread's register backing store that is
-		 * currently residing on the thread's kernel stack, then ptrace()
-		 * may end up accessing a stale value.  But if the thread isn't
-		 * stopped, that's a problem anyhow, so we're doing as well as we
-		 * can...
+		 * If the thread is not in an attachable state, we'll
+		 * ignore it.  The net effect is that if ADDR happens
+		 * to overlap with the portion of the thread's
+		 * register backing store that is currently residing
+		 * on the thread's kernel stack, then ptrace() may end
+		 * up accessing a stale value.  But if the thread
+		 * isn't stopped, that's a problem anyhow, so we're
+		 * doing as well as we can...
 		 */
 		return 0;
 
@@ -540,10 +574,11 @@
 }
 
 /*
- * GDB apparently wants to be able to read the register-backing store of any thread when
- * attached to a given process.  If we are peeking or poking an address that happens to
- * reside in the kernel-backing store of another thread, we need to attach to that thread,
- * because otherwise we end up accessing stale data.
+ * GDB apparently wants to be able to read the register-backing store
+ * of any thread when attached to a given process.  If we are peeking
+ * or poking an address that happens to reside in the kernel-backing
+ * store of another thread, we need to attach to that thread, because
+ * otherwise we end up accessing stale data.
  *
  * task_list_lock must be read-locked before calling this routine!
  */
@@ -557,7 +592,8 @@
 	if (!(mm = get_task_mm(child)))
 		return child;
 
-	mm_users = atomic_read(&mm->mm_users) - 1;	/* -1 because of our get_task_mm()... */
+	/* -1 because of our get_task_mm(): */
+	mm_users = atomic_read(&mm->mm_users) - 1;
 	if (mm_users <= 1)
 		goto out;		/* not multi-threaded */
 
@@ -627,7 +663,8 @@
 }
 
 static int
-access_fr (struct unw_frame_info *info, int regnum, int hi, unsigned long *data, int write_access)
+access_fr (struct unw_frame_info *info, int regnum, int hi,
+	   unsigned long *data, int write_access)
 {
 	struct ia64_fpreg fpval;
 	int ret;
@@ -649,7 +686,8 @@
  * kernel exit-path, rather than the syscall-exit path.
  */
 static void
-convert_to_non_syscall (struct task_struct *child, struct pt_regs  *pt, unsigned long cfm)
+convert_to_non_syscall (struct task_struct *child, struct pt_regs  *pt,
+			unsigned long cfm)
 {
 	struct unw_frame_info info, prev_info;
 	unsigned long ip, pr;
@@ -674,11 +712,51 @@
 }
 
 static int
-access_uarea (struct task_struct *child, unsigned long addr, unsigned long *data, int write_access)
+access_nat_bits (struct task_struct *child, struct pt_regs *pt,
+		 struct unw_frame_info *info,
+		 unsigned long *data, int write_access)
+{
+	unsigned long regnum, nat_bits, scratch_unat, dummy = 0;
+	char nat = 0;
+
+	if (write_access) {
+		nat_bits = *data;
+		scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
+		if (unw_set_ar(info, UNW_AR_UNAT, scratch_unat) < 0) {
+			dprintk("ptrace: failed to set ar.unat\n");
+			return -1;
+		}
+		for (regnum = 4; regnum <= 7; ++regnum) {
+			unw_get_gr(info, regnum, &dummy, &nat);
+			unw_set_gr(info, regnum, dummy,
+				   (nat_bits >> regnum) & 1);
+		}
+	} else {
+		if (unw_get_ar(info, UNW_AR_UNAT, &scratch_unat) < 0) {
+			dprintk("ptrace: failed to read ar.unat\n");
+			return -1;
+		}
+		nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
+		for (regnum = 4; regnum <= 7; ++regnum) {
+			unw_get_gr(info, regnum, &dummy, &nat);
+			nat_bits |= (nat != 0) << regnum;
+		}
+		*data = nat_bits;
+	}
+	return 0;
+}
+
+static int
+access_uarea (struct task_struct *child, unsigned long addr,
+	      unsigned long *data, int write_access)
 {
 	unsigned long *ptr, regnum, urbs_end, rnat_addr, cfm;
 	struct switch_stack *sw;
 	struct pt_regs *pt;
+#	define pt_reg_addr(pt, reg)	((void *)			    \
+					 ((unsigned long) (pt)		    \
+					  + offsetof(struct pt_regs, reg)))
+
 
 	pt = ia64_task_regs(child);
 	sw = (struct switch_stack *) (child->thread.ksp + 16);
@@ -694,17 +772,20 @@
 			ia64_sync_fph(child);
 		else
 			ia64_flush_fph(child);
-		ptr = (unsigned long *) ((unsigned long) &child->thread.fph + addr);
+		ptr = (unsigned long *)
+			((unsigned long) &child->thread.fph + addr);
 	} else if ((addr >= PT_F10) && (addr < PT_F11 + 16)) {
 		/* scratch registers untouched by kernel (saved in pt_regs) */
-		ptr = (unsigned long *)
-			((long) pt + offsetof(struct pt_regs, f10) + addr - PT_F10);
+		ptr = pt_reg_addr(pt, f10) + (addr - PT_F10);
 	} else if (addr >= PT_F12 && addr < PT_F15 + 16) {
-		/* scratch registers untouched by kernel (saved in switch_stack) */
-		ptr = (unsigned long *) ((long) sw + (addr - PT_NAT_BITS - 32));
+		/*
+		 * Scratch registers untouched by kernel (saved in
+		 * switch_stack).
+		 */
+		ptr = (unsigned long *) ((long) sw
+					 + (addr - PT_NAT_BITS - 32));
 	} else if (addr < PT_AR_LC + 8) {
 		/* preserved state: */
-		unsigned long nat_bits, scratch_unat, dummy = 0;
 		struct unw_frame_info info;
 		char nat = 0;
 		int ret;
@@ -715,62 +796,48 @@
 
 		switch (addr) {
 		      case PT_NAT_BITS:
-			if (write_access) {
-				nat_bits = *data;
-				scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
-				if (unw_set_ar(&info, UNW_AR_UNAT, scratch_unat) < 0) {
-					dprintk("ptrace: failed to set ar.unat\n");
-					return -1;
-				}
-				for (regnum = 4; regnum <= 7; ++regnum) {
-					unw_get_gr(&info, regnum, &dummy, &nat);
-					unw_set_gr(&info, regnum, dummy, (nat_bits >> regnum) & 1);
-				}
-			} else {
-				if (unw_get_ar(&info, UNW_AR_UNAT, &scratch_unat) < 0) {
-					dprintk("ptrace: failed to read ar.unat\n");
-					return -1;
-				}
-				nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
-				for (regnum = 4; regnum <= 7; ++regnum) {
-					unw_get_gr(&info, regnum, &dummy, &nat);
-					nat_bits |= (nat != 0) << regnum;
-				}
-				*data = nat_bits;
-			}
-			return 0;
+			return access_nat_bits(child, pt, &info,
+					       data, write_access);
 
 		      case PT_R4: case PT_R5: case PT_R6: case PT_R7:
 			if (write_access) {
 				/* read NaT bit first: */
 				unsigned long dummy;
 
-				ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4, &dummy, &nat);
+				ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4,
+						 &dummy, &nat);
 				if (ret < 0)
 					return ret;
 			}
-			return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data, &nat,
-					     write_access);
+			return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data,
+					     &nat, write_access);
 
-		      case PT_B1: case PT_B2: case PT_B3: case PT_B4: case PT_B5:
-			return unw_access_br(&info, (addr - PT_B1)/8 + 1, data, write_access);
+		      case PT_B1: case PT_B2: case PT_B3:
+		      case PT_B4: case PT_B5:
+			return unw_access_br(&info, (addr - PT_B1)/8 + 1, data,
+					     write_access);
 
 		      case PT_AR_EC:
-			return unw_access_ar(&info, UNW_AR_EC, data, write_access);
+			return unw_access_ar(&info, UNW_AR_EC, data,
+					     write_access);
 
 		      case PT_AR_LC:
-			return unw_access_ar(&info, UNW_AR_LC, data, write_access);
+			return unw_access_ar(&info, UNW_AR_LC, data,
+					     write_access);
 
 		      default:
 			if (addr >= PT_F2 && addr < PT_F5 + 16)
-				return access_fr(&info, (addr - PT_F2)/16 + 2, (addr & 8) != 0,
-						 data, write_access);
+				return access_fr(&info, (addr - PT_F2)/16 + 2,
+						 (addr & 8) != 0, data,
+						 write_access);
 			else if (addr >= PT_F16 && addr < PT_F31 + 16)
-				return access_fr(&info, (addr - PT_F16)/16 + 16, (addr & 8) != 0,
+				return access_fr(&info,
+						 (addr - PT_F16)/16 + 16,
+						 (addr & 8) != 0,
 						 data, write_access);
 			else {
-				dprintk("ptrace: rejecting access to register address 0x%lx\n",
-					addr);
+				dprintk("ptrace: rejecting access to register "
+					"address 0x%lx\n", addr);
 				return -1;
 			}
 		}
@@ -779,34 +846,49 @@
 		switch (addr) {
 		      case PT_AR_BSP:
 			/*
-			 * By convention, we use PT_AR_BSP to refer to the end of the user-level
-			 * backing store.  Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof) to get
-			 * the real value of ar.bsp at the time the kernel was entered.
+			 * By convention, we use PT_AR_BSP to refer to
+			 * the end of the user-level backing store.
+			 * Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
+			 * to get the real value of ar.bsp at the time
+			 * the kernel was entered.
 			 *
-			 * Furthermore, when changing the contents of PT_AR_BSP (or
-			 * PT_CFM) we MUST copy any users-level stacked registers that are
-			 * stored on the kernel stack back to user-space because
-			 * otherwise, we might end up clobbering kernel stacked registers.
-			 * Also, if this happens while the task is blocked in a system
-			 * call, which convert the state such that the non-system-call
-			 * exit path is used.  This ensures that the proper state will be
-			 * picked up when resuming execution.  However, it *also* means
-			 * that once we write PT_AR_BSP/PT_CFM, it won't be possible to
-			 * modify the syscall arguments of the pending system call any
-			 * longer.  This shouldn't be an issue because modifying
-			 * PT_AR_BSP/PT_CFM generally implies that we're either abandoning
-			 * the pending system call or that we defer it's re-execution
-			 * (e.g., due to GDB doing an inferior function call).
+			 * Furthermore, when changing the contents of
+			 * PT_AR_BSP (or PT_CFM) we MUST copy any
+			 * users-level stacked registers that are
+			 * stored on the kernel stack back to
+			 * user-space because otherwise, we might end
+			 * up clobbering kernel stacked registers.
+			 * Also, if this happens while the task is
+			 * blocked in a system call, which convert the
+			 * state such that the non-system-call exit
+			 * path is used.  This ensures that the proper
+			 * state will be picked up when resuming
+			 * execution.  However, it *also* means that
+			 * once we write PT_AR_BSP/PT_CFM, it won't be
+			 * possible to modify the syscall arguments of
+			 * the pending system call any longer.  This
+			 * shouldn't be an issue because modifying
+			 * PT_AR_BSP/PT_CFM generally implies that
+			 * we're either abandoning the pending system
+			 * call or that we defer it's re-execution
+			 * (e.g., due to GDB doing an inferior
+			 * function call).
 			 */
 			urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
 			if (write_access) {
 				if (*data != urbs_end) {
 					if (ia64_sync_user_rbs(child, sw,
-							       pt->ar_bspstore, urbs_end) < 0)
+							       pt->ar_bspstore,
+							       urbs_end) < 0)
 						return -1;
 					if (in_syscall(pt))
-						convert_to_non_syscall(child, pt, cfm);
-					/* simulate user-level write of ar.bsp: */
+						convert_to_non_syscall(child,
+								       pt,
+								       cfm);
+					/*
+					 * Simulate user-level write
+					 * of ar.bsp:
+					 */
 					pt->loadrs = 0;
 					pt->ar_bspstore = *data;
 				}
@@ -817,14 +899,17 @@
 		      case PT_CFM:
 			urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
 			if (write_access) {
-				if (((cfm ^ *data) & 0x3fffffffffUL) != 0) {
+				if (((cfm ^ *data) & PFM_MASK) != 0) {
 					if (ia64_sync_user_rbs(child, sw,
-							       pt->ar_bspstore, urbs_end) < 0)
+							       pt->ar_bspstore,
+							       urbs_end) < 0)
 						return -1;
 					if (in_syscall(pt))
-						convert_to_non_syscall(child, pt, cfm);
-					pt->cr_ifs = ((pt->cr_ifs & ~0x3fffffffffUL)
-						      | (*data & 0x3fffffffffUL));
+						convert_to_non_syscall(child,
+								       pt,
+								       cfm);
+					pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
+						      | (*data & PFM_MASK));
 				}
 			} else
 				*data = cfm;
@@ -832,99 +917,94 @@
 
 		      case PT_CR_IPSR:
 			if (write_access)
-				pt->cr_ipsr = ((*data & IPSR_WRITE_MASK)
-					       | (pt->cr_ipsr & ~IPSR_WRITE_MASK));
+				pt->cr_ipsr = ((*data & IPSR_MASK)
+					       | (pt->cr_ipsr & ~IPSR_MASK));
 			else
-				*data = (pt->cr_ipsr & IPSR_READ_MASK);
+				*data = (pt->cr_ipsr & IPSR_MASK);
 			return 0;
 
 		      case PT_AR_RNAT:
 			urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
-			rnat_addr = (long) ia64_rse_rnat_addr((long *) urbs_end);
+			rnat_addr = (long) ia64_rse_rnat_addr((long *)
+							      urbs_end);
 			if (write_access)
-				return ia64_poke(child, sw, urbs_end, rnat_addr, *data);
+				return ia64_poke(child, sw, urbs_end,
+						 rnat_addr, *data);
 			else
-				return ia64_peek(child, sw, urbs_end, rnat_addr, data);
+				return ia64_peek(child, sw, urbs_end,
+						 rnat_addr, data);
 
 		      case PT_R1:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r1));
+			ptr = pt_reg_addr(pt, r1);
 			break;
-
 		      case PT_R2:  case PT_R3:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, r2) + addr - PT_R2);
+			ptr = pt_reg_addr(pt, r2) + (addr - PT_R2);
 			break;
 		      case PT_R8:  case PT_R9:  case PT_R10: case PT_R11:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, r8)+  addr - PT_R8);
+			ptr = pt_reg_addr(pt, r8) + (addr - PT_R8);
 			break;
 		      case PT_R12: case PT_R13:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, r12)+  addr - PT_R12);
+			ptr = pt_reg_addr(pt, r12) + (addr - PT_R12);
 			break;
 		      case PT_R14:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r14));
+			ptr = pt_reg_addr(pt, r14);
 			break;
 		      case PT_R15:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r15));
+			ptr = pt_reg_addr(pt, r15);
 			break;
 		      case PT_R16: case PT_R17: case PT_R18: case PT_R19:
 		      case PT_R20: case PT_R21: case PT_R22: case PT_R23:
 		      case PT_R24: case PT_R25: case PT_R26: case PT_R27:
 		      case PT_R28: case PT_R29: case PT_R30: case PT_R31:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, r16) + addr - PT_R16);
+			ptr = pt_reg_addr(pt, r16) + (addr - PT_R16);
 			break;
 		      case PT_B0:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b0));
+			ptr = pt_reg_addr(pt, b0);
 			break;
 		      case PT_B6:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b6));
+			ptr = pt_reg_addr(pt, b6);
 			break;
 		      case PT_B7:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b7));
+			ptr = pt_reg_addr(pt, b7);
 			break;
 		      case PT_F6:  case PT_F6+8: case PT_F7: case PT_F7+8:
 		      case PT_F8:  case PT_F8+8: case PT_F9: case PT_F9+8:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, f6) + addr - PT_F6);
+			ptr = pt_reg_addr(pt, f6) + (addr - PT_F6);
 			break;
 		      case PT_AR_BSPSTORE:
-			ptr = (unsigned long *)
-				((long) pt + offsetof(struct pt_regs, ar_bspstore));
+			ptr = pt_reg_addr(pt, ar_bspstore);
 			break;
 		      case PT_AR_RSC:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_rsc));
+			ptr = pt_reg_addr(pt, ar_rsc);
 			break;
 		      case PT_AR_UNAT:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_unat));
+			ptr = pt_reg_addr(pt, ar_unat);
 			break;
 		      case PT_AR_PFS:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_pfs));
+			ptr = pt_reg_addr(pt, ar_pfs);
 			break;
 		      case PT_AR_CCV:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_ccv));
+			ptr = pt_reg_addr(pt, ar_ccv);
 			break;
 		      case PT_AR_FPSR:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_fpsr));
+			ptr = pt_reg_addr(pt, ar_fpsr);
 			break;
 		      case PT_CR_IIP:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, cr_iip));
+			ptr = pt_reg_addr(pt, cr_iip);
 			break;
 		      case PT_PR:
-			ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, pr));
+			ptr = pt_reg_addr(pt, pr);
 			break;
 			/* scratch register */
 
 		      default:
 			/* disallow accessing anything else... */
-			dprintk("ptrace: rejecting access to register address 0x%lx\n",
-				addr);
+			dprintk("ptrace: rejecting access to register "
+				"address 0x%lx\n", addr);
 			return -1;
 		}
 	} else if (addr <= PT_AR_SSD) {
-		ptr = (unsigned long *)
-			((long) pt + offsetof(struct pt_regs, ar_csd) + addr - PT_AR_CSD);
+		ptr = pt_reg_addr(pt, ar_csd) + (addr - PT_AR_CSD);
 	} else {
 		/* access debug registers */
 
@@ -937,41 +1017,46 @@
 		}
 
 		if (regnum >= 8) {
-			dprintk("ptrace: rejecting access to register address 0x%lx\n", addr);
+			dprintk("ptrace: rejecting access to register "
+				"address 0x%lx\n", addr);
 			return -1;
 		}
 #ifdef CONFIG_PERFMON
 		/*
-		 * Check if debug registers are used by perfmon. This test must be done
-		 * once we know that we can do the operation, i.e. the arguments are all
-		 * valid, but before we start modifying the state.
+		 * Check if debug registers are used by perfmon. This
+		 * test must be done once we know that we can do the
+		 * operation, i.e. the arguments are all valid, but
+		 * before we start modifying the state.
 		 *
-		 * Perfmon needs to keep a count of how many processes are trying to
-		 * modify the debug registers for system wide monitoring sessions.
+		 * Perfmon needs to keep a count of how many processes
+		 * are trying to modify the debug registers for system
+		 * wide monitoring sessions.
 		 *
-		 * We also include read access here, because they may cause the
-		 * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two
-		 * arrays are also used by perfmon, but we do not use
-		 * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context
-		 * switch code.
+		 * We also include read access here, because they may
+		 * cause the PMU-installed debug register state
+		 * (dbr[], ibr[]) to be reset. The two arrays are also
+		 * used by perfmon, but we do not use
+		 * IA64_THREAD_DBG_VALID. The registers are restored
+		 * by the PMU context switch code.
 		 */
 		if (pfm_use_debug_registers(child)) return -1;
 #endif
 
 		if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
 			child->thread.flags |= IA64_THREAD_DBG_VALID;
-			memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
-			memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
+			memset(child->thread.dbr, 0,
+			       sizeof(child->thread.dbr));
+			memset(child->thread.ibr, 0,
+			       sizeof(child->thread.ibr));
 		}
 
 		ptr += regnum;
 
-		if (write_access)
-			/* don't let the user set kernel-level breakpoints... */
+		if ((regnum & 1) && write_access) {
+			/* don't let the user set kernel-level breakpoints: */
 			*ptr = *data & ~(7UL << 56);
-		else
-			*data = *ptr;
-		return 0;
+			return 0;
+		}
 	}
 	if (write_access)
 		*ptr = *data;
@@ -992,7 +1077,8 @@
 	char nat = 0;
 	int i;
 
-	retval = verify_area(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs));
+	retval = verify_area(VERIFY_WRITE, ppr,
+			     sizeof(struct pt_all_user_regs));
 	if (retval != 0) {
 		return -EIO;
 	}
@@ -1094,11 +1180,13 @@
 
 	/* fr6-fr11 */
 
-	retval |= __copy_to_user(&ppr->fr[6], &pt->f6, sizeof(struct ia64_fpreg) * 6);
+	retval |= __copy_to_user(&ppr->fr[6], &pt->f6,
+				 sizeof(struct ia64_fpreg) * 6);
 
 	/* fp scratch regs(12-15) */
 
-	retval |= __copy_to_user(&ppr->fr[12], &sw->f12, sizeof(struct ia64_fpreg) * 4);
+	retval |= __copy_to_user(&ppr->fr[12], &sw->f12,
+				 sizeof(struct ia64_fpreg) * 4);
 
 	/* fr16-fr31 */
 
@@ -1111,7 +1199,8 @@
 	/* fph */
 
 	ia64_flush_fph(child);
-	retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph, sizeof(ppr->fr[32]) * 96);
+	retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph,
+				 sizeof(ppr->fr[32]) * 96);
 
 	/*  preds */
 
@@ -1138,7 +1227,8 @@
 
 	memset(&fpval, 0, sizeof(fpval));
 
-	retval = verify_area(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs));
+	retval = verify_area(VERIFY_READ, ppr,
+			     sizeof(struct pt_all_user_regs));
 	if (retval != 0) {
 		return -EIO;
 	}
@@ -1186,7 +1276,8 @@
 
 	for (i = 4; i < 8; i++) {
 		retval |= __get_user(val, &ppr->gr[i]);
-		if (unw_set_gr(&info, i, val, 0) < 0)	 /* NaT bit will be set via PT_NAT_BITS */
+		/* NaT bit will be set via PT_NAT_BITS: */
+		if (unw_set_gr(&info, i, val, 0) < 0)
 			return -EIO;
 	}
 
@@ -1230,16 +1321,19 @@
 
 	/* fr6-fr11 */
 
-	retval |= __copy_from_user(&pt->f6, &ppr->fr[6], sizeof(ppr->fr[6]) * 6);
+	retval |= __copy_from_user(&pt->f6, &ppr->fr[6],
+				   sizeof(ppr->fr[6]) * 6);
 
 	/* fp scratch regs(12-15) */
 
-	retval |= __copy_from_user(&sw->f12, &ppr->fr[12], sizeof(ppr->fr[12]) * 4);
+	retval |= __copy_from_user(&sw->f12, &ppr->fr[12],
+				   sizeof(ppr->fr[12]) * 4);
 
 	/* fr16-fr31 */
 
 	for (i = 16; i < 32; i++) {
-		retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
+		retval |= __copy_from_user(&fpval, &ppr->fr[i],
+					   sizeof(fpval));
 		if (unw_set_fr(&info, i, fpval) < 0)
 			return -EIO;
 	}
@@ -1247,7 +1341,8 @@
 	/* fph */
 
 	ia64_sync_fph(child);
-	retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32], sizeof(ppr->fr[32]) * 96);
+	retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32],
+				   sizeof(ppr->fr[32]) * 96);
 
 	/* preds */
 
@@ -1279,16 +1374,15 @@
 {
 	struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child));
 
-	/* make sure the single step/take-branch tra bits are not set: */
+	/* make sure the single step/taken-branch trap bits are not set: */
 	child_psr->ss = 0;
 	child_psr->tb = 0;
 }
 
 asmlinkage long
-sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data,
-	    long arg4, long arg5, long arg6, long arg7, long stack)
+sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data)
 {
-	struct pt_regs *pt, *regs = (struct pt_regs *) &stack;
+	struct pt_regs *pt;
 	unsigned long urbs_end, peek_or_poke;
 	struct task_struct *child;
 	struct switch_stack *sw;
@@ -1308,8 +1402,10 @@
 		goto out;
 	}
 
-	peek_or_poke = (request == PTRACE_PEEKTEXT || request == PTRACE_PEEKDATA
-			|| request == PTRACE_POKETEXT || request == PTRACE_POKEDATA);
+	peek_or_poke = (request == PTRACE_PEEKTEXT
+			|| request == PTRACE_PEEKDATA
+			|| request == PTRACE_POKETEXT
+			|| request == PTRACE_POKEDATA);
 	ret = -ESRCH;
 	read_lock(&tasklist_lock);
 	{
@@ -1341,31 +1437,37 @@
 
 	switch (request) {
 	      case PTRACE_PEEKTEXT:
-	      case PTRACE_PEEKDATA:		/* read word at location addr */
+	      case PTRACE_PEEKDATA:
+		/* read word at location addr */
 		urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
 		ret = ia64_peek(child, sw, urbs_end, addr, &data);
 		if (ret == 0) {
 			ret = data;
-			regs->r8 = 0;	/* ensure "ret" is not mistaken as an error code */
+			/* ensure "ret" is not mistaken as an error code: */
+			force_successful_syscall_return();
 		}
 		goto out_tsk;
 
 	      case PTRACE_POKETEXT:
-	      case PTRACE_POKEDATA:		/* write the word at location addr */
+	      case PTRACE_POKEDATA:
+		/* write the word at location addr */
 		urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
 		ret = ia64_poke(child, sw, urbs_end, addr, data);
 		goto out_tsk;
 
-	      case PTRACE_PEEKUSR:		/* read the word at addr in the USER area */
+	      case PTRACE_PEEKUSR:
+		/* read the word at addr in the USER area */
 		if (access_uarea(child, addr, &data, 0) < 0) {
 			ret = -EIO;
 			goto out_tsk;
 		}
 		ret = data;
-		regs->r8 = 0;	/* ensure "ret" is not mistaken as an error code */
+		/* ensure "ret" is not mistaken as an error code */
+		force_successful_syscall_return();
 		goto out_tsk;
 
-	      case PTRACE_POKEUSR:	      /* write the word at addr in the USER area */
+	      case PTRACE_POKEUSR:
+		/* write the word at addr in the USER area */
 		if (access_uarea(child, addr, &data, 1) < 0) {
 			ret = -EIO;
 			goto out_tsk;
@@ -1373,16 +1475,20 @@
 		ret = 0;
 		goto out_tsk;
 
-	      case PTRACE_OLD_GETSIGINFO:		/* for backwards-compatibility */
+	      case PTRACE_OLD_GETSIGINFO:
+		/* for backwards-compatibility */
 		ret = ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
 		goto out_tsk;
 
-	      case PTRACE_OLD_SETSIGINFO:		/* for backwards-compatibility */
+	      case PTRACE_OLD_SETSIGINFO:
+		/* for backwards-compatibility */
 		ret = ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
 		goto out_tsk;
 
-	      case PTRACE_SYSCALL:	/* continue and stop at next (return from) syscall */
-	      case PTRACE_CONT:		/* restart after signal. */
+	      case PTRACE_SYSCALL:
+		/* continue and stop at next (return from) syscall */
+	      case PTRACE_CONT:
+		/* restart after signal. */
 		ret = -EIO;
 		if (data > _NSIG)
 			goto out_tsk;
@@ -1392,7 +1498,10 @@
 			clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
 		child->exit_code = data;
 
-		/* make sure the single step/taken-branch trap bits are not set: */
+		/*
+		 * Make sure the single step/taken-branch trap bits
+		 * are not set:
+		 */
 		ia64_psr(pt)->ss = 0;
 		ia64_psr(pt)->tb = 0;
 
@@ -1406,19 +1515,18 @@
 		 * sigkill.  Perhaps it should be put in the status
 		 * that it wants to exit.
 		 */
-		if (child->exit_state == EXIT_ZOMBIE)		/* already dead */
+		if (child->exit_state == EXIT_ZOMBIE)
+			/* already dead */
 			goto out_tsk;
 		child->exit_code = SIGKILL;
 
-		/* make sure the single step/take-branch tra bits are not set: */
-		ia64_psr(pt)->ss = 0;
-		ia64_psr(pt)->tb = 0;
-
+		ptrace_disable(child);
 		wake_up_process(child);
 		ret = 0;
 		goto out_tsk;
 
-	      case PTRACE_SINGLESTEP:		/* let child execute for one instruction */
+	      case PTRACE_SINGLESTEP:
+		/* let child execute for one instruction */
 	      case PTRACE_SINGLEBLOCK:
 		ret = -EIO;
 		if (data > _NSIG)
@@ -1437,16 +1545,19 @@
 		ret = 0;
 		goto out_tsk;
 
-	      case PTRACE_DETACH:		/* detach a process that was attached. */
+	      case PTRACE_DETACH:
+		/* detach a process that was attached. */
 		ret = ptrace_detach(child, data);
 		goto out_tsk;
 
 	      case PTRACE_GETREGS:
-		ret = ptrace_getregs(child, (struct pt_all_user_regs __user *) data);
+		ret = ptrace_getregs(child,
+				     (struct pt_all_user_regs __user *) data);
 		goto out_tsk;
 
 	      case PTRACE_SETREGS:
-		ret = ptrace_setregs(child, (struct pt_all_user_regs __user *) data);
+		ret = ptrace_setregs(child,
+				     (struct pt_all_user_regs __user *) data);
 		goto out_tsk;
 
 	      default:
@@ -1469,15 +1580,16 @@
 	if (!(current->ptrace & PT_PTRACED))
 		return;
 	/*
-	 * The 0x80 provides a way for the tracing parent to distinguish between a syscall
-	 * stop and SIGTRAP delivery.
+	 * The 0x80 provides a way for the tracing parent to
+	 * distinguish between a syscall stop and SIGTRAP delivery.
 	 */
-	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
+	ptrace_notify(SIGTRAP
+		      | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
 
 	/*
-	 * This isn't the same as continuing with a signal, but it will do for normal use.
-	 * strace only continues with a signal if the stopping signal is not SIGTRAP.
-	 * -brl
+	 * This isn't the same as continuing with a signal, but it
+	 * will do for normal use.  strace only continues with a
+	 * signal if the stopping signal is not SIGTRAP.  -brl
 	 */
 	if (current->exit_code) {
 		send_sig(current->exit_code, current, 1);
@@ -1489,21 +1601,22 @@
 
 asmlinkage void
 syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
-		     long arg4, long arg5, long arg6, long arg7, long stack)
+		     long arg4, long arg5, long arg6, long arg7,
+		     struct pt_regs regs)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
 	long syscall;
 
 	if (unlikely(current->audit_context)) {
-		if (IS_IA32_PROCESS(regs))
-			syscall = regs->r1;
+		if (IS_IA32_PROCESS(&regs))
+			syscall = regs.r1;
 		else
-			syscall = regs->r15;
+			syscall = regs.r15;
 
 		audit_syscall_entry(current, syscall, arg0, arg1, arg2, arg3);
 	}
 
-	if (test_thread_flag(TIF_SYSCALL_TRACE) && (current->ptrace & PT_PTRACED))
+	if (test_thread_flag(TIF_SYSCALL_TRACE)
+	    && (current->ptrace & PT_PTRACED))
 		syscall_trace();
 }
 
@@ -1511,11 +1624,13 @@
 
 asmlinkage void
 syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
-		     long arg4, long arg5, long arg6, long arg7, long stack)
+		     long arg4, long arg5, long arg6, long arg7,
+		     struct pt_regs regs)
 {
 	if (unlikely(current->audit_context))
-		audit_syscall_exit(current, ((struct pt_regs *) &stack)->r8);
+		audit_syscall_exit(current, regs.r8);
 
-	if (test_thread_flag(TIF_SYSCALL_TRACE) && (current->ptrace & PT_PTRACED))
+	if (test_thread_flag(TIF_SYSCALL_TRACE)
+	    && (current->ptrace & PT_PTRACED))
 		syscall_trace();
 }
diff -Nru a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
--- a/arch/ia64/kernel/setup.c	2005-01-18 12:06:18 -08:00
+++ b/arch/ia64/kernel/setup.c	2005-02-02 12:21:27 -08:00
@@ -60,7 +60,6 @@
 unsigned long __per_cpu_offset[NR_CPUS];
 EXPORT_SYMBOL(__per_cpu_offset);
 #endif
-unsigned long __per_cpu_mca[NR_CPUS];
 
 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
@@ -388,7 +387,7 @@
 	/* enable IA-64 Machine Check Abort Handling unless disabled */
 	if (!strstr(saved_command_line, "nomca"))
 		ia64_mca_init();
-	
+
 	platform_setup(cmdline_p);
 	paging_init();
 }
@@ -602,7 +601,6 @@
 cpu_init (void)
 {
 	extern void __devinit ia64_mmu_init (void *);
-	extern void set_mca_pointer (struct cpuinfo_ia64 *, void *);
 	unsigned long num_phys_stacked;
 	pal_vm_info_2_u_t vmi;
 	unsigned int max_ctx;
@@ -611,6 +609,14 @@
 
 	cpu_data = per_cpu_init();
 
+	/*
+	 * We set ar.k3 so that assembly code in MCA handler can compute
+	 * physical addresses of per cpu variables with a simple:
+	 *   phys = ar.k3 + &per_cpu_var
+	 */
+	ia64_set_kr(IA64_KR_PER_CPU_DATA,
+		    ia64_tpa(cpu_data) - (long) __per_cpu_start);
+
 	get_max_cacheline_size();
 
 	/*
@@ -657,7 +663,7 @@
 		BUG();
 
 	ia64_mmu_init(ia64_imva(cpu_data));
-	set_mca_pointer(cpu_info, cpu_data);
+	ia64_mca_cpu_init(ia64_imva(cpu_data));
 
 #ifdef CONFIG_IA32_SUPPORT
 	ia32_cpu_init();
diff -Nru a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c
--- a/arch/ia64/kernel/signal.c	2004-12-13 15:10:01 -08:00
+++ b/arch/ia64/kernel/signal.c	2005-01-25 12:23:45 -08:00
@@ -84,12 +84,11 @@
 }
 
 asmlinkage long
-sys_sigaltstack (const stack_t __user *uss, stack_t __user *uoss, long arg2, long arg3, long arg4,
-		 long arg5, long arg6, long arg7, long stack)
+sys_sigaltstack (const stack_t __user *uss, stack_t __user *uoss, long arg2,
+		 long arg3, long arg4, long arg5, long arg6, long arg7,
+		 struct pt_regs regs)
 {
-	struct pt_regs *pt = (struct pt_regs *) &stack;
-
-	return do_sigaltstack(uss, uoss, pt->r12);
+	return do_sigaltstack(uss, uoss, regs.r12);
 }
 
 static long
diff -Nru a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
--- a/arch/ia64/kernel/sys_ia64.c	2004-10-18 22:26:36 -07:00
+++ b/arch/ia64/kernel/sys_ia64.c	2005-01-25 12:23:45 -08:00
@@ -2,7 +2,7 @@
  * This file contains various system calls that have different calling
  * conventions on different platforms.
  *
- * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co
+ * Copyright (C) 1999-2000, 2002-2003, 2005 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <linux/config.h>
@@ -163,10 +163,9 @@
  * and r9) as this is faster than doing a copy_to_user().
  */
 asmlinkage long
-sys_pipe (long arg0, long arg1, long arg2, long arg3,
-	  long arg4, long arg5, long arg6, long arg7, long stack)
+sys_pipe (void)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
+	struct pt_regs *regs = ia64_task_regs(current);
 	int fd[2];
 	int retval;
 
diff -Nru a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c
--- a/arch/ia64/kernel/traps.c	2004-10-05 11:27:40 -07:00
+++ b/arch/ia64/kernel/traps.c	2005-01-25 12:23:45 -08:00
@@ -358,11 +358,10 @@
 };
 
 struct illegal_op_return
-ia64_illegal_op_fault (unsigned long ec, unsigned long arg1, unsigned long arg2,
-		       unsigned long arg3, unsigned long arg4, unsigned long arg5,
-		       unsigned long arg6, unsigned long arg7, unsigned long stack)
+ia64_illegal_op_fault (unsigned long ec, long arg1, long arg2, long arg3,
+		       long arg4, long arg5, long arg6, long arg7,
+		       struct pt_regs regs)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
 	struct illegal_op_return rv;
 	struct siginfo si;
 	char buf[128];
@@ -371,19 +370,19 @@
 	{
 		extern struct illegal_op_return ia64_emulate_brl (struct pt_regs *, unsigned long);
 
-		rv = ia64_emulate_brl(regs, ec);
+		rv = ia64_emulate_brl(&regs, ec);
 		if (rv.fkt != (unsigned long) -1)
 			return rv;
 	}
 #endif
 
 	sprintf(buf, "IA-64 Illegal operation fault");
-	die_if_kernel(buf, regs, 0);
+	die_if_kernel(buf, &regs, 0);
 
 	memset(&si, 0, sizeof(si));
 	si.si_signo = SIGILL;
 	si.si_code = ILL_ILLOPC;
-	si.si_addr = (void __user *) (regs->cr_iip + ia64_psr(regs)->ri);
+	si.si_addr = (void __user *) (regs.cr_iip + ia64_psr(&regs)->ri);
 	force_sig_info(SIGILL, &si, current);
 	rv.fkt = 0;
 	return rv;
@@ -391,11 +390,10 @@
 
 void
 ia64_fault (unsigned long vector, unsigned long isr, unsigned long ifa,
-	    unsigned long iim, unsigned long itir, unsigned long arg5,
-	    unsigned long arg6, unsigned long arg7, unsigned long stack)
+	    unsigned long iim, unsigned long itir, long arg5, long arg6,
+	    long arg7, struct pt_regs regs)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
-	unsigned long code, error = isr;
+	unsigned long code, error = isr, iip;
 	struct siginfo siginfo;
 	char buf[128];
 	int result, sig;
@@ -415,10 +413,12 @@
 		 * This fault was due to lfetch.fault, set "ed" bit in the psr to cancel
 		 * the lfetch.
 		 */
-		ia64_psr(regs)->ed = 1;
+		ia64_psr(&regs)->ed = 1;
 		return;
 	}
 
+	iip = regs.cr_iip + ia64_psr(&regs)->ri;
+
 	switch (vector) {
 	      case 24: /* General Exception */
 		code = (isr >> 4) & 0xf;
@@ -428,8 +428,8 @@
 		if (code == 8) {
 # ifdef CONFIG_IA64_PRINT_HAZARDS
 			printk("%s[%d]: possible hazard @ ip=%016lx (pr = %016lx)\n",
-			       current->comm, current->pid, regs->cr_iip + ia64_psr(regs)->ri,
-			       regs->pr);
+			       current->comm, current->pid,
+			       regs.cr_iip + ia64_psr(&regs)->ri, regs.pr);
 # endif
 			return;
 		}
@@ -437,14 +437,14 @@
 
 	      case 25: /* Disabled FP-Register */
 		if (isr & 2) {
-			disabled_fph_fault(regs);
+			disabled_fph_fault(&regs);
 			return;
 		}
 		sprintf(buf, "Disabled FPL fault---not supposed to happen!");
 		break;
 
 	      case 26: /* NaT Consumption */
-		if (user_mode(regs)) {
+		if (user_mode(&regs)) {
 			void __user *addr;
 
 			if (((isr >> 4) & 0xf) == 2) {
@@ -456,7 +456,8 @@
 				/* register NaT consumption */
 				sig = SIGILL;
 				code = ILL_ILLOPN;
-				addr = (void __user *) (regs->cr_iip + ia64_psr(regs)->ri);
+				addr = (void __user *) (regs.cr_iip
+							+ ia64_psr(&regs)->ri);
 			}
 			siginfo.si_signo = sig;
 			siginfo.si_code = code;
@@ -467,17 +468,17 @@
 			siginfo.si_isr = isr;
 			force_sig_info(sig, &siginfo, current);
 			return;
-		} else if (ia64_done_with_exception(regs))
+		} else if (ia64_done_with_exception(&regs))
 			return;
 		sprintf(buf, "NaT consumption");
 		break;
 
 	      case 31: /* Unsupported Data Reference */
-		if (user_mode(regs)) {
+		if (user_mode(&regs)) {
 			siginfo.si_signo = SIGILL;
 			siginfo.si_code = ILL_ILLOPN;
 			siginfo.si_errno = 0;
-			siginfo.si_addr = (void __user *) (regs->cr_iip + ia64_psr(regs)->ri);
+			siginfo.si_addr = (void __user *) iip;
 			siginfo.si_imm = vector;
 			siginfo.si_flags = __ISR_VALID;
 			siginfo.si_isr = isr;
@@ -490,7 +491,7 @@
 	      case 29: /* Debug */
 	      case 35: /* Taken Branch Trap */
 	      case 36: /* Single Step Trap */
-		if (fsys_mode(current, regs)) {
+		if (fsys_mode(current, &regs)) {
 			extern char __kernel_syscall_via_break[];
 			/*
 			 * Got a trap in fsys-mode: Taken Branch Trap and Single Step trap
@@ -498,13 +499,13 @@
 			 */
 			if (unlikely(vector == 29)) {
 				die("Got debug trap in fsys-mode---not supposed to happen!",
-				    regs, 0);
+				    &regs, 0);
 				return;
 			}
 			/* re-do the system call via break 0x100000: */
-			regs->cr_iip = (unsigned long) __kernel_syscall_via_break;
-			ia64_psr(regs)->ri = 0;
-			ia64_psr(regs)->cpl = 3;
+			regs.cr_iip = (unsigned long) __kernel_syscall_via_break;
+			ia64_psr(&regs)->ri = 0;
+			ia64_psr(&regs)->cpl = 3;
 			return;
 		}
 		switch (vector) {
@@ -515,8 +516,8 @@
 			 * Erratum 10 (IFA may contain incorrect address) now has
 			 * "NoFix" status.  There are no plans for fixing this.
 			 */
-			if (ia64_psr(regs)->is == 0)
-			  ifa = regs->cr_iip;
+			if (ia64_psr(&regs)->is == 0)
+			  ifa = regs.cr_iip;
 #endif
 			break;
 		      case 35: siginfo.si_code = TRAP_BRANCH; ifa = 0; break;
@@ -533,12 +534,12 @@
 
 	      case 32: /* fp fault */
 	      case 33: /* fp trap */
-		result = handle_fpu_swa((vector == 32) ? 1 : 0, regs, isr);
+		result = handle_fpu_swa((vector == 32) ? 1 : 0, &regs, isr);
 		if ((result < 0) || (current->thread.flags & IA64_THREAD_FPEMU_SIGFPE)) {
 			siginfo.si_signo = SIGFPE;
 			siginfo.si_errno = 0;
 			siginfo.si_code = FPE_FLTINV;
-			siginfo.si_addr = (void __user *) (regs->cr_iip + ia64_psr(regs)->ri);
+			siginfo.si_addr = (void __user *) iip;
 			siginfo.si_flags = __ISR_VALID;
 			siginfo.si_isr = isr;
 			siginfo.si_imm = 0;
@@ -554,19 +555,18 @@
 			 * interesting work (e.g., signal delivery is done in the kernel
 			 * exit path).
 			 */
-			ia64_psr(regs)->lp = 0;
+			ia64_psr(&regs)->lp = 0;
 			return;
 		} else {
 			/* Unimplemented Instr. Address Trap */
-			if (user_mode(regs)) {
+			if (user_mode(&regs)) {
 				siginfo.si_signo = SIGILL;
 				siginfo.si_code = ILL_BADIADDR;
 				siginfo.si_errno = 0;
 				siginfo.si_flags = 0;
 				siginfo.si_isr = 0;
 				siginfo.si_imm = 0;
-				siginfo.si_addr = (void __user *)
-					(regs->cr_iip + ia64_psr(regs)->ri);
+				siginfo.si_addr = (void __user *) iip;
 				force_sig_info(SIGILL, &siginfo, current);
 				return;
 			}
@@ -576,23 +576,23 @@
 
 	      case 45:
 #ifdef CONFIG_IA32_SUPPORT
-		if (ia32_exception(regs, isr) == 0)
+		if (ia32_exception(&regs, isr) == 0)
 			return;
 #endif
 		printk(KERN_ERR "Unexpected IA-32 exception (Trap 45)\n");
 		printk(KERN_ERR "  iip - 0x%lx, ifa - 0x%lx, isr - 0x%lx\n",
-		       regs->cr_iip, ifa, isr);
+		       iip, ifa, isr);
 		force_sig(SIGSEGV, current);
 		break;
 
 	      case 46:
 #ifdef CONFIG_IA32_SUPPORT
-		if (ia32_intercept(regs, isr) == 0)
+		if (ia32_intercept(&regs, isr) == 0)
 			return;
 #endif
 		printk(KERN_ERR "Unexpected IA-32 intercept trap (Trap 46)\n");
 		printk(KERN_ERR "  iip - 0x%lx, ifa - 0x%lx, isr - 0x%lx, iim - 0x%lx\n",
-		       regs->cr_iip, ifa, isr, iim);
+		       iip, ifa, isr, iim);
 		force_sig(SIGSEGV, current);
 		return;
 
@@ -604,6 +604,6 @@
 		sprintf(buf, "Fault %lu", vector);
 		break;
 	}
-	die_if_kernel(buf, regs, error);
+	die_if_kernel(buf, &regs, error);
 	force_sig(SIGILL, current);
 }
diff -Nru a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
--- a/arch/ia64/mm/contig.c	2005-01-18 15:21:57 -08:00
+++ b/arch/ia64/mm/contig.c	2005-02-02 12:21:57 -08:00
@@ -178,7 +178,7 @@
 void *
 per_cpu_init (void)
 {
-	void *cpu_data, *mca_data;
+	void *cpu_data;
 	int cpu;
 
 	/*
@@ -189,14 +189,11 @@
 	if (smp_processor_id() == 0) {
 		cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS,
 					   PERCPU_PAGE_SIZE, __pa(MAX_DMA_ADDRESS));
-		mca_data = alloc_bootmem(PERCPU_MCA_SIZE * NR_CPUS);
 		for (cpu = 0; cpu < NR_CPUS; cpu++) {
 			memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
 			__per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start;
 			cpu_data += PERCPU_PAGE_SIZE;
 			per_cpu(local_per_cpu_offset, cpu) = __per_cpu_offset[cpu];
-			__per_cpu_mca[cpu] = (unsigned long)__pa(mca_data);
-			mca_data += PERCPU_MCA_SIZE;
 		}
 	}
 	return __per_cpu_start + __per_cpu_offset[smp_processor_id()];
diff -Nru a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
--- a/arch/ia64/mm/discontig.c	2005-01-18 12:06:18 -08:00
+++ b/arch/ia64/mm/discontig.c	2005-02-02 12:22:02 -08:00
@@ -26,7 +26,6 @@
 #include <asm/meminit.h>
 #include <asm/numa.h>
 #include <asm/sections.h>
-#include <asm/mca.h>
 
 /*
  * Track per-node information needed to setup the boot memory allocator, the
@@ -294,9 +293,6 @@
  *   |------------------------|
  *   |  local ia64_node_data  |
  *   |------------------------|
- *   |    MCA/INIT data *     |
- *   |    cpus_on_this_node   |
- *   |------------------------|
  *   |          ???           |
  *   |________________________|
  *
@@ -310,7 +306,7 @@
 {
 	unsigned long epfn, cpu, cpus, phys_cpus;
 	unsigned long pernodesize = 0, pernode, pages, mapsize;
-	void *cpu_data, *mca_data_phys;
+	void *cpu_data;
 	struct bootmem_data *bdp = &mem_data[node].bootmem_data;
 
 	epfn = (start + len) >> PAGE_SHIFT;
@@ -339,7 +335,6 @@
 	pernodesize += node * L1_CACHE_BYTES;
 	pernodesize += L1_CACHE_ALIGN(sizeof(pg_data_t));
 	pernodesize += L1_CACHE_ALIGN(sizeof(struct ia64_node_data));
-	pernodesize += L1_CACHE_ALIGN(sizeof(ia64_mca_cpu_t)) * phys_cpus;
 	pernodesize = PAGE_ALIGN(pernodesize);
 	pernode = NODEDATA_ALIGN(start, node);
 
@@ -362,9 +357,6 @@
 		mem_data[node].pgdat->bdata = bdp;
 		pernode += L1_CACHE_ALIGN(sizeof(pg_data_t));
 
-		mca_data_phys = (void *)pernode;
-		pernode += L1_CACHE_ALIGN(sizeof(ia64_mca_cpu_t)) * phys_cpus;
-
 		/*
 		 * Copy the static per-cpu data into the region we
 		 * just set aside and then setup __per_cpu_offset
@@ -374,18 +366,6 @@
 			if (node == node_cpuid[cpu].nid) {
 				memcpy(__va(cpu_data), __phys_per_cpu_start,
 				       __per_cpu_end - __per_cpu_start);
-				if ((cpu == 0) || (node_cpuid[cpu].phys_id > 0)) {
-					/* 
-					 * The memory for the cpuinfo structure is allocated
-					 * here, but the data in the structure is initialized
-					 * later.  Save the physical address of the MCA save
-					 * area in __per_cpu_mca[cpu].  When the cpuinfo struct 
-					 * is initialized, the value in __per_cpu_mca[cpu]
-					 * will be put in the cpuinfo structure.
-					 */
-					__per_cpu_mca[cpu] = __pa(mca_data_phys);
-					mca_data_phys += L1_CACHE_ALIGN(sizeof(ia64_mca_cpu_t));
-				}
 				__per_cpu_offset[cpu] = (char*)__va(cpu_data) -
 					__per_cpu_start;
 				cpu_data += PERCPU_PAGE_SIZE;
diff -Nru a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
--- a/arch/ia64/mm/init.c	2005-01-18 12:06:18 -08:00
+++ b/arch/ia64/mm/init.c	2005-01-26 10:01:35 -08:00
@@ -40,7 +40,6 @@
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 
 extern void ia64_tlb_init (void);
-extern void efi_get_pal_addr (void);
 
 unsigned long MAX_DMA_ADDRESS = PAGE_OFFSET + 0x100000000UL;
 
@@ -290,27 +289,6 @@
 	put_kernel_page(page, GATE_ADDR + PERCPU_PAGE_SIZE, PAGE_GATE);
 #endif
 	ia64_patch_gate();
-}
-
-void
-set_mca_pointer(struct cpuinfo_ia64 *cpuinfo, void *cpu_data)
-{
-	void *my_cpu_data = ia64_imva(cpu_data);
-
-        /*
-         * The MCA info structure was allocated earlier and a physical address pointer
-         * saved in __per_cpu_mca[cpu].  Move that pointer into the cpuinfo structure.
-         */
-
-        cpuinfo->ia64_pa_mca_data = (__u64 *)__per_cpu_mca[smp_processor_id()];
-
-        cpuinfo->percpu_paddr = pte_val(mk_pte_phys(__pa(my_cpu_data), PAGE_KERNEL));
-        ia64_set_kr(IA64_KR_PA_CPU_INFO, __pa(cpuinfo));
-
-        /*
-         * Set pal_base and pal_paddr in cpuinfo structure.
-         */
-        efi_get_pal_addr();
 }
 
 void __devinit
diff -Nru a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
--- a/arch/ia64/pci/pci.c	2005-01-22 14:42:51 -08:00
+++ b/arch/ia64/pci/pci.c	2005-01-25 13:23:42 -08:00
@@ -71,7 +71,7 @@
 	u64 addr, mode, data = 0;
 	int result = 0;
 
-	if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 4095))
+	if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
 		return -EINVAL;
 
 	if ((seg | reg) <= 255) {
diff -Nru a/arch/ia64/sn/include/shubio.h b/arch/ia64/sn/include/shubio.h
--- a/arch/ia64/sn/include/shubio.h	2004-10-11 13:03:57 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,3476 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_SHUBIO_H
-#define _ASM_IA64_SN_SHUBIO_H
-
-#define HUB_WIDGET_ID_MAX 0xf
-#define IIO_NUM_ITTES   7
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
-
-#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
-                                                   /* This register is also accessible from
-                                                    * Crosstalk at address 0x0.  */
-#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
-#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
-#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
-#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
-#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
-#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
-#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
-#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
-#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
-#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
-
-#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
-#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
-
-#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
-#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
-
-#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
-#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
-#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
-#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
-#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
-#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
-#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
-
-#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
-#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
-#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
-#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
-#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
-#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
-#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
-#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
-#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
-
-#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
-#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
-#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
-#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
-#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
-
-#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
-#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
-
-#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
-
-#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
-#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
-
-
-#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
-#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
-
-#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
-#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
-#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
-#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
-#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
-
-#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
-
-#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
-#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
-#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
-#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
-#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
-#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
-#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
-#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
-
-#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
-#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
-#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
-#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
-#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
-#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
-#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
-#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
-
-#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
-#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
-#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
-#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
-#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
-#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
-#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
-#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
-
-#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
-#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
-#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
-#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
-#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
-
-#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
-#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
-#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
-#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
-#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
-
-#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
-#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
-#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
-#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
-#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
-
-#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
-#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
-#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
-#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
-#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
-
-#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
-#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
-#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
-#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
-#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
-
-#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
-#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
-#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
-#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
-#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
-
-#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
-#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
-#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
-#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
-#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
-
-#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
-#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
-#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
-#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
-#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
-
-#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
-#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
-#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
-#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
-#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
-
-#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
-#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
-#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
-#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
-#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
-
-#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
-#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
-#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
-#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
-#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
-
-#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
-#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
-#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
-#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
-#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
-
-#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
-#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
-#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
-#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
-#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
-
-#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
-#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
-#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
-#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
-#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
-
-#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
-#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
-#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
-#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
-#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
-
-#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
-#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
-#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
-
-#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
-
-#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
-#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
-#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
-#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
-#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
-#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
-#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
-#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
-#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
-#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
-#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
-#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
-
-#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
-#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register echoes some information from the         *
- * LB_REV_ID register. It is available through Crosstalk as described   *
- * above. The REV_NUM and MFG_NUM fields receive their values from      *
- * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
- * The PART_NUM field's value is the Crosstalk device ID number that    *
- * Steve Miller assigned to the SHub chip.                              *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_wid_u {
-	uint64_t	ii_wid_regval;
-	struct	{
-		uint64_t	w_rsvd_1		  :	 1;
-		uint64_t	w_mfg_num		  :	11;
-		uint64_t	w_part_num		  :	16;
-		uint64_t	w_rev_num		  :	 4;
-		uint64_t	w_rsvd			  :	32;
-	} ii_wid_fld_s;
-} ii_wid_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  The fields in this register are set upon detection of an error      *
- * and cleared by various mechanisms, as explained in the               *
- * description.                                                         *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_wstat_u {
-	uint64_t	ii_wstat_regval;
-	struct	{
-		uint64_t	w_pending		  :	 4;
-		uint64_t	w_xt_crd_to		  :	 1;
-		uint64_t	w_xt_tail_to		  :	 1;
-		uint64_t	w_rsvd_3		  :	 3;
-		uint64_t       w_tx_mx_rty               :      1;
-		uint64_t	w_rsvd_2		  :	 6;
-		uint64_t	w_llp_tx_cnt		  :	 8;
-		uint64_t	w_rsvd_1		  :	 8;
-		uint64_t	w_crazy			  :	 1;
-		uint64_t	w_rsvd			  :	31;
-	} ii_wstat_fld_s;
-} ii_wstat_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This is a read-write enabled register. It controls     *
- * various aspects of the Crosstalk flow control.                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_wcr_u {
-	uint64_t	ii_wcr_regval;
-	struct	{
-		uint64_t	w_wid			  :	 4;
-		uint64_t	w_tag			  :	 1;
-		uint64_t	w_rsvd_1		  :	 8;
-		uint64_t	w_dst_crd		  :	 3;
-		uint64_t	w_f_bad_pkt		  :	 1;
-		uint64_t	w_dir_con		  :	 1;
-		uint64_t	w_e_thresh		  :	 5;
-		uint64_t	w_rsvd			  :	41;
-	} ii_wcr_fld_s;
-} ii_wcr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register's value is a bit vector that guards      *
- * access to local registers within the II as well as to external       *
- * Crosstalk widgets. Each bit in the register corresponds to a         *
- * particular region in the system; a region consists of one, two or    *
- * four nodes (depending on the value of the REGION_SIZE field in the   *
- * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
- * protection provided by this register applies to PIO read             *
- * operations as well as PIO write operations. The II will perform a    *
- * PIO read or write request only if the bit for the requestor's        *
- * region is set; otherwise, the II will not perform the requested      *
- * operation and will return an error response. When a PIO read or      *
- * write request targets an external Crosstalk widget, then not only    *
- * must the bit for the requestor's region be set in the ILAPR, but     *
- * also the target widget's bit in the IOWA register must be set in     *
- * order for the II to perform the requested operation; otherwise,      *
- * the II will return an error response. Hence, the protection          *
- * provided by the IOWA register supplements the protection provided    *
- * by the ILAPR for requests that target external Crosstalk widgets.    *
- * This register itself can be accessed only by the nodes whose         *
- * region ID bits are enabled in this same register. It can also be     *
- * accessed through the IAlias space by the local processors.           *
- * The reset value of this register allows access by all nodes.         *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ilapr_u {
-	uint64_t	ii_ilapr_regval;
-	struct  {
-		uint64_t	i_region                  :	64;
-	} ii_ilapr_fld_s;
-} ii_ilapr_u_t;
-
-
-
-
-/************************************************************************
- *                                                                      *
- * Description:  A write to this register of the 64-bit value           *
- * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
- * corresponding to the region of the requestor to be set (allow        *
- * access). A write of any other value will be ignored. Access          *
- * protection for this register is "SGIrules".                          *
- * This register can also be accessed through the IAlias space.         *
- * However, this access will not change the access permissions in the   *
- * ILAPR.                                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ilapo_u {
-	uint64_t	ii_ilapo_regval;
-	struct	{
-		uint64_t	i_io_ovrride            :	64;
-	} ii_ilapo_fld_s;
-} ii_ilapo_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- *  This register qualifies all the PIO and Graphics writes launched    *
- * from the SHUB towards a widget.                                      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iowa_u {
-	uint64_t	ii_iowa_regval;
-	struct	{
-		uint64_t	i_w0_oac		  :	 1;
-		uint64_t	i_rsvd_1		  :	 7;
-                uint64_t       i_wx_oac                  :      8;
-		uint64_t	i_rsvd			  :	48;
-	} ii_iowa_fld_s;
-} ii_iowa_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register qualifies all the requests launched      *
- * from a widget towards the Shub. This register is intended to be      *
- * used by software in case of misbehaving widgets.                     *
- *                                                                      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iiwa_u {
-	uint64_t	ii_iiwa_regval;
-	struct  {
-		uint64_t	i_w0_iac                  :	 1;
-		uint64_t	i_rsvd_1		  :	 7;
-		uint64_t	i_wx_iac		  :	 8;
-		uint64_t	i_rsvd			  :	48;
-	} ii_iiwa_fld_s;
-} ii_iiwa_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register qualifies all the operations launched    *
- * from a widget towards the SHub. It allows individual access          *
- * control for up to 8 devices per widget. A device refers to           *
- * individual DMA master hosted by a widget.                            *
- * The bits in each field of this register are cleared by the Shub      *
- * upon detection of an error which requires the device to be           *
- * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
- * Crosstalk). Whether or not a device has access rights to this        *
- * Shub is determined by an AND of the device enable bit in the         *
- * appropriate field of this register and the corresponding bit in      *
- * the Wx_IAC field (for the widget which this device belongs to).      *
- * The bits in this field are set by writing a 1 to them. Incoming      *
- * replies from Crosstalk are not subject to this access control        *
- * mechanism.                                                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iidem_u {
-	uint64_t	ii_iidem_regval;
-	struct	{
-		uint64_t	i_w8_dxs		  :	 8;
-		uint64_t	i_w9_dxs		  :	 8;
-		uint64_t	i_wa_dxs		  :	 8;
-		uint64_t	i_wb_dxs		  :	 8;
-		uint64_t	i_wc_dxs		  :	 8;
-		uint64_t	i_wd_dxs		  :	 8;
-		uint64_t	i_we_dxs		  :	 8;
-		uint64_t	i_wf_dxs		  :	 8;
-	} ii_iidem_fld_s;
-} ii_iidem_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the various programmable fields necessary    *
- * for controlling and observing the LLP signals.                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ilcsr_u {
-	uint64_t	ii_ilcsr_regval;
-	struct  {
-		uint64_t	i_nullto                  :	 6;
-		uint64_t	i_rsvd_4		  :	 2;
-		uint64_t	i_wrmrst		  :	 1;
-		uint64_t	i_rsvd_3		  :	 1;
-		uint64_t	i_llp_en		  :	 1;
-		uint64_t	i_bm8			  :	 1;
-		uint64_t	i_llp_stat		  :	 2;
-		uint64_t	i_remote_power		  :	 1;
-		uint64_t	i_rsvd_2		  :	 1;
-		uint64_t	i_maxrtry		  :	10;
-		uint64_t	i_d_avail_sel		  :	 2;
-		uint64_t	i_rsvd_1		  :	 4;
-		uint64_t	i_maxbrst		  :	10;
-                uint64_t       i_rsvd                    :     22;
-
-	} ii_ilcsr_fld_s;
-} ii_ilcsr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This is simply a status registers that monitors the LLP error       *
- * rate.                                                                *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_illr_u {
-	uint64_t	ii_illr_regval;
-	struct	{
-		uint64_t	i_sn_cnt		  :	16;
-		uint64_t	i_cb_cnt		  :	16;
-		uint64_t	i_rsvd			  :	32;
-	} ii_illr_fld_s;
-} ii_illr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  All II-detected non-BTE error interrupts are           *
- * specified via this register.                                         *
- * NOTE: The PI interrupt register address is hardcoded in the II. If   *
- * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
- * packet) to address offset 0x0180_0090 within the local register      *
- * address space of PI0 on the node specified by the NODE field. If     *
- * PI_ID==1, then the II sends the interrupt request to address         *
- * offset 0x01A0_0090 within the local register address space of PI1    *
- * on the node specified by the NODE field.                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iidsr_u {
-	uint64_t	ii_iidsr_regval;
-	struct  {
-		uint64_t	i_level                   :	 8;
-		uint64_t	i_pi_id			  :	 1;
-		uint64_t	i_node			  :	11;
-		uint64_t       i_rsvd_3                  :      4;
-		uint64_t	i_enable		  :	 1;
-		uint64_t	i_rsvd_2		  :	 3;
-		uint64_t	i_int_sent		  :	 2;
-		uint64_t       i_rsvd_1                  :      2;
-		uint64_t	i_pi0_forward_int	  :	 1;
-		uint64_t	i_pi1_forward_int	  :	 1;
-		uint64_t	i_rsvd			  :	30;
-	} ii_iidsr_fld_s;
-} ii_iidsr_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- *  There are two instances of this register. This register is used     *
- * for matching up the incoming responses from the graphics widget to   *
- * the processor that initiated the graphics operation. The             *
- * write-responses are converted to graphics credits and returned to    *
- * the processor so that the processor interface can manage the flow    *
- * control.                                                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_igfx0_u {
-	uint64_t	ii_igfx0_regval;
-	struct	{
-		uint64_t	i_w_num			  :	 4;
-		uint64_t       i_pi_id                   :      1;
-		uint64_t	i_n_num			  :	12;
-		uint64_t       i_p_num                   :      1;
-		uint64_t       i_rsvd                    :     46;
-	} ii_igfx0_fld_s;
-} ii_igfx0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are two instances of this register. This register is used     *
- * for matching up the incoming responses from the graphics widget to   *
- * the processor that initiated the graphics operation. The             *
- * write-responses are converted to graphics credits and returned to    *
- * the processor so that the processor interface can manage the flow    *
- * control.                                                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_igfx1_u {
-	uint64_t	ii_igfx1_regval;
-	struct  {
-		uint64_t	i_w_num			  :	 4;
-		uint64_t       i_pi_id                   :      1;
-		uint64_t	i_n_num			  :	12;
-		uint64_t       i_p_num                   :      1;
-		uint64_t       i_rsvd                    :     46;
-	} ii_igfx1_fld_s;
-} ii_igfx1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are two instances of this registers. These registers are      *
- * used as scratch registers for software use.                          *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iscr0_u {
-	uint64_t	ii_iscr0_regval;
-	struct  {
-		uint64_t	i_scratch                 :	64;
-	} ii_iscr0_fld_s;
-} ii_iscr0_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- *  There are two instances of this registers. These registers are      *
- * used as scratch registers for software use.                          *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iscr1_u {
-	uint64_t	ii_iscr1_regval;
-	struct  {
-		uint64_t	i_scratch                 :	64;
-	} ii_iscr1_fld_s;
-} ii_iscr1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the SHub is thus the lower 16 GBytes per widget       * 
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte1_u {
-	uint64_t	ii_itte1_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_w_num			  :	 4;
-		uint64_t	i_iosp			  :	 1;
-		uint64_t	i_rsvd			  :	51;
-	} ii_itte1_fld_s;
-} ii_itte1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte2_u {
-	uint64_t	ii_itte2_regval;
-	struct	{
-		uint64_t	i_offset		  :	 5;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_w_num			  :	 4;
-		uint64_t	i_iosp			  :	 1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte2_fld_s;
-} ii_itte2_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte3_u {
-	uint64_t	ii_itte3_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t       i_rsvd_1                  :      3;
-		uint64_t       i_w_num                   :      4;
-		uint64_t       i_iosp                    :      1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte3_fld_s;
-} ii_itte3_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a SHub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the SHub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte4_u {
-	uint64_t	ii_itte4_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t       i_w_num                   :      4;
-		uint64_t       i_iosp                    :      1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte4_fld_s;
-} ii_itte4_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a SHub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte5_u {
-	uint64_t	ii_itte5_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t       i_rsvd_1                  :      3;
-		uint64_t       i_w_num                   :      4;
-		uint64_t       i_iosp                    :      1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte5_fld_s;
-} ii_itte5_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte6_u {
-	uint64_t	ii_itte6_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t       i_rsvd_1                  :      3;
-		uint64_t       i_w_num                   :      4;
-		uint64_t       i_iosp                    :      1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte6_fld_s;
-} ii_itte6_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_itte7_u {
-	uint64_t	ii_itte7_regval;
-	struct  {
-		uint64_t	i_offset                  :	 5;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t       i_w_num                   :      4;
-		uint64_t       i_iosp                    :      1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_itte7_fld_s;
-} ii_itte7_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprb0_u {
-	uint64_t	ii_iprb0_regval;
-	struct  {
-		uint64_t	i_c                       :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t       i_rsvd_2                  :      2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprb0_fld_s;
-} ii_iprb0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprb8_u {
-	uint64_t	ii_iprb8_regval;
-	struct  {
-		uint64_t	i_c                       :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t       i_rsvd_2                  :      2;
-		uint64_t	i_nb			  :	14;
-		uint64_t       i_rsvd_1                  :      2;
-		uint64_t       i_m                       :      2;
-		uint64_t       i_f                       :      1;
-		uint64_t       i_of_cnt                  :      5;
-		uint64_t       i_error                   :      1;
-		uint64_t       i_rd_to                   :      1;
-		uint64_t       i_spur_wr                 :      1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t       i_rsvd                    :     11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprb8_fld_s;
-} ii_iprb8_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprb9_u {
-	uint64_t	ii_iprb9_regval;
-	struct	{
-		uint64_t	i_c			  :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprb9_fld_s;
-} ii_iprb9_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.        *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- *                                                                      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprba_u {
-	uint64_t	ii_iprba_regval;
-	struct  {
-		uint64_t	i_c                       :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t       i_rsvd_2                  :      2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprba_fld_s;
-} ii_iprba_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprbb_u {
-	uint64_t	ii_iprbb_regval;
-	struct	{
-		uint64_t	i_c			  :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprbb_fld_s;
-} ii_iprbb_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprbc_u {
-	uint64_t	ii_iprbc_regval;
-	struct	{
-		uint64_t	i_c			  :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprbc_fld_s;
-} ii_iprbc_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprbd_u {
-	uint64_t	ii_iprbd_regval;
-	struct	{
-		uint64_t	i_c			  :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprbd_fld_s;
-} ii_iprbd_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprbe_u {
-	uint64_t	ii_iprbe_regval;
-	struct	{
-		uint64_t	i_c			  :	 8;
-		uint64_t	i_na			  :	14;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_nb			  :	14;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_m			  :	 2;
-		uint64_t	i_f			  :	 1;
-		uint64_t	i_of_cnt		  :	 5;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rd_to			  :	 1;
-		uint64_t	i_spur_wr		  :	 1;
-		uint64_t	i_spur_rd		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-		uint64_t	i_mult_err		  :	 1;
-	} ii_iprbe_fld_s;
-} ii_iprbe_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of Shub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .                                                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprbf_u {
-        uint64_t       ii_iprbf_regval;
-        struct  {
-                uint64_t       i_c                       :      8;
-                uint64_t       i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t       i_nb                      :     14;
-                uint64_t       i_rsvd_1                  :      2;
-                uint64_t       i_m                       :      2;
-                uint64_t       i_f                       :      1;
-                uint64_t       i_of_cnt                  :      5;
-                uint64_t       i_error                   :      1;
-                uint64_t       i_rd_to                   :      1;
-                uint64_t       i_spur_wr                 :      1;
-                uint64_t       i_spur_rd                 :      1;
-                uint64_t       i_rsvd                    :     11;
-                uint64_t       i_mult_err                :      1;
-        } ii_iprbe_fld_s;
-} ii_iprbf_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register specifies the timeout value to use for monitoring     *
- * Crosstalk credits which are used outbound to Crosstalk. An           *
- * internal counter called the Crosstalk Credit Timeout Counter         *
- * increments every 128 II clocks. The counter starts counting          *
- * anytime the credit count drops below a threshold, and resets to      *
- * zero (stops counting) anytime the credit count is at or above the    *
- * threshold. The threshold is 1 credit in direct connect mode and 2    *
- * in Crossbow connect mode. When the internal Crosstalk Credit         *
- * Timeout Counter reaches the value programmed in this register, a     *
- * Crosstalk Credit Timeout has occurred. The internal counter is not   *
- * readable from software, and stops counting at its maximum value,     *
- * so it cannot cause more than one interrupt.                          *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ixcc_u {
-	uint64_t	ii_ixcc_regval;
-	struct  {
-		uint64_t	i_time_out                :	26;
-		uint64_t	i_rsvd			  :	38;
-	} ii_ixcc_fld_s;
-} ii_ixcc_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register qualifies all the PIO and DMA            *
- * operations launched from widget 0 towards the SHub. In               *
- * addition, it also qualifies accesses by the BTE streams.             *
- * The bits in each field of this register are cleared by the SHub      *
- * upon detection of an error which requires widget 0 or the BTE        *
- * streams to be terminated. Whether or not widget x has access         *
- * rights to this SHub is determined by an AND of the device            *
- * enable bit in the appropriate field of this register and bit 0 in    *
- * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
- * them. Incoming replies from Crosstalk are not subject to this        *
- * access control mechanism.                                            *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_imem_u {
-	uint64_t	ii_imem_regval;
-	struct  {
-		uint64_t	i_w0_esd                  :	 1;
-		uint64_t	i_rsvd_3		  :	 3;
-		uint64_t	i_b0_esd		  :	 1;
-		uint64_t	i_rsvd_2		  :	 3;
-		uint64_t	i_b1_esd		  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_clr_precise		  :	 1;
-		uint64_t       i_rsvd                    :     51;
-	} ii_imem_fld_s;
-} ii_imem_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register specifies the timeout value to use for   *
- * monitoring Crosstalk tail flits coming into the Shub in the          *
- * TAIL_TO field. An internal counter associated with this register     *
- * is incremented every 128 II internal clocks (7 bits). The counter    *
- * starts counting anytime a header micropacket is received and stops   *
- * counting (and resets to zero) any time a micropacket with a Tail     *
- * bit is received. Once the counter reaches the threshold value        *
- * programmed in this register, it generates an interrupt to the        *
- * processor that is programmed into the IIDSR. The counter saturates   *
- * (does not roll over) at its maximum value, so it cannot cause        *
- * another interrupt until after it is cleared.                         *
- * The register also contains the Read Response Timeout values. The     *
- * Prescalar is 23 bits, and counts II clocks. An internal counter      *
- * increments on every II clock and when it reaches the value in the    *
- * Prescalar field, all IPRTE registers with their valid bits set       *
- * have their Read Response timers bumped. Whenever any of them match   *
- * the value in the RRSP_TO field, a Read Response Timeout has          *
- * occurred, and error handling occurs as described in the Error        *
- * Handling section of this document.                                   *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ixtt_u {
-	uint64_t	ii_ixtt_regval;
-	struct  {
-		uint64_t	i_tail_to                 :	26;
-		uint64_t	i_rsvd_1		  :	 6;
-		uint64_t	i_rrsp_ps		  :	23;
-		uint64_t	i_rrsp_to		  :	 5;
-		uint64_t	i_rsvd			  :	 4;
-	} ii_ixtt_fld_s;
-} ii_ixtt_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  Writing a 1 to the fields of this register clears the appropriate   *
- * error bits in other areas of SHub. Note that when the                *
- * E_PRB_x bits are used to clear error bits in PRB registers,          *
- * SPUR_RD and SPUR_WR may persist, because they require additional     *
- * action to clear them. See the IPRBx and IXSS Register                *
- * specifications.                                                      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ieclr_u {
-	uint64_t	ii_ieclr_regval;
-	struct  {
-		uint64_t	i_e_prb_0                 :	 1;
-		uint64_t	i_rsvd			  :	 7;
-		uint64_t	i_e_prb_8		  :	 1;
-		uint64_t	i_e_prb_9		  :	 1;
-		uint64_t	i_e_prb_a		  :	 1;
-		uint64_t	i_e_prb_b		  :	 1;
-		uint64_t	i_e_prb_c		  :	 1;
-		uint64_t	i_e_prb_d		  :	 1;
-		uint64_t	i_e_prb_e		  :	 1;
-		uint64_t	i_e_prb_f		  :	 1;
-		uint64_t	i_e_crazy		  :	 1;
-		uint64_t	i_e_bte_0		  :	 1;
-		uint64_t	i_e_bte_1		  :	 1;
-		uint64_t	i_reserved_1		  :	10;
-		uint64_t	i_spur_rd_hdr		  :	 1;
-		uint64_t	i_cam_intr_to		  :	 1;
-		uint64_t	i_cam_overflow		  :	 1;
-		uint64_t	i_cam_read_miss		  :	 1;
-		uint64_t	i_ioq_rep_underflow	  :	 1;
-		uint64_t	i_ioq_req_underflow	  :	 1;
-		uint64_t	i_ioq_rep_overflow	  :	 1;
-		uint64_t	i_ioq_req_overflow	  :	 1;
-		uint64_t	i_iiq_rep_overflow	  :	 1;
-		uint64_t	i_iiq_req_overflow	  :	 1;
-		uint64_t	i_ii_xn_rep_cred_overflow :	 1;
-		uint64_t	i_ii_xn_req_cred_overflow :	 1;
-		uint64_t	i_ii_xn_invalid_cmd	  :	 1;
-		uint64_t	i_xn_ii_invalid_cmd	  :	 1;
-		uint64_t	i_reserved_2		  :	21;
-	} ii_ieclr_fld_s;
-} ii_ieclr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register controls both BTEs. SOFT_RESET is intended for        *
- * recovery after an error. COUNT controls the total number of CRBs     *
- * that both BTEs (combined) can use, which affects total BTE           *
- * bandwidth.                                                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibcr_u {
-	uint64_t	ii_ibcr_regval;
-	struct  {
-		uint64_t	i_count                   :	 4;
-		uint64_t	i_rsvd_1		  :	 4;
-		uint64_t	i_soft_reset		  :	 1;
-		uint64_t	i_rsvd			  :	55;
-	} ii_ibcr_fld_s;
-} ii_ibcr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the header of a spurious read response       *
- * received from Crosstalk. A spurious read response is defined as a    *
- * read response received by II from a widget for which (1) the SIDN    *
- * has a value between 1 and 7, inclusive (II never sends requests to   *
- * these widgets (2) there is no valid IPRTE register which             *
- * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
- * not the same as the widget recorded in the IPRTE register            *
- * referenced by the TNUM. If this condition is true, and if the        *
- * IXSS[VALID] bit is clear, then the header of the spurious read       *
- * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
- * errant header is thereby captured, and no further spurious read      *
- * respones are captured until IXSS[VALID] is cleared by setting the    *
- * appropriate bit in IECLR.Everytime a spurious read response is       *
- * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
- * message's SIDN field is set. This always happens, regarless of       *
- * whether a header is captured. The programmer should check            *
- * IXSM[SIDN] to determine which widget sent the spurious response,     *
- * because there may be more than one SPUR_RD bit set in the PRB        *
- * registers. The widget indicated by IXSM[SIDN] was the first          *
- * spurious read response to be received since the last time            *
- * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
- * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
- * spurious messages from other widets which were detected after the    *
- * header was captured..                                                *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ixsm_u {
-	uint64_t	ii_ixsm_regval;
-	struct  {
-		uint64_t	i_byte_en                 :	32;
-		uint64_t	i_reserved		  :	 1;
-		uint64_t	i_tag			  :	 3;
-		uint64_t	i_alt_pactyp		  :	 4;
-		uint64_t	i_bo			  :	 1;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_vbpm			  :	 1;
-		uint64_t	i_gbr			  :	 1;
-		uint64_t	i_ds			  :	 2;
-		uint64_t	i_ct			  :	 1;
-		uint64_t	i_tnum			  :	 5;
-		uint64_t	i_pactyp		  :	 4;
-		uint64_t	i_sidn			  :	 4;
-		uint64_t	i_didn			  :	 4;
-	} ii_ixsm_fld_s;
-} ii_ixsm_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the sideband bits of a spurious read         *
- * response received from Crosstalk.                                    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ixss_u {
-	uint64_t	ii_ixss_regval;
-	struct  {
-		uint64_t	i_sideband                :	 8;
-		uint64_t	i_rsvd			  :	55;
-		uint64_t	i_valid			  :	 1;
-	} ii_ixss_fld_s;
-} ii_ixss_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register enables software to access the II LLP's test port.    *
- * Refer to the LLP 2.5 documentation for an explanation of the test    *
- * port. Software can write to this register to program the values      *
- * for the control fields (TestErrCapture, TestClear, TestFlit,         *
- * TestMask and TestSeed). Similarly, software can read from this       *
- * register to obtain the values of the test port's status outputs      *
- * (TestCBerr, TestValid and TestData).                                 *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ilct_u {
-	uint64_t	ii_ilct_regval;
-	struct  {
-		uint64_t	i_test_seed               :	20;
-		uint64_t	i_test_mask               :	 8;
-		uint64_t	i_test_data               :	20;
-		uint64_t	i_test_valid              :	 1;
-		uint64_t	i_test_cberr              :	 1;
-		uint64_t	i_test_flit               :	 3;
-		uint64_t	i_test_clear              :	 1;
-		uint64_t	i_test_err_capture        :	 1;
-		uint64_t	i_rsvd                    :	 9;
-	} ii_ilct_fld_s;
-} ii_ilct_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  If the II detects an illegal incoming Duplonet packet (request or   *
- * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
- * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
- * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
- * and assigns a value to the ERR_TYPE field which indicates the        *
- * specific nature of the error. The II recognizes four different       *
- * types of errors: short request packets (ERR_TYPE==2), short reply    *
- * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
- * reply packets (ERR_TYPE==5). The encodings for these types of        *
- * errors were chosen to be consistent with the same types of errors    *
- * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
- * the LB unit). If the II detects an illegal incoming Duplonet         *
- * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
- * the OVERRUN bit to indicate that a subsequent error has happened,    *
- * and does nothing further.                                            *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iieph1_u {
-	uint64_t	ii_iieph1_regval;
-	struct	{
-		uint64_t	i_command		  :	 7;
-		uint64_t	i_rsvd_5		  :	 1;
-		uint64_t	i_suppl			  :	14;
-		uint64_t	i_rsvd_4		  :	 1;
-		uint64_t	i_source		  :	14;
-		uint64_t	i_rsvd_3		  :	 1;
-		uint64_t	i_err_type		  :	 4;
-		uint64_t	i_rsvd_2		  :	 4;
-		uint64_t	i_overrun		  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_valid			  :	 1;
-		uint64_t	i_rsvd			  :	13;
-	} ii_iieph1_fld_s;
-} ii_iieph1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register holds the Address field from the header flit of an    *
- * incoming erroneous Duplonet packet, along with the tail bit which    *
- * accompanied this header flit. This register is essentially an        *
- * extension of IIEPH1. Two registers were necessary because the 64     *
- * bits available in only a single register were insufficient to        *
- * capture the entire header flit of an erroneous packet.               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iieph2_u {
-	uint64_t	ii_iieph2_regval;
-	struct  {
-		uint64_t	i_rsvd_0		  :	 3;
-		uint64_t	i_address                 :	47;
-		uint64_t	i_rsvd_1		  :	10;
-		uint64_t	i_tail			  :	 1;
-		uint64_t	i_rsvd			  :	 3;
-	} ii_iieph2_fld_s;
-} ii_iieph2_u_t;
-
-
-/******************************/
-
-
-
-/************************************************************************
- *                                                                      *
- *  This register's value is a bit vector that guards access from SXBs  *
- * to local registers within the II as well as to external Crosstalk    *
- * widgets								*
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_islapr_u {
-	uint64_t	ii_islapr_regval;
-	struct  {
-		uint64_t	i_region		  :	64;
-	} ii_islapr_fld_s;
-} ii_islapr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  A write to this register of the 56-bit value "Pup+Bun" will cause	*
- * the bit in the ISLAPR register corresponding to the region of the	*
- * requestor to be set (access allowed).				(
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_islapo_u {
-	uint64_t	ii_islapo_regval;
-	struct  {
-		uint64_t	i_io_sbx_ovrride	  :	56;
-		uint64_t	i_rsvd			  :	 8;
-	} ii_islapo_fld_s;
-} ii_islapo_u_t;
-
-/************************************************************************
- *                                                                      *
- *  Determines how long the wrapper will wait aftr an interrupt is	*
- * initially issued from the II before it times out the outstanding	*
- * interrupt and drops it from the interrupt queue.			* 
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iwi_u {
-	uint64_t	ii_iwi_regval;
-	struct  {
-		uint64_t	i_prescale		  :	24;
-		uint64_t	i_rsvd			  :	 8;
-		uint64_t	i_timeout		  :	 8;
-		uint64_t	i_rsvd1			  :	 8;
-		uint64_t	i_intrpt_retry_period	  :	 8;
-		uint64_t	i_rsvd2			  :	 8;
-	} ii_iwi_fld_s;
-} ii_iwi_u_t;
-
-/************************************************************************
- *                                                                      *
- *  Log errors which have occurred in the II wrapper. The errors are	*
- * cleared by writing to the IECLR register.				* 
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iwel_u {
-	uint64_t	ii_iwel_regval;
-	struct  {
-		uint64_t	i_intr_timed_out	  :	 1;
-		uint64_t	i_rsvd			  :	 7;
-		uint64_t	i_cam_overflow		  :	 1;
-		uint64_t	i_cam_read_miss		  :	 1;
-		uint64_t	i_rsvd1			  :	 2;
-		uint64_t	i_ioq_rep_underflow	  :	 1;
-		uint64_t	i_ioq_req_underflow	  :	 1;
-		uint64_t	i_ioq_rep_overflow	  :	 1;
-		uint64_t	i_ioq_req_overflow	  :	 1;
-		uint64_t	i_iiq_rep_overflow	  :	 1;
-		uint64_t	i_iiq_req_overflow	  :	 1;
-		uint64_t	i_rsvd2			  :	 6;
-		uint64_t	i_ii_xn_rep_cred_over_under:	 1;
-		uint64_t	i_ii_xn_req_cred_over_under:	 1;
-		uint64_t	i_rsvd3			  :	 6;
-		uint64_t	i_ii_xn_invalid_cmd	  :	 1;
-		uint64_t	i_xn_ii_invalid_cmd	  :	 1;
-		uint64_t	i_rsvd4			  :	30;
-	} ii_iwel_fld_s;
-} ii_iwel_u_t;
-
-/************************************************************************
- *                                                                      *
- *  Controls the II wrapper.						* 
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iwc_u {
-	uint64_t	ii_iwc_regval;
-	struct  {
-		uint64_t	i_dma_byte_swap		  :	 1;
-		uint64_t	i_rsvd			  :	 3;
-		uint64_t	i_cam_read_lines_reset	  :	 1;
-		uint64_t	i_rsvd1			  :	 3;
-		uint64_t	i_ii_xn_cred_over_under_log:	 1;
-		uint64_t	i_rsvd2			  :	19;
-		uint64_t	i_xn_rep_iq_depth	  :	 5;
-		uint64_t	i_rsvd3			  :	 3;
-		uint64_t	i_xn_req_iq_depth	  :	 5;
-		uint64_t	i_rsvd4			  :	 3;
-		uint64_t	i_iiq_depth		  :	 6;
-		uint64_t	i_rsvd5			  :	12;
-		uint64_t	i_force_rep_cred	  :	 1;
-		uint64_t	i_force_req_cred	  :	 1;
-	} ii_iwc_fld_s;
-} ii_iwc_u_t;
-
-/************************************************************************
- *                                                                      *
- *  Status in the II wrapper.						* 
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iws_u {
-	uint64_t	ii_iws_regval;
-	struct  {
-		uint64_t	i_xn_rep_iq_credits	  :	 5;
-		uint64_t	i_rsvd			  :	 3;
-		uint64_t	i_xn_req_iq_credits	  :	 5;
-		uint64_t	i_rsvd1			  :	51;
-	} ii_iws_fld_s;
-} ii_iws_u_t;
-
-/************************************************************************
- *                                                                      *
- *  Masks errors in the IWEL register.					*
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iweim_u {
-	uint64_t	ii_iweim_regval;
-	struct  {
-		uint64_t	i_intr_timed_out	  :	 1;
-		uint64_t	i_rsvd			  :	 7;
-		uint64_t	i_cam_overflow		  :	 1;
-		uint64_t	i_cam_read_miss		  :	 1;
-		uint64_t	i_rsvd1			  :	 2;
-		uint64_t	i_ioq_rep_underflow	  :	 1;
-		uint64_t	i_ioq_req_underflow	  :	 1;
-		uint64_t	i_ioq_rep_overflow	  :	 1;
-		uint64_t	i_ioq_req_overflow	  :	 1;
-		uint64_t	i_iiq_rep_overflow	  :	 1;
-		uint64_t	i_iiq_req_overflow	  :	 1;
-		uint64_t	i_rsvd2			  :	 6;
-		uint64_t	i_ii_xn_rep_cred_overflow :	 1;
-		uint64_t	i_ii_xn_req_cred_overflow :	 1;
-		uint64_t	i_rsvd3			  :	 6;
-		uint64_t	i_ii_xn_invalid_cmd	  :	 1;
-		uint64_t	i_xn_ii_invalid_cmd	  :	 1;
-		uint64_t	i_rsvd4			  :	30;
-	} ii_iweim_fld_s;
-} ii_iweim_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  A write to this register causes a particular field in the           *
- * corresponding widget's PRB entry to be adjusted up or down by 1.     *
- * This counter should be used when recovering from error and reset     *
- * conditions. Note that software would be capable of causing           *
- * inadvertent overflow or underflow of these counters.                 *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ipca_u {
-	uint64_t	ii_ipca_regval;
-	struct  {
-		uint64_t	i_wid                     :	 4;
-		uint64_t	i_adjust		  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_field			  :	 2;
-		uint64_t	i_rsvd			  :	54;
-	} ii_ipca_fld_s;
-} ii_ipca_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-
-typedef union ii_iprte0a_u {
-	uint64_t	ii_iprte0a_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t       i_vld                     :      1;
-	} ii_iprte0a_fld_s;
-} ii_iprte0a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte1a_u {
-	uint64_t	ii_iprte1a_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t       i_vld                     :      1;
-	} ii_iprte1a_fld_s;
-} ii_iprte1a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte2a_u {
-	uint64_t	ii_iprte2a_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t       i_vld                     :      1;
-	} ii_iprte2a_fld_s;
-} ii_iprte2a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte3a_u {
-	uint64_t	ii_iprte3a_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t	i_vld			  :	 1;
-	} ii_iprte3a_fld_s;
-} ii_iprte3a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte4a_u {
-	uint64_t	ii_iprte4a_regval;
-	struct	{
-		uint64_t	i_rsvd_1		  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t	i_vld			  :	 1;
-	} ii_iprte4a_fld_s;
-} ii_iprte4a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte5a_u {
-	uint64_t	ii_iprte5a_regval;
-	struct	{
-		uint64_t	i_rsvd_1		  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t	i_vld			  :	 1;
-	} ii_iprte5a_fld_s;
-} ii_iprte5a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte6a_u {
-	uint64_t	ii_iprte6a_regval;
-	struct	{
-		uint64_t	i_rsvd_1		  :	54;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t	i_vld			  :	 1;
-	} ii_iprte6a_fld_s;
-} ii_iprte6a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte7a_u {
-        uint64_t       ii_iprte7a_regval;
-        struct  {
-                uint64_t       i_rsvd_1                  :     54;
-                uint64_t       i_widget                  :      4;
-                uint64_t       i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
-        } ii_iprtea7_fld_s;
-} ii_iprte7a_u_t;
-
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-
-typedef union ii_iprte0b_u {
-	uint64_t	ii_iprte0b_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte0b_fld_s;
-} ii_iprte0b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte1b_u {
-	uint64_t	ii_iprte1b_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte1b_fld_s;
-} ii_iprte1b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte2b_u {
-	uint64_t	ii_iprte2b_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte2b_fld_s;
-} ii_iprte2b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte3b_u {
-	uint64_t	ii_iprte3b_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte3b_fld_s;
-} ii_iprte3b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte4b_u {
-	uint64_t	ii_iprte4b_regval;
-	struct	{
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte4b_fld_s;
-} ii_iprte4b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte5b_u {
-	uint64_t	ii_iprte5b_regval;
-	struct	{
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-	} ii_iprte5b_fld_s;
-} ii_iprte5b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte6b_u {
-	uint64_t	ii_iprte6b_regval;
-	struct	{
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-
-	} ii_iprte6b_fld_s;
-} ii_iprte6b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iprte7b_u {
-        uint64_t       ii_iprte7b_regval;
-        struct  {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_address		  :	47;
-		uint64_t	i_init			  :	 3;
-		uint64_t       i_source                  :     11;
-        } ii_iprte7b_fld_s;
-} ii_iprte7b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  SHub II contains a feature which did not exist in      *
- * the Hub which automatically cleans up after a Read Response          *
- * timeout, including deallocation of the IPRTE and recovery of IBuf    *
- * space. The inclusion of this register in SHub is for backward        *
- * compatibility                                                        *
- * A write to this register causes an entry from the table of           *
- * outstanding PIO Read Requests to be freed and returned to the        *
- * stack of free entries. This register is used in handling the         *
- * timeout errors that result in a PIO Reply never returning from       *
- * Crosstalk.                                                           *
- * Note that this register does not affect the contents of the IPRTE    *
- * registers. The Valid bits in those registers have to be              *
- * specifically turned off by software.                                 *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ipdr_u {
-	uint64_t	ii_ipdr_regval;
-	struct  {
-		uint64_t	i_te                      :	 3;
-		uint64_t	i_rsvd_1		  :	 1;
-		uint64_t	i_pnd			  :	 1;
-		uint64_t	i_init_rpcnt		  :	 1;
-		uint64_t	i_rsvd			  :	58;
-	} ii_ipdr_fld_s;
-} ii_ipdr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  A write to this register causes a CRB entry to be returned to the   *
- * queue of free CRBs. The entry should have previously been cleared    *
- * (mark bit) via backdoor access to the pertinent CRB entry. This      *
- * register is used in the last step of handling the errors that are    *
- * captured and marked in CRB entries.  Briefly: 1) first error for     *
- * DMA write from a particular device, and first error for a            *
- * particular BTE stream, lead to a marked CRB entry, and processor     *
- * interrupt, 2) software reads the error information captured in the   *
- * CRB entry, and presumably takes some corrective action, 3)           *
- * software clears the mark bit, and finally 4) software writes to      *
- * the ICDR register to return the CRB entry to the list of free CRB    *
- * entries.                                                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icdr_u {
-	uint64_t	ii_icdr_regval;
-	struct  {
-		uint64_t	i_crb_num                 :	 4;
-		uint64_t	i_pnd			  :	 1;
-		uint64_t       i_rsvd                    :     59;
-	} ii_icdr_fld_s;
-} ii_icdr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register provides debug access to two FIFOs inside of II.      *
- * Both IOQ_MAX* fields of this register contain the instantaneous      *
- * depth (in units of the number of available entries) of the           *
- * associated IOQ FIFO.  A read of this register will return the        *
- * number of free entries on each FIFO at the time of the read.  So     *
- * when a FIFO is idle, the associated field contains the maximum       *
- * depth of the FIFO.  This register is writable for debug reasons      *
- * and is intended to be written with the maximum desired FIFO depth    *
- * while the FIFO is idle. Software must assure that II is idle when    *
- * this register is written. If there are any active entries in any     *
- * of these FIFOs when this register is written, the results are        *
- * undefined.                                                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ifdr_u {
-	uint64_t	ii_ifdr_regval;
-	struct  {
-		uint64_t	i_ioq_max_rq              :	 7;
-		uint64_t	i_set_ioq_rq		  :	 1;
-		uint64_t	i_ioq_max_rp		  :	 7;
-		uint64_t	i_set_ioq_rp		  :	 1;
-		uint64_t	i_rsvd			  :	48;
-	} ii_ifdr_fld_s;
-} ii_ifdr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register allows the II to become sluggish in removing          *
- * messages from its inbound queue (IIQ). This will cause messages to   *
- * back up in either virtual channel. Disabling the "molasses" mode     *
- * subsequently allows the II to be tested under stress. In the         *
- * sluggish ("Molasses") mode, the localized effects of congestion      *
- * can be observed.                                                     *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iiap_u {
-        uint64_t       ii_iiap_regval;
-        struct  {
-                uint64_t       i_rq_mls                  :      6;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_rp_mls		  :	 6;
-		uint64_t       i_rsvd                    :     50;
-        } ii_iiap_fld_s;
-} ii_iiap_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register allows several parameters of CRB operation to be      *
- * set. Note that writing to this register can have catastrophic side   *
- * effects, if the CRB is not quiescent, i.e. if the CRB is             *
- * processing protocol messages when the write occurs.                  *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icmr_u {
-	uint64_t	ii_icmr_regval;
-	struct  {
-		uint64_t	i_sp_msg                  :	 1;
-		uint64_t	i_rd_hdr		  :	 1;
-		uint64_t	i_rsvd_4		  :	 2;
-		uint64_t	i_c_cnt			  :	 4;
-		uint64_t	i_rsvd_3		  :	 4;
-		uint64_t	i_clr_rqpd		  :	 1;
-		uint64_t	i_clr_rppd		  :	 1;
-		uint64_t	i_rsvd_2		  :	 2;
-		uint64_t	i_fc_cnt		  :	 4;
-		uint64_t	i_crb_vld		  :	15;
-		uint64_t	i_crb_mark		  :	15;
-		uint64_t	i_rsvd_1		  :	 2;
-		uint64_t	i_precise		  :	 1;
-		uint64_t	i_rsvd			  :	11;
-	} ii_icmr_fld_s;
-} ii_icmr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register allows control of the table portion of the CRB        *
- * logic via software. Control operations from this register have       *
- * priority over all incoming Crosstalk or BTE requests.                *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_iccr_u {
-	uint64_t	ii_iccr_regval;
-	struct  {
-		uint64_t	i_crb_num                 :	 4;
-		uint64_t	i_rsvd_1		  :	 4;
-		uint64_t	i_cmd			  :	 8;
-		uint64_t	i_pending		  :	 1;
-		uint64_t	i_rsvd			  :	47;
-	} ii_iccr_fld_s;
-} ii_iccr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register allows the maximum timeout value to be programmed.    *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icto_u {
-	uint64_t	ii_icto_regval;
-	struct  {
-		uint64_t	i_timeout                 :	 8;
-		uint64_t	i_rsvd			  :	56;
-	} ii_icto_fld_s;
-} ii_icto_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register allows the timeout prescalar to be programmed. An     *
- * internal counter is associated with this register. When the          *
- * internal counter reaches the value of the PRESCALE field, the        *
- * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
- * field). The internal counter resets to zero, and then continues      *
- * counting.                                                            *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ictp_u {
-	uint64_t	ii_ictp_regval;
-	struct  {
-		uint64_t	i_prescale                :	24;
-		uint64_t	i_rsvd			  :	40;
-	} ii_ictp_fld_s;
-} ii_ictp_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- * The CRB Entry registers can be conceptualized as rows and columns    *
- * (illustrated in the table above). Each row contains the 4            *
- * registers required for a single CRB Entry. The first doubleword      *
- * (column) for each entry is labeled A, and the second doubleword      *
- * (higher address) is labeled B, the third doubleword is labeled C,    *
- * the fourth doubleword is labeled D and the fifth doubleword is       *
- * labeled E. All CRB entries have their addresses on a quarter         *
- * cacheline aligned boundary.                   *
- * Upon reset, only the following fields are initialized: valid         *
- * (VLD), priority count, timeout, timeout valid, and context valid.    *
- * All other bits should be cleared by software before use (after       *
- * recovering any potential error state from before the reset).         *
- * The following four tables summarize the format for the four          *
- * registers that are used for each ICRB# Entry.                        *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icrb0_a_u {
-	uint64_t	ii_icrb0_a_regval;
-	struct  {
-		uint64_t	ia_iow                    :	 1;
-		uint64_t	ia_vld			  :	 1;
-		uint64_t	ia_addr			  :	47;
-		uint64_t	ia_tnum			  :	 5;
-		uint64_t	ia_sidn			  :	 4;
-		uint64_t       ia_rsvd                   :      6;
-	} ii_icrb0_a_fld_s;
-} ii_icrb0_a_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icrb0_b_u {
-	uint64_t	ii_icrb0_b_regval;
-	struct	{
-		uint64_t	ib_xt_err		  :	 1;
-		uint64_t	ib_mark			  :	 1;
-		uint64_t	ib_ln_uce		  :	 1;
-		uint64_t	ib_errcode		  :	 3;
-		uint64_t	ib_error		  :	 1;
-		uint64_t	ib_stall__bte_1		  :	 1;
-		uint64_t	ib_stall__bte_0		  :	 1;
-		uint64_t	ib_stall__intr		  :	 1;
-		uint64_t	ib_stall_ib		  :	 1;
-		uint64_t	ib_intvn		  :	 1;
-		uint64_t	ib_wb			  :	 1;
-		uint64_t	ib_hold			  :	 1;
-		uint64_t	ib_ack			  :	 1;
-		uint64_t	ib_resp			  :	 1;
-		uint64_t	ib_ack_cnt		  :	11;
-		uint64_t	ib_rsvd			  :	 7;
-		uint64_t	ib_exc			  :	 5;
-		uint64_t	ib_init			  :	 3;
-		uint64_t	ib_imsg			  :	 8;
-		uint64_t	ib_imsgtype		  :	 2;
-		uint64_t	ib_use_old		  :	 1;
-		uint64_t	ib_rsvd_1		  :	11;
-	} ii_icrb0_b_fld_s;
-} ii_icrb0_b_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icrb0_c_u {
-	uint64_t	ii_icrb0_c_regval;
-	struct	{
-		uint64_t	ic_source		  :	15;
-		uint64_t	ic_size			  :	 2;
-		uint64_t	ic_ct			  :	 1;
-		uint64_t	ic_bte_num		  :	 1;
-		uint64_t	ic_gbr			  :	 1;
-		uint64_t	ic_resprqd		  :	 1;
-		uint64_t	ic_bo			  :	 1;
-		uint64_t	ic_suppl		  :	15;
-		uint64_t	ic_rsvd			  :	27;
-	} ii_icrb0_c_fld_s;
-} ii_icrb0_c_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icrb0_d_u {
-	uint64_t	ii_icrb0_d_regval;
-	struct  {
-		uint64_t	id_pa_be                  :	43;
-		uint64_t	id_bte_op		  :	 1;
-		uint64_t	id_pr_psc		  :	 4;
-		uint64_t	id_pr_cnt		  :	 4;
-		uint64_t	id_sleep		  :	 1;
-		uint64_t	id_rsvd			  :	11;
-	} ii_icrb0_d_fld_s;
-} ii_icrb0_d_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icrb0_e_u {
-	uint64_t	ii_icrb0_e_regval;
-	struct  {
-		uint64_t	ie_timeout                :	 8;
-		uint64_t	ie_context		  :	15;
-		uint64_t	ie_rsvd			  :	 1;
-		uint64_t	ie_tvld			  :	 1;
-		uint64_t	ie_cvld			  :	 1;
-		uint64_t	ie_rsvd_0		  :	38;
-	} ii_icrb0_e_fld_s;
-} ii_icrb0_e_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the lower 64 bits of the header of the       *
- * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
- * register is set.                                                     *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icsml_u {
-	uint64_t	ii_icsml_regval;
-	struct  {
-		uint64_t	i_tt_addr                 :	47;
-		uint64_t	i_newsuppl_ex		  :	14;
-		uint64_t	i_reserved		  :	 2;
-		uint64_t       i_overflow                :      1;
-	} ii_icsml_fld_s;
-} ii_icsml_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the middle 64 bits of the header of the      *
- * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
- * register is set.                                                     *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icsmm_u {
-	uint64_t	ii_icsmm_regval;
-	struct  {
-		uint64_t	i_tt_ack_cnt              :	11;
-		uint64_t	i_reserved		  :	53;
-	} ii_icsmm_fld_s;
-} ii_icsmm_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the microscopic state, all the inputs to     *
- * the protocol table, captured with the spurious message. Valid when   *
- * the SP_MSG bit in the ICMR register is set.                          *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_icsmh_u {
-	uint64_t	ii_icsmh_regval;
-	struct  {
-		uint64_t	i_tt_vld                  :	 1;
-		uint64_t	i_xerr			  :	 1;
-		uint64_t	i_ft_cwact_o		  :	 1;
-		uint64_t	i_ft_wact_o		  :	 1;
-		uint64_t       i_ft_active_o             :      1;
-		uint64_t	i_sync			  :	 1;
-		uint64_t	i_mnusg			  :	 1;
-		uint64_t	i_mnusz			  :	 1;
-		uint64_t	i_plusz			  :	 1;
-		uint64_t	i_plusg			  :	 1;
-		uint64_t	i_tt_exc		  :	 5;
-		uint64_t	i_tt_wb			  :	 1;
-		uint64_t	i_tt_hold		  :	 1;
-		uint64_t	i_tt_ack		  :	 1;
-		uint64_t	i_tt_resp		  :	 1;
-		uint64_t	i_tt_intvn		  :	 1;
-		uint64_t	i_g_stall_bte1		  :	 1;
-		uint64_t	i_g_stall_bte0		  :	 1;
-		uint64_t	i_g_stall_il		  :	 1;
-		uint64_t	i_g_stall_ib		  :	 1;
-		uint64_t	i_tt_imsg		  :	 8;
-		uint64_t	i_tt_imsgtype		  :	 2;
-		uint64_t	i_tt_use_old		  :	 1;
-		uint64_t	i_tt_respreqd		  :	 1;
-		uint64_t	i_tt_bte_num		  :	 1;
-		uint64_t	i_cbn			  :	 1;
-		uint64_t	i_match			  :	 1;
-		uint64_t	i_rpcnt_lt_34		  :	 1;
-		uint64_t	i_rpcnt_ge_34		  :	 1;
-		uint64_t	i_rpcnt_lt_18		  :	 1;
-		uint64_t	i_rpcnt_ge_18		  :	 1;
-		uint64_t       i_rpcnt_lt_2              :      1;
-		uint64_t	i_rpcnt_ge_2		  :	 1;
-		uint64_t	i_rqcnt_lt_18		  :	 1;
-		uint64_t	i_rqcnt_ge_18		  :	 1;
-		uint64_t	i_rqcnt_lt_2		  :	 1;
-		uint64_t	i_rqcnt_ge_2		  :	 1;
-		uint64_t	i_tt_device		  :	 7;
-		uint64_t	i_tt_init		  :	 3;
-		uint64_t	i_reserved		  :	 5;
-	} ii_icsmh_fld_s;
-} ii_icsmh_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
- * II core and a 3-bit selection signal to the fsbclk domain in the II  *
- * wrapper.                                                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_idbss_u {
-	uint64_t	ii_idbss_regval;
-	struct  {
-		uint64_t	i_iioclk_core_submenu     :	 3;
-		uint64_t	i_rsvd			  :	 5;
-		uint64_t	i_fsbclk_wrapper_submenu  :	 3;
-		uint64_t	i_rsvd_1		  :	 5;
-		uint64_t	i_iioclk_menu		  :	 5;
-		uint64_t	i_rsvd_2		  :	43;
-	} ii_idbss_fld_s;
-} ii_idbss_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register is used to set up the length for a       *
- * transfer and then to monitor the progress of that transfer. This     *
- * register needs to be initialized before a transfer is started. A     *
- * legitimate write to this register will set the Busy bit, clear the   *
- * Error bit, and initialize the length to the value desired.           *
- * While the transfer is in progress, hardware will decrement the       *
- * length field with each successful block that is copied. Once the     *
- * transfer completes, hardware will clear the Busy bit. The length     *
- * field will also contain the number of cache lines left to be         *
- * transferred.                                                         *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibls0_u {
-	uint64_t	ii_ibls0_regval;
-	struct	{
-		uint64_t	i_length		  :	16;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_busy			  :	 1;
-		uint64_t       i_rsvd                    :     43;
-	} ii_ibls0_fld_s;
-} ii_ibls0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibsa0_u {
-	uint64_t	ii_ibsa0_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	42;
-		uint64_t       i_rsvd                    :     15;
-	} ii_ibsa0_fld_s;
-} ii_ibsa0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibda0_u {
-	uint64_t	ii_ibda0_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	42;
-		uint64_t	i_rsvd			  :	15;
-	} ii_ibda0_fld_s;
-} ii_ibda0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  Writing to this register sets up the attributes of the transfer     *
- * and initiates the transfer operation. Reading this register has      *
- * the side effect of terminating any transfer in progress. Note:       *
- * stopping a transfer midstream could have an adverse impact on the    *
- * other BTE. If a BTE stream has to be stopped (due to error           *
- * handling for example), both BTE streams should be stopped and        *
- * their transfers discarded.                                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibct0_u {
-	uint64_t	ii_ibct0_regval;
-	struct  {
-		uint64_t	i_zerofill                :	 1;
-		uint64_t	i_rsvd_2		  :	 3;
-		uint64_t	i_notify		  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t       i_poison                  :      1;
-		uint64_t       i_rsvd                    :     55;
-	} ii_ibct0_fld_s;
-} ii_ibct0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the address to which the WINV is sent.       *
- * This address has to be cache line aligned.                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibna0_u {
-	uint64_t	ii_ibna0_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	42;
-		uint64_t	i_rsvd			  :	15;
-	} ii_ibna0_fld_s;
-} ii_ibna0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the programmable level as well as the node   *
- * ID and PI unit of the processor to which the interrupt will be       *
- * sent.                                                                *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibia0_u {
-	uint64_t	ii_ibia0_regval;
-	struct  {
-		uint64_t	i_rsvd_2                   :	 1;
-		uint64_t	i_node_id		  :	11;
-		uint64_t	i_rsvd_1		  :	 4;
-		uint64_t	i_level			  :	 7;
-		uint64_t       i_rsvd                    :     41;
-	} ii_ibia0_fld_s;
-} ii_ibia0_u_t;
-
-
-/************************************************************************
- *                                                                      *
- * Description:  This register is used to set up the length for a       *
- * transfer and then to monitor the progress of that transfer. This     *
- * register needs to be initialized before a transfer is started. A     *
- * legitimate write to this register will set the Busy bit, clear the   *
- * Error bit, and initialize the length to the value desired.           *
- * While the transfer is in progress, hardware will decrement the       *
- * length field with each successful block that is copied. Once the     *
- * transfer completes, hardware will clear the Busy bit. The length     *
- * field will also contain the number of cache lines left to be         *
- * transferred.                                                         *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibls1_u {
-	uint64_t	ii_ibls1_regval;
-	struct  {
-		uint64_t	i_length                  :	16;
-		uint64_t	i_error			  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_busy			  :	 1;
-		uint64_t       i_rsvd                    :     43;
-	} ii_ibls1_fld_s;
-} ii_ibls1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibsa1_u {
-	uint64_t	ii_ibsa1_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	33;
-		uint64_t	i_rsvd			  :	24;
-	} ii_ibsa1_fld_s;
-} ii_ibsa1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibda1_u {
-	uint64_t	ii_ibda1_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	33;
-		uint64_t	i_rsvd			  :	24;
-	} ii_ibda1_fld_s;
-} ii_ibda1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  Writing to this register sets up the attributes of the transfer     *
- * and initiates the transfer operation. Reading this register has      *
- * the side effect of terminating any transfer in progress. Note:       *
- * stopping a transfer midstream could have an adverse impact on the    *
- * other BTE. If a BTE stream has to be stopped (due to error           *
- * handling for example), both BTE streams should be stopped and        *
- * their transfers discarded.                                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibct1_u {
-	uint64_t	ii_ibct1_regval;
-	struct  {
-		uint64_t	i_zerofill                :	 1;
-		uint64_t	i_rsvd_2		  :	 3;
-		uint64_t	i_notify		  :	 1;
-		uint64_t	i_rsvd_1		  :	 3;
-		uint64_t	i_poison		  :	 1;
-		uint64_t	i_rsvd			  :	55;
-	} ii_ibct1_fld_s;
-} ii_ibct1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the address to which the WINV is sent.       *
- * This address has to be cache line aligned.                           *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibna1_u {
-	uint64_t	ii_ibna1_regval;
-	struct  {
-		uint64_t	i_rsvd_1                  :	 7;
-		uint64_t	i_addr			  :	33;
-		uint64_t       i_rsvd                    :     24;
-	} ii_ibna1_fld_s;
-} ii_ibna1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register contains the programmable level as well as the node   *
- * ID and PI unit of the processor to which the interrupt will be       *
- * sent.                                                                *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ibia1_u {
-	uint64_t	ii_ibia1_regval;
-	struct  {
-		uint64_t	i_pi_id                   :	 1;
-		uint64_t	i_node_id		  :	 8;
-		uint64_t	i_rsvd_1		  :	 7;
-		uint64_t	i_level			  :	 7;
-		uint64_t	i_rsvd			  :	41;
-	} ii_ibia1_fld_s;
-} ii_ibia1_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *  This register defines the resources that feed information into      *
- * the two performance counters located in the IO Performance           *
- * Profiling Register. There are 17 different quantities that can be    *
- * measured. Given these 17 different options, the two performance      *
- * counters have 15 of them in common; menu selections 0 through 0xE    *
- * are identical for each performance counter. As for the other two     *
- * options, one is available from one performance counter and the       *
- * other is available from the other performance counter. Hence, the    *
- * II supports all 17*16=272 possible combinations of quantities to     *
- * measure.                                                             *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ipcr_u {
-	uint64_t	ii_ipcr_regval;
-	struct  {
-		uint64_t	i_ippr0_c                 :	 4;
-		uint64_t	i_ippr1_c		  :	 4;
-		uint64_t	i_icct			  :	 8;
-		uint64_t       i_rsvd                    :     48;
-	} ii_ipcr_fld_s;
-} ii_ipcr_u_t;
-
-
-/************************************************************************
- *                                                                      *
- *                                                                      *
- *                                                                      *
- ************************************************************************/
-
-typedef union ii_ippr_u {
-	uint64_t	ii_ippr_regval;
-	struct  {
-		uint64_t	i_ippr0                   :	32;
-		uint64_t	i_ippr1			  :	32;
-	} ii_ippr_fld_s;
-} ii_ippr_u_t;
-
-
-
-/**************************************************************************
- *                                                                        *
- * The following defines which were not formed into structures are        *
- * probably indentical to another register, and the name of the           *
- * register is provided against each of these registers. This             *
- * information needs to be checked carefully                              *
- *                                                                        *
- *           IIO_ICRB1_A                IIO_ICRB0_A                       *
- *           IIO_ICRB1_B                IIO_ICRB0_B                       *
- *           IIO_ICRB1_C                IIO_ICRB0_C                       *
- *           IIO_ICRB1_D                IIO_ICRB0_D                       *
- *           IIO_ICRB1_E                IIO_ICRB0_E                       *
- *           IIO_ICRB2_A                IIO_ICRB0_A                       *
- *           IIO_ICRB2_B                IIO_ICRB0_B                       *
- *           IIO_ICRB2_C                IIO_ICRB0_C                       *
- *           IIO_ICRB2_D                IIO_ICRB0_D                       *
- *           IIO_ICRB2_E                IIO_ICRB0_E                       *
- *           IIO_ICRB3_A                IIO_ICRB0_A                       *
- *           IIO_ICRB3_B                IIO_ICRB0_B                       *
- *           IIO_ICRB3_C                IIO_ICRB0_C                       *
- *           IIO_ICRB3_D                IIO_ICRB0_D                       *
- *           IIO_ICRB3_E                IIO_ICRB0_E                       *
- *           IIO_ICRB4_A                IIO_ICRB0_A                       *
- *           IIO_ICRB4_B                IIO_ICRB0_B                       *
- *           IIO_ICRB4_C                IIO_ICRB0_C                       *
- *           IIO_ICRB4_D                IIO_ICRB0_D                       *
- *           IIO_ICRB4_E                IIO_ICRB0_E                       *
- *           IIO_ICRB5_A                IIO_ICRB0_A                       *
- *           IIO_ICRB5_B                IIO_ICRB0_B                       *
- *           IIO_ICRB5_C                IIO_ICRB0_C                       *
- *           IIO_ICRB5_D                IIO_ICRB0_D                       *
- *           IIO_ICRB5_E                IIO_ICRB0_E                       *
- *           IIO_ICRB6_A                IIO_ICRB0_A                       *
- *           IIO_ICRB6_B                IIO_ICRB0_B                       *
- *           IIO_ICRB6_C                IIO_ICRB0_C                       *
- *           IIO_ICRB6_D                IIO_ICRB0_D                       *
- *           IIO_ICRB6_E                IIO_ICRB0_E                       *
- *           IIO_ICRB7_A                IIO_ICRB0_A                       *
- *           IIO_ICRB7_B                IIO_ICRB0_B                       *
- *           IIO_ICRB7_C                IIO_ICRB0_C                       *
- *           IIO_ICRB7_D                IIO_ICRB0_D                       *
- *           IIO_ICRB7_E                IIO_ICRB0_E                       *
- *           IIO_ICRB8_A                IIO_ICRB0_A                       *
- *           IIO_ICRB8_B                IIO_ICRB0_B                       *
- *           IIO_ICRB8_C                IIO_ICRB0_C                       *
- *           IIO_ICRB8_D                IIO_ICRB0_D                       *
- *           IIO_ICRB8_E                IIO_ICRB0_E                       *
- *           IIO_ICRB9_A                IIO_ICRB0_A                       *
- *           IIO_ICRB9_B                IIO_ICRB0_B                       *
- *           IIO_ICRB9_C                IIO_ICRB0_C                       *
- *           IIO_ICRB9_D                IIO_ICRB0_D                       *
- *           IIO_ICRB9_E                IIO_ICRB0_E                       *
- *           IIO_ICRBA_A                IIO_ICRB0_A                       *
- *           IIO_ICRBA_B                IIO_ICRB0_B                       *
- *           IIO_ICRBA_C                IIO_ICRB0_C                       *
- *           IIO_ICRBA_D                IIO_ICRB0_D                       *
- *           IIO_ICRBA_E                IIO_ICRB0_E                       *
- *           IIO_ICRBB_A                IIO_ICRB0_A                       *
- *           IIO_ICRBB_B                IIO_ICRB0_B                       *
- *           IIO_ICRBB_C                IIO_ICRB0_C                       *
- *           IIO_ICRBB_D                IIO_ICRB0_D                       *
- *           IIO_ICRBB_E                IIO_ICRB0_E                       *
- *           IIO_ICRBC_A                IIO_ICRB0_A                       *
- *           IIO_ICRBC_B                IIO_ICRB0_B                       *
- *           IIO_ICRBC_C                IIO_ICRB0_C                       *
- *           IIO_ICRBC_D                IIO_ICRB0_D                       *
- *           IIO_ICRBC_E                IIO_ICRB0_E                       *
- *           IIO_ICRBD_A                IIO_ICRB0_A                       *
- *           IIO_ICRBD_B                IIO_ICRB0_B                       *
- *           IIO_ICRBD_C                IIO_ICRB0_C                       *
- *           IIO_ICRBD_D                IIO_ICRB0_D                       *
- *           IIO_ICRBD_E                IIO_ICRB0_E                       *
- *           IIO_ICRBE_A                IIO_ICRB0_A                       *
- *           IIO_ICRBE_B                IIO_ICRB0_B                       *
- *           IIO_ICRBE_C                IIO_ICRB0_C                       *
- *           IIO_ICRBE_D                IIO_ICRB0_D                       *
- *           IIO_ICRBE_E                IIO_ICRB0_E                       *
- *                                                                        *
- **************************************************************************/
-
-
-/*
- * Slightly friendlier names for some common registers.
- */
-#define IIO_WIDGET              IIO_WID      /* Widget identification */
-#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
-#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
-#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
-#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
-#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
-#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
-#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
-#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
-#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
-#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
-#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
-#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
-#define IIO_IGFX_0 		IIO_IGFX0
-#define IIO_IGFX_1 		IIO_IGFX1
-#define IIO_IBCT_0		IIO_IBCT0
-#define IIO_IBCT_1		IIO_IBCT1
-#define IIO_IBLS_0		IIO_IBLS0
-#define IIO_IBLS_1		IIO_IBLS1
-#define IIO_IBSA_0		IIO_IBSA0
-#define IIO_IBSA_1		IIO_IBSA1
-#define IIO_IBDA_0		IIO_IBDA0
-#define IIO_IBDA_1		IIO_IBDA1
-#define IIO_IBNA_0		IIO_IBNA0
-#define IIO_IBNA_1		IIO_IBNA1
-#define IIO_IBIA_0		IIO_IBIA0
-#define IIO_IBIA_1		IIO_IBIA1
-#define IIO_IOPRB_0		IIO_IPRB0
-
-#define IIO_PRTE_A(_x)		(IIO_IPRTE0_A + (8 * (_x)))
-#define IIO_PRTE_B(_x)		(IIO_IPRTE0_B + (8 * (_x)))
-#define IIO_NUM_PRTES		8	/* Total number of PRB table entries */
-#define IIO_WIDPRTE_A(x)	IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
-#define IIO_WIDPRTE_B(x)	IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
-
-#define IIO_NUM_IPRBS 		(9) 
-
-#define IIO_LLP_CSR_IS_UP               0x00002000
-#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
-#define IIO_LLP_CSR_LLP_STAT_SHFT       12
-
-#define IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */
-#define IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence Number errors */
-
-/* key to IIO_PROTECT_OVRRD */
-#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
-
-/* BTE register names */
-#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
-#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
-#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
-#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
-#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1   	(IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
-
-/* BTE register offsets from base */
-#define BTEOFF_STAT             0
-#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
-#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
-#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
-#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
-#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
-
-
-/* names used in shub diags */
-#define IIO_BASE_BTE0   IIO_IBLS_0		
-#define IIO_BASE_BTE1   IIO_IBLS_1		
-
-/*
- * Macro which takes the widget number, and returns the
- * IO PRB address of that widget.
- * value _x is expected to be a widget number in the range
- * 0, 8 - 0xF
- */
-#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
-                        (_x) : \
-                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
-
-
-/* GFX Flow Control Node/Widget Register */
-#define IIO_IGFX_W_NUM_BITS	4	/* size of widget num field */
-#define IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)
-#define IIO_IGFX_W_NUM_SHIFT	0
-#define IIO_IGFX_PI_NUM_BITS	1	/* size of PI num field */
-#define IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)
-#define IIO_IGFX_PI_NUM_SHIFT	4
-#define IIO_IGFX_N_NUM_BITS	8	/* size of node num field */
-#define IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)
-#define IIO_IGFX_N_NUM_SHIFT	5
-#define IIO_IGFX_P_NUM_BITS	1	/* size of processor num field */
-#define IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)
-#define IIO_IGFX_P_NUM_SHIFT	16
-#define IIO_IGFX_INIT(widget, pi, node, cpu)				(\
-	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \
-	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \
-	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \
-	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
-
-
-/* Scratch registers (all bits available) */
-#define IIO_SCRATCH_REG0        IIO_ISCR0
-#define IIO_SCRATCH_REG1        IIO_ISCR1
-#define IIO_SCRATCH_MASK        0xffffffffffffffffUL
-
-#define IIO_SCRATCH_BIT0_0      0x0000000000000001UL
-#define IIO_SCRATCH_BIT0_1      0x0000000000000002UL
-#define IIO_SCRATCH_BIT0_2      0x0000000000000004UL
-#define IIO_SCRATCH_BIT0_3      0x0000000000000008UL
-#define IIO_SCRATCH_BIT0_4      0x0000000000000010UL
-#define IIO_SCRATCH_BIT0_5      0x0000000000000020UL
-#define IIO_SCRATCH_BIT0_6      0x0000000000000040UL
-#define IIO_SCRATCH_BIT0_7      0x0000000000000080UL
-#define IIO_SCRATCH_BIT0_8      0x0000000000000100UL
-#define IIO_SCRATCH_BIT0_9      0x0000000000000200UL
-#define IIO_SCRATCH_BIT0_A      0x0000000000000400UL
-
-#define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
-#define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
-/* IO Translation Table Entries */
-#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
-                                        /* Hw manuals number them 1..7! */
-/*
- * IIO_IMEM Register fields.
- */
-#define IIO_IMEM_W0ESD  0x1UL             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1UL << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1UL << 8)        /* BTE 1 Shut down due to error */
-
-/*
- * As a permanent workaround for a bug in the PI side of the shub, we've
- * redefined big window 7 as small window 0.
- XXX does this still apply for SN1??
- */
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
-
-/*
- * Use the top big window as a surrogate for the first small window
- */
-#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
-
-#define ILCSR_WARM_RESET        0x100
-
-/*
- * CRB manipulation macros
- *      The CRB macros are slightly complicated, since there are up to
- *      four registers associated with each CRB entry.
- */
-#define IIO_NUM_CRBS            15      /* Number of CRBs */
-#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
-#define IIO_ICRB_OFFSET         8
-#define IIO_ICRB_0              IIO_ICRB0_A
-#define IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
-/* XXX - This is now tuneable:
-        #define IIO_FIRST_PC_ENTRY 12
- */
-
-#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
-#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
-#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
-#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
-#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
-
-#define TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)
-
-/*
- * values for "ecode" field
- */
-#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
-                                         * e.g. WINV to a Read only line. */
-#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
-
-/*
- * Values for field imsgtype
- */
-#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
-#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
-
-/*
- * values for field initiator.
- */
-#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
-#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
-
-/*
- * Number of credits Hub widget has while sending req/response to
- * xbow.
- * Value of 3 is required by Xbow 1.1
- * We may be able to increase this to 4 with Xbow 1.2.
- */
-#define       HUBII_XBOW_CREDIT       3
-#define       HUBII_XBOW_REV2_CREDIT  4
-
-/*
- * Number of credits that xtalk devices should use when communicating
- * with a SHub (depth of SHub's queue).
- */
-#define HUB_CREDIT 4
-
-/*
- * Some IIO_PRB fields
- */
-#define IIO_PRB_MULTI_ERR	(1LL << 63)
-#define IIO_PRB_SPUR_RD		(1LL << 51)
-#define IIO_PRB_SPUR_WR		(1LL << 50)
-#define IIO_PRB_RD_TO		(1LL << 49)
-#define IIO_PRB_ERROR		(1LL << 48)
-
-/*************************************************************************
-
- Some of the IIO field masks and shifts are defined here.
- This is in order to maintain compatibility in SN0 and SN1 code
- 
-**************************************************************************/
-
-/*
- * ICMR register fields
- * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
- * present in SHub)
- */
-
-#define IIO_ICMR_CRB_VLD_SHFT   20
-#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
-
-#define IIO_ICMR_FC_CNT_SHFT    16
-#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
-
-#define IIO_ICMR_C_CNT_SHFT     4
-#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
-
-#define IIO_ICMR_PRECISE        (1UL << 52)
-#define IIO_ICMR_CLR_RPPD       (1UL << 13)
-#define IIO_ICMR_CLR_RQPD       (1UL << 12)
-
-/*
- * IIO PIO Deallocation register field masks : (IIO_IPDR)
- XXX present but not needed in bedrock?  See the manual.
- */
-#define IIO_IPDR_PND    (1 << 4)
-
-/*
- * IIO CRB deallocation register field masks: (IIO_ICDR)
- */
-#define IIO_ICDR_PND    (1 << 4)
-
-/* 
- * IO BTE Length/Status (IIO_IBLS) register bit field definitions
- */
-#define IBLS_BUSY		(0x1UL << 20)
-#define IBLS_ERROR_SHFT		16
-#define IBLS_ERROR		(0x1UL << IBLS_ERROR_SHFT)
-#define IBLS_LENGTH_MASK	0xffff
-
-/*
- * IO BTE Control/Terminate register (IBCT) register bit field definitions
- */
-#define IBCT_POISON		(0x1UL << 8)
-#define IBCT_NOTIFY		(0x1UL << 4)
-#define IBCT_ZFIL_MODE		(0x1UL << 0)
-
-/*
- * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
- */
-#define IIEPH1_VALID		(1UL << 44)
-#define IIEPH1_OVERRUN		(1UL << 40)
-#define IIEPH1_ERR_TYPE_SHFT	32
-#define IIEPH1_ERR_TYPE_MASK	0xf
-#define IIEPH1_SOURCE_SHFT	20
-#define IIEPH1_SOURCE_MASK	11
-#define IIEPH1_SUPPL_SHFT	8
-#define IIEPH1_SUPPL_MASK	11
-#define IIEPH1_CMD_SHFT		0
-#define IIEPH1_CMD_MASK		7
-
-#define IIEPH2_TAIL		(1UL << 40)
-#define IIEPH2_ADDRESS_SHFT	0
-#define IIEPH2_ADDRESS_MASK	38
-
-#define IIEPH1_ERR_SHORT_REQ	2
-#define IIEPH1_ERR_SHORT_REPLY	3
-#define IIEPH1_ERR_LONG_REQ	4
-#define IIEPH1_ERR_LONG_REPLY	5
-
-/*
- * IO Error Clear register bit field definitions
- */
-#define IECLR_PI1_FWD_INT	(1UL << 31)  /* clear PI1_FORWARD_INT in iidsr */
-#define IECLR_PI0_FWD_INT	(1UL << 30)  /* clear PI0_FORWARD_INT in iidsr */
-#define IECLR_SPUR_RD_HDR	(1UL << 29)  /* clear valid bit in ixss reg */
-#define IECLR_BTE1		(1UL << 18)  /* clear bte error 1 */
-#define IECLR_BTE0		(1UL << 17)  /* clear bte error 0 */
-#define IECLR_CRAZY		(1UL << 16)  /* clear crazy bit in wstat reg */
-#define IECLR_PRB_F		(1UL << 15)  /* clear err bit in PRB_F reg */
-#define IECLR_PRB_E		(1UL << 14)  /* clear err bit in PRB_E reg */
-#define IECLR_PRB_D		(1UL << 13)  /* clear err bit in PRB_D reg */
-#define IECLR_PRB_C		(1UL << 12)  /* clear err bit in PRB_C reg */
-#define IECLR_PRB_B		(1UL << 11)  /* clear err bit in PRB_B reg */
-#define IECLR_PRB_A		(1UL << 10)  /* clear err bit in PRB_A reg */
-#define IECLR_PRB_9		(1UL << 9)   /* clear err bit in PRB_9 reg */
-#define IECLR_PRB_8		(1UL << 8)   /* clear err bit in PRB_8 reg */
-#define IECLR_PRB_0		(1UL << 0)   /* clear err bit in PRB_0 reg */
-
-/*
- * IIO CRB control register Fields: IIO_ICCR 
- */
-#define	IIO_ICCR_PENDING	(0x10000)
-#define	IIO_ICCR_CMD_MASK	(0xFF)
-#define	IIO_ICCR_CMD_SHFT	(7)
-#define	IIO_ICCR_CMD_NOP	(0x0)	/* No Op */
-#define	IIO_ICCR_CMD_WAKE	(0x100) /* Reactivate CRB entry and process */
-#define	IIO_ICCR_CMD_TIMEOUT	(0x200)	/* Make CRB timeout & mark invalid */
-#define	IIO_ICCR_CMD_EJECT	(0x400)	/* Contents of entry written to memory 
-					 * via a WB
-					 */
-#define	IIO_ICCR_CMD_FLUSH	(0x800)
-
-/*
- *
- * CRB Register description.
- *
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- *
- * Many of the fields in CRB are status bits used by hardware
- * for implementation of the protocol. It's very dangerous to
- * mess around with the CRB registers.
- *
- * It's OK to read the CRB registers and try to make sense out of the
- * fields in CRB.
- *
- * Updating CRB requires all activities in Hub IIO to be quiesced.
- * otherwise, a write to CRB could corrupt other CRB entries.
- * CRBs are here only as a back door peek to shub IIO's status.
- * Quiescing implies  no dmas no PIOs
- * either directly from the cpu or from sn0net.
- * this is not something that can be done easily. So, AVOID updating
- * CRBs.
- */
-
-/*
- * Easy access macros for CRBs, all 5 registers (A-E)
- */
-typedef ii_icrb0_a_u_t icrba_t;
-#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
-#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
-#define a_addr          ii_icrb0_a_fld_s.ia_addr
-#define a_valid         ii_icrb0_a_fld_s.ia_vld
-#define a_iow           ii_icrb0_a_fld_s.ia_iow
-#define a_regvalue	ii_icrb0_a_regval
-
-typedef ii_icrb0_b_u_t icrbb_t;
-#define b_use_old       ii_icrb0_b_fld_s.ib_use_old
-#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
-#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
-#define b_initiator     ii_icrb0_b_fld_s.ib_init
-#define b_exc           ii_icrb0_b_fld_s.ib_exc
-#define b_ackcnt        ii_icrb0_b_fld_s.ib_ack_cnt
-#define b_resp          ii_icrb0_b_fld_s.ib_resp
-#define b_ack           ii_icrb0_b_fld_s.ib_ack
-#define b_hold          ii_icrb0_b_fld_s.ib_hold
-#define b_wb            ii_icrb0_b_fld_s.ib_wb
-#define b_intvn         ii_icrb0_b_fld_s.ib_intvn
-#define b_stall_ib      ii_icrb0_b_fld_s.ib_stall_ib
-#define b_stall_int     ii_icrb0_b_fld_s.ib_stall__intr
-#define b_stall_bte_0   ii_icrb0_b_fld_s.ib_stall__bte_0
-#define b_stall_bte_1   ii_icrb0_b_fld_s.ib_stall__bte_1
-#define b_error         ii_icrb0_b_fld_s.ib_error
-#define b_ecode         ii_icrb0_b_fld_s.ib_errcode
-#define b_lnetuce       ii_icrb0_b_fld_s.ib_ln_uce
-#define b_mark          ii_icrb0_b_fld_s.ib_mark
-#define b_xerr          ii_icrb0_b_fld_s.ib_xt_err
-#define b_regvalue	ii_icrb0_b_regval
-
-typedef ii_icrb0_c_u_t icrbc_t;
-#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
-#define c_barrop        ii_icrb0_c_fld_s.ic_bo
-#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
-#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
-#define c_btenum        ii_icrb0_c_fld_s.ic_bte_num
-#define c_cohtrans      ii_icrb0_c_fld_s.ic_ct
-#define c_xtsize        ii_icrb0_c_fld_s.ic_size
-#define c_source        ii_icrb0_c_fld_s.ic_source
-#define c_regvalue	ii_icrb0_c_regval
-
-
-typedef ii_icrb0_d_u_t icrbd_t;
-#define d_sleep         ii_icrb0_d_fld_s.id_sleep
-#define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
-#define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
-#define d_bteop         ii_icrb0_d_fld_s.id_bte_op
-#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
-#define d_benable       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
-#define d_regvalue	ii_icrb0_d_regval
-
-typedef ii_icrb0_e_u_t icrbe_t;
-#define icrbe_ctxtvld   ii_icrb0_e_fld_s.ie_cvld
-#define icrbe_toutvld   ii_icrb0_e_fld_s.ie_tvld
-#define icrbe_context   ii_icrb0_e_fld_s.ie_context
-#define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
-#define e_regvalue	ii_icrb0_e_regval
-
-
-/* Number of widgets supported by shub */
-#define HUB_NUM_WIDGET          9
-#define HUB_WIDGET_ID_MIN       0x8
-#define HUB_WIDGET_ID_MAX       0xf
-
-#define HUB_WIDGET_PART_NUM     0xc120
-#define MAX_HUBS_PER_XBOW       2
-
-/* A few more #defines for backwards compatibility */
-#define iprb_t          ii_iprb0_u_t
-#define iprb_regval     ii_iprb0_regval
-#define iprb_mult_err	ii_iprb0_fld_s.i_mult_err
-#define iprb_spur_rd	ii_iprb0_fld_s.i_spur_rd
-#define iprb_spur_wr	ii_iprb0_fld_s.i_spur_wr
-#define iprb_rd_to	ii_iprb0_fld_s.i_rd_to
-#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
-#define iprb_error      ii_iprb0_fld_s.i_error
-#define iprb_ff         ii_iprb0_fld_s.i_f
-#define iprb_mode       ii_iprb0_fld_s.i_m
-#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
-#define iprb_anakctr    ii_iprb0_fld_s.i_na
-#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
-
-#define LNK_STAT_WORKING        0x2		/* LLP is working */
-
-#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
-#define IIO_WSTAT_TXRETRY_SHFT  (16)
-#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
-                                          IIO_WSTAT_TXRETRY_MASK)
-
-/* Number of II perf. counters we can multiplex at once */
-
-#define IO_PERF_SETS	32
-
-/* Bit for the widget in inbound access register */
-#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
-/* Bit for the widget in outbound access register */
-#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
-
-/* NOTE: The following define assumes that we are going to get
- * widget numbers from 8 thru F and the device numbers within
- * widget from 0 thru 7.
- */
-#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
-
-/* IO Interrupt Destination Register */
-#define IIO_IIDSR_SENT_SHIFT    28
-#define IIO_IIDSR_SENT_MASK     0x30000000
-#define IIO_IIDSR_ENB_SHIFT     24
-#define IIO_IIDSR_ENB_MASK      0x01000000
-#define IIO_IIDSR_NODE_SHIFT    9
-#define IIO_IIDSR_NODE_MASK     0x000ff700
-#define IIO_IIDSR_PI_ID_SHIFT   8
-#define IIO_IIDSR_PI_ID_MASK    0x00000100
-#define IIO_IIDSR_LVL_SHIFT     0
-#define IIO_IIDSR_LVL_MASK      0x000000ff
-
-/* Xtalk timeout threshhold register (IIO_IXTT) */
-#define IXTT_RRSP_TO_SHFT	55	   /* read response timeout */
-#define IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)
-#define IXTT_RRSP_PS_SHFT	32	   /* read responsed TO prescalar */
-#define IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
-#define IXTT_TAIL_TO_SHFT	0	   /* tail timeout counter threshold */
-#define IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
-
-/*
- * The IO LLP control status register and widget control register
- */
-
-typedef union hubii_wcr_u {
-        uint64_t      wcr_reg_value;
-        struct {
-	  uint64_t	wcr_widget_id:   4,     /* LLP crossbar credit */
-			wcr_tag_mode:	 1,	/* Tag mode */
-			wcr_rsvd1:	 8,	/* Reserved */
-			wcr_xbar_crd:	 3,	/* LLP crossbar credit */
-			wcr_f_bad_pkt:	 1,	/* Force bad llp pkt enable */
-			wcr_dir_con:	 1,	/* widget direct connect */
-			wcr_e_thresh:	 5,	/* elasticity threshold */
-			wcr_rsvd:	41;	/* unused */
-        } wcr_fields_s;
-} hubii_wcr_t;
-
-#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
-
-/* The structures below are defined to extract and modify the ii
-performance registers */
-
-/* io_perf_sel allows the caller to specify what tests will be
-   performed */
-
-typedef union io_perf_sel {
-        uint64_t perf_sel_reg;
-        struct {
-               uint64_t	perf_ippr0 :  4,
-				perf_ippr1 :  4,
-				perf_icct  :  8,
-				perf_rsvd  : 48;
-        } perf_sel_bits;
-} io_perf_sel_t;
-
-/* io_perf_cnt is to extract the count from the shub registers. Due to
-   hardware problems there is only one counter, not two. */
-
-typedef union io_perf_cnt {
-        uint64_t      perf_cnt;
-        struct {
-               uint64_t	perf_cnt   : 20,
-				perf_rsvd2 : 12,
-				perf_rsvd1 : 32;
-        } perf_cnt_bits;
-
-} io_perf_cnt_t;
-
-typedef union iprte_a {
-	uint64_t	entry;
-	struct {
-		uint64_t	i_rsvd_1                  :	 3;
-		uint64_t	i_addr			  :	38;
-		uint64_t	i_init			  :	 3;
-		uint64_t	i_source		  :	 8;
-		uint64_t	i_rsvd			  :	 2;
-		uint64_t	i_widget		  :	 4;
-		uint64_t	i_to_cnt		  :	 5;
-		uint64_t       i_vld                     :      1;
-	} iprte_fields;
-} iprte_a_t;
-
-#endif /* _ASM_IA64_SN_SHUBIO_H */
-
diff -Nru a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c
--- a/arch/ia64/sn/kernel/bte.c	2004-10-19 13:37:28 -07:00
+++ b/arch/ia64/sn/kernel/bte.c	2005-01-28 15:38:45 -08:00
@@ -13,7 +13,7 @@
 #include <asm/sn/arch.h>
 #include <asm/sn/sn_cpuid.h>
 #include <asm/sn/pda.h>
-#include "shubio.h"
+#include <asm/sn/shubio.h>
 #include <asm/nodedata.h>
 #include <asm/delay.h>
 
diff -Nru a/arch/ia64/sn/kernel/bte_error.c b/arch/ia64/sn/kernel/bte_error.c
--- a/arch/ia64/sn/kernel/bte_error.c	2005-01-19 17:15:06 -08:00
+++ b/arch/ia64/sn/kernel/bte_error.c	2005-01-28 15:38:54 -08:00
@@ -10,7 +10,7 @@
 #include <asm/sn/sn_sal.h>
 #include "ioerror.h"
 #include <asm/sn/addrs.h>
-#include "shubio.h"
+#include <asm/sn/shubio.h>
 #include <asm/sn/geo.h>
 #include "xtalk/xwidgetdev.h"
 #include "xtalk/hubdev.h"
diff -Nru a/arch/ia64/sn/kernel/huberror.c b/arch/ia64/sn/kernel/huberror.c
--- a/arch/ia64/sn/kernel/huberror.c	2004-10-19 13:39:55 -07:00
+++ b/arch/ia64/sn/kernel/huberror.c	2005-01-28 15:38:55 -08:00
@@ -13,7 +13,7 @@
 #include <asm/sn/sn_sal.h>
 #include "ioerror.h"
 #include <asm/sn/addrs.h>
-#include "shubio.h"
+#include <asm/sn/shubio.h>
 #include <asm/sn/geo.h>
 #include "xtalk/xwidgetdev.h"
 #include "xtalk/hubdev.h"
diff -Nru a/arch/mips/Kconfig b/arch/mips/Kconfig
--- a/arch/mips/Kconfig	2005-01-30 22:33:45 -08:00
+++ b/arch/mips/Kconfig	2005-02-03 06:42:40 -08:00
@@ -456,6 +456,9 @@
 
 config SGI_IP22
 	bool "Support for SGI IP22 (Indy/Indigo2)"
+	select ARC
+	select ARC32
+	select BOOT_ELF32
 	select DMA_NONCOHERENT
 	select IP22_CPU_SCACHE
 	select IRQ_CPU
diff -Nru a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
--- a/arch/mips/configs/ip22_defconfig	2004-12-15 12:56:10 -08:00
+++ b/arch/mips/configs/ip22_defconfig	2005-02-03 06:42:40 -08:00
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Sun Nov 21 14:11:59 2004
+# Linux kernel version: 2.6.11-rc2
+# Wed Jan 26 02:49:04 2005
 #
 CONFIG_MIPS=y
 # CONFIG_MIPS64 is not set
@@ -86,16 +86,16 @@
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_TOSHIBA_RBTX4927 is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_HAVE_DEC_LOCK=y
 CONFIG_ARC=y
 CONFIG_DMA_NONCOHERENT=y
 # CONFIG_CPU_LITTLE_ENDIAN is not set
 CONFIG_IRQ_CPU=y
 CONFIG_SWAP_IO_SPACE=y
+CONFIG_ARC32=y
 CONFIG_BOOT_ELF32=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_ARC32=y
-# CONFIG_FB is not set
 CONFIG_ARC_CONSOLE=y
 CONFIG_ARC_PROMLIB=y
 
@@ -139,6 +139,19 @@
 CONFIG_MMU=y
 
 #
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# PCI Hotplug Support
+#
+
+#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
@@ -154,6 +167,7 @@
 #
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -173,9 +187,11 @@
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_LBD is not set
 CONFIG_CDROM_PKTCDVD=m
@@ -189,6 +205,7 @@
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
+CONFIG_ATA_OVER_ETH=m
 
 #
 # ATA/ATAPI/MFM/RLL support
@@ -223,13 +240,13 @@
 #
 CONFIG_SCSI_SPI_ATTRS=m
 # CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
 
 #
 # SCSI low-level drivers
 #
 CONFIG_SGIWD93_SCSI=y
 # CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_QLOGIC_1280_1040 is not set
 # CONFIG_SCSI_DEBUG is not set
 
 #
@@ -390,8 +407,6 @@
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
-# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
-# CONFIG_IP_NF_COMPAT_IPFWADM is not set
 
 #
 # IPv6: Netfilter Configuration
@@ -470,6 +485,7 @@
 CONFIG_NET_CLS_U32=m
 # CONFIG_CLS_U32_PERF is not set
 # CONFIG_NET_CLS_IND is not set
+# CONFIG_CLS_U32_MARK is not set
 CONFIG_NET_CLS_RSVP=m
 CONFIG_NET_CLS_RSVP6=m
 # CONFIG_NET_CLS_ACT is not set
@@ -560,6 +576,7 @@
 CONFIG_SERIO_I8042=y
 CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_CT82C710 is not set
+CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
 
 #
@@ -626,7 +643,6 @@
 #
 # Ftape, the floppy tape device driver
 #
-# CONFIG_AGP is not set
 # CONFIG_DRM is not set
 CONFIG_RAW_DRIVER=m
 CONFIG_MAX_RAW_DEVS=256
@@ -658,6 +674,7 @@
 #
 # Graphics support
 #
+# CONFIG_FB is not set
 
 #
 # Console display driver support
@@ -675,6 +692,7 @@
 # CONFIG_LOGO_LINUX_VGA16 is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 CONFIG_LOGO_SGI_CLUT224=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -688,11 +706,25 @@
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 
 #
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
 # USB Gadget Support
 #
 # CONFIG_USB_GADGET is not set
 
 #
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=m
@@ -797,7 +829,7 @@
 CONFIG_CIFS=m
 # CONFIG_CIFS_STATS is not set
 # CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_POSIX is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
@@ -868,6 +900,11 @@
 CONFIG_NLS_UTF8=m
 
 #
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set
@@ -910,10 +947,14 @@
 CONFIG_CRYPTO_TEST=m
 
 #
+# Hardware crypto devices
+#
+
+#
 # Library routines
 #
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC32 is not set
+CONFIG_CRC32=m
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
diff -Nru a/arch/mips/defconfig b/arch/mips/defconfig
--- a/arch/mips/defconfig	2004-12-15 12:56:10 -08:00
+++ b/arch/mips/defconfig	2005-02-03 06:42:40 -08:00
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Sun Nov 21 14:11:54 2004
+# Linux kernel version: 2.6.11-rc2
+# Wed Jan 26 02:48:59 2005
 #
 CONFIG_MIPS=y
 # CONFIG_MIPS64 is not set
@@ -86,16 +86,16 @@
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_TOSHIBA_RBTX4927 is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_HAVE_DEC_LOCK=y
 CONFIG_ARC=y
 CONFIG_DMA_NONCOHERENT=y
 # CONFIG_CPU_LITTLE_ENDIAN is not set
 CONFIG_IRQ_CPU=y
 CONFIG_SWAP_IO_SPACE=y
+CONFIG_ARC32=y
 CONFIG_BOOT_ELF32=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_ARC32=y
-# CONFIG_FB is not set
 CONFIG_ARC_CONSOLE=y
 CONFIG_ARC_PROMLIB=y
 
@@ -139,6 +139,19 @@
 CONFIG_MMU=y
 
 #
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# PCI Hotplug Support
+#
+
+#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
@@ -154,6 +167,7 @@
 #
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -173,9 +187,11 @@
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_LBD is not set
 CONFIG_CDROM_PKTCDVD=m
@@ -189,6 +205,7 @@
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
+CONFIG_ATA_OVER_ETH=m
 
 #
 # ATA/ATAPI/MFM/RLL support
@@ -223,13 +240,13 @@
 #
 CONFIG_SCSI_SPI_ATTRS=m
 # CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
 
 #
 # SCSI low-level drivers
 #
 CONFIG_SGIWD93_SCSI=y
 # CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_QLOGIC_1280_1040 is not set
 # CONFIG_SCSI_DEBUG is not set
 
 #
@@ -390,8 +407,6 @@
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
-# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
-# CONFIG_IP_NF_COMPAT_IPFWADM is not set
 
 #
 # IPv6: Netfilter Configuration
@@ -470,6 +485,7 @@
 CONFIG_NET_CLS_U32=m
 # CONFIG_CLS_U32_PERF is not set
 # CONFIG_NET_CLS_IND is not set
+# CONFIG_CLS_U32_MARK is not set
 CONFIG_NET_CLS_RSVP=m
 CONFIG_NET_CLS_RSVP6=m
 # CONFIG_NET_CLS_ACT is not set
@@ -560,6 +576,7 @@
 CONFIG_SERIO_I8042=y
 CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_CT82C710 is not set
+CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
 
 #
@@ -626,7 +643,6 @@
 #
 # Ftape, the floppy tape device driver
 #
-# CONFIG_AGP is not set
 # CONFIG_DRM is not set
 CONFIG_RAW_DRIVER=m
 CONFIG_MAX_RAW_DEVS=256
@@ -658,6 +674,7 @@
 #
 # Graphics support
 #
+# CONFIG_FB is not set
 
 #
 # Console display driver support
@@ -675,6 +692,7 @@
 # CONFIG_LOGO_LINUX_VGA16 is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 CONFIG_LOGO_SGI_CLUT224=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -688,11 +706,25 @@
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 
 #
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
 # USB Gadget Support
 #
 # CONFIG_USB_GADGET is not set
 
 #
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=m
@@ -797,7 +829,7 @@
 CONFIG_CIFS=m
 # CONFIG_CIFS_STATS is not set
 # CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_POSIX is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
@@ -868,6 +900,11 @@
 CONFIG_NLS_UTF8=m
 
 #
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set
@@ -910,10 +947,14 @@
 CONFIG_CRYPTO_TEST=m
 
 #
+# Hardware crypto devices
+#
+
+#
 # Library routines
 #
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC32 is not set
+CONFIG_CRC32=m
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
diff -Nru a/arch/mips/lib-32/dump_tlb.c b/arch/mips/lib-32/dump_tlb.c
--- a/arch/mips/lib-32/dump_tlb.c	2004-02-19 12:53:00 -08:00
+++ b/arch/mips/lib-32/dump_tlb.c	2005-02-07 18:25:11 -08:00
@@ -32,6 +32,8 @@
 	case PM_256M:	return "256Mb";
 #endif
 	}
+
+	return "unknown";
 }
 
 #define BARRIER()					\
diff -Nru a/arch/mips/lib-64/dump_tlb.c b/arch/mips/lib-64/dump_tlb.c
--- a/arch/mips/lib-64/dump_tlb.c	2005-01-30 22:22:40 -08:00
+++ b/arch/mips/lib-64/dump_tlb.c	2005-02-07 18:25:11 -08:00
@@ -32,6 +32,8 @@
 	case PM_256M:	return "256Mb";
 #endif
 	}
+
+	return "unknown";
 }
 
 #define BARRIER()					\
diff -Nru a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
--- a/arch/mips/sgi-ip22/ip22-nvram.c	2004-02-19 12:53:02 -08:00
+++ b/arch/mips/sgi-ip22/ip22-nvram.c	2005-02-03 06:42:40 -08:00
@@ -26,7 +26,7 @@
 #define EEPROM_DATO	0x08	/* Data out */
 #define EEPROM_DATI	0x10	/* Data in */
 
-/* We need to use this functions early... */
+/* We need to use these functions early... */
 #define delay()	({						\
 	int x;							\
 	for (x=0; x<100000; x++) __asm__ __volatile__(""); })
diff -Nru a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
--- a/arch/mips/sgi-ip22/ip22-setup.c	2004-11-29 05:11:43 -08:00
+++ b/arch/mips/sgi-ip22/ip22-setup.c	2005-02-03 06:42:40 -08:00
@@ -120,9 +120,8 @@
 	}
 #endif
 
-#ifdef CONFIG_VT
-#ifdef CONFIG_SGI_NEWPORT_CONSOLE
-	if (ctype && *ctype == 'g'){
+#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
+	{
 		ULONG *gfxinfo;
 		ULONG * (*__vec)(void) = (void *) (long)
 			*((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20));
@@ -137,7 +136,6 @@
 			conswitchp = &newport_con;
 		}
 	}
-#endif
 #endif
 
 	return 0;
diff -Nru a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
--- a/arch/ppc/boot/simple/Makefile	2005-01-03 15:49:19 -08:00
+++ b/arch/ppc/boot/simple/Makefile	2005-02-03 06:42:41 -08:00
@@ -66,6 +66,12 @@
          end-$(CONFIG_EBONY)		:= ebony
   entrypoint-$(CONFIG_EBONY)		:= 0x01000000
 
+      zimage-$(CONFIG_LUAN)		:= zImage-TREE
+zimageinitrd-$(CONFIG_LUAN)		:= zImage.initrd-TREE
+         end-$(CONFIG_LUAN)		:= luan
+  entrypoint-$(CONFIG_LUAN)		:= 0x01000000
+     extra.o-$(CONFIG_LUAN)		:= pibs.o
+
       zimage-$(CONFIG_OCOTEA)		:= zImage-TREE
 zimageinitrd-$(CONFIG_OCOTEA)		:= zImage.initrd-TREE
          end-$(CONFIG_OCOTEA)		:= ocotea
diff -Nru a/arch/ppc/boot/simple/pibs.c b/arch/ppc/boot/simple/pibs.c
--- a/arch/ppc/boot/simple/pibs.c	2004-10-05 23:05:22 -07:00
+++ b/arch/ppc/boot/simple/pibs.c	2005-02-03 06:42:41 -08:00
@@ -1,5 +1,5 @@
 /*
- * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
+ * 2004-2005 (c) MontaVista, Software, Inc.  This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
@@ -10,7 +10,7 @@
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <asm/ppcboot.h>
-#include <platforms/4xx/ocotea.h>
+#include <asm/ibm4xx.h>
 
 extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
 				       unsigned long cksum);
@@ -89,13 +89,15 @@
 
 	decompress_kernel(load_addr, num_words, cksum);
 
-	mac64 = simple_strtoull((char *)OCOTEA_PIBS_MAC_BASE, 0, 16);
+	mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
 	memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
-	mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET), 0, 16);
+#ifdef CONFIG_440GX
+	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
 	memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
-	mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET*2), 0, 16);
+	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
 	memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
-	mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET*3), 0, 16);
+	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
 	memcpy(hold_residual->bi_enet3addr, (char *)&mac64+2, 6);
+#endif
 	return (void *)hold_residual;
 }
diff -Nru a/arch/ppc/configs/luan_defconfig b/arch/ppc/configs/luan_defconfig
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/configs/luan_defconfig	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,668 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11-rc2
+# Mon Jan 31 16:26:31 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_EBONY is not set
+CONFIG_LUAN=y
+# CONFIG_OCOTEA is not set
+CONFIG_440SP=y
+CONFIG_440=y
+CONFIG_IBM_OCP=y
+CONFIG_IBM_EMAC4=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on console=ttyS0,115200"
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=128
+CONFIG_IBM_EMAC_TXB=128
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -Nru a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
--- a/arch/ppc/kernel/head_44x.S	2005-01-03 15:49:17 -08:00
+++ b/arch/ppc/kernel/head_44x.S	2005-02-03 06:42:41 -08:00
@@ -21,7 +21,7 @@
  * 	Author: MontaVista Software, Inc.
  *         	frank_rowand@mvista.com or source@mvista.com
  * 	   	debbie_chu@mvista.com
- *    Copyright 2002-2004 MontaVista Software, Inc.
+ *    Copyright 2002-2005 MontaVista Software, Inc.
  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -185,11 +185,11 @@
 	 * are used for polled operation.
 	 */
  	/* pageid fields */
-	lis	r3,0xe000	
+	lis	r3,UART0_IO_BASE@h
 	ori	r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
 
 	/* xlat fields */
-	lis	r4,0x4000		/* RPN is 0x40000000 */
+	lis	r4,UART0_PHYS_IO_BASE@h		/* RPN depends on SoC */
 	ori	r4,r4,0x0001		/* ERPN is 1 for second 4GB page */
 
 	/* attrib fields */
diff -Nru a/arch/ppc/lib/locks.c b/arch/ppc/lib/locks.c
--- a/arch/ppc/lib/locks.c	2004-06-03 05:26:37 -07:00
+++ b/arch/ppc/lib/locks.c	2005-02-04 19:02:33 -08:00
@@ -91,44 +91,57 @@
 }
 EXPORT_SYMBOL(_raw_spin_unlock);
 
-
 /*
- * Just like x86, implement read-write locks as a 32-bit counter
- * with the high bit (sign) being the "write" bit.
- * -- Cort
+ * For rwlocks, zero is unlocked, -1 is write-locked,
+ * positive is read-locked.
  */
+static __inline__ int __read_trylock(rwlock_t *rw)
+{
+	signed int tmp;
+
+	__asm__ __volatile__(
+"2:	lwarx	%0,0,%1		# __read_trylock\n\
+	addic.	%0,%0,1\n\
+	ble-	1f\n"
+	PPC405_ERR77(0,%1)
+"	stwcx.	%0,0,%1\n\
+	bne-	2b\n\
+	isync\n\
+1:"
+	: "=&r"(tmp)
+	: "r"(&rw->lock)
+	: "cr0", "memory");
+
+	return tmp;
+}
+
+int _raw_read_trylock(rwlock_t *rw)
+{
+	return __read_trylock(rw) > 0;
+}
+EXPORT_SYMBOL(_raw_read_trylock);
+
 void _raw_read_lock(rwlock_t *rw)
 {
-	unsigned long stuck = INIT_STUCK;
-	int cpu = smp_processor_id();
+	unsigned int stuck;
 
-again:
-	/* get our read lock in there */
-	atomic_inc((atomic_t *) &(rw)->lock);
-	if ( (signed long)((rw)->lock) < 0) /* someone has a write lock */
-	{
-		/* turn off our read lock */
-		atomic_dec((atomic_t *) &(rw)->lock);
-		/* wait for the write lock to go away */
-		while ((signed long)((rw)->lock) < 0)
-		{
-			if(!--stuck)
-			{
-				printk("_read_lock(%p) CPU#%d\n", rw, cpu);
+	while (__read_trylock(rw) <= 0) {
+		stuck = INIT_STUCK;
+		while (!read_can_lock(rw)) {
+			if (--stuck == 0) {
+				printk("_read_lock(%p) CPU#%d lock %d\n",
+				       rw, _smp_processor_id(), rw->lock);
 				stuck = INIT_STUCK;
 			}
 		}
-		/* try to get the read lock again */
-		goto again;
 	}
-	wmb();
 }
 EXPORT_SYMBOL(_raw_read_lock);
 
 void _raw_read_unlock(rwlock_t *rw)
 {
 	if ( rw->lock == 0 )
-		printk("_read_unlock(): %s/%d (nip %08lX) lock %lx\n",
+		printk("_read_unlock(): %s/%d (nip %08lX) lock %d\n",
 		       current->comm,current->pid,current->thread.regs->nip,
 		      rw->lock);
 	wmb();
@@ -138,40 +151,17 @@
 
 void _raw_write_lock(rwlock_t *rw)
 {
-	unsigned long stuck = INIT_STUCK;
-	int cpu = smp_processor_id();
+	unsigned int stuck;
 
-again:
-	if ( test_and_set_bit(31,&(rw)->lock) ) /* someone has a write lock */
-	{
-		while ( (rw)->lock & (1<<31) ) /* wait for write lock */
-		{
-			if(!--stuck)
-			{
-				printk("write_lock(%p) CPU#%d lock %lx)\n",
-				       rw, cpu,rw->lock);
+	while (cmpxchg(&rw->lock, 0, -1) != 0) {
+		stuck = INIT_STUCK;
+		while (!write_can_lock(rw)) {
+			if (--stuck == 0) {
+				printk("write_lock(%p) CPU#%d lock %d)\n",
+				       rw, _smp_processor_id(), rw->lock);
 				stuck = INIT_STUCK;
 			}
-			barrier();
 		}
-		goto again;
-	}
-
-	if ( (rw)->lock & ~(1<<31)) /* someone has a read lock */
-	{
-		/* clear our write lock and wait for reads to go away */
-		clear_bit(31,&(rw)->lock);
-		while ( (rw)->lock & ~(1<<31) )
-		{
-			if(!--stuck)
-			{
-				printk("write_lock(%p) 2 CPU#%d lock %lx)\n",
-				       rw, cpu,rw->lock);
-				stuck = INIT_STUCK;
-			}
-			barrier();
-		}
-		goto again;
 	}
 	wmb();
 }
@@ -179,14 +169,8 @@
 
 int _raw_write_trylock(rwlock_t *rw)
 {
-	if (test_and_set_bit(31, &(rw)->lock)) /* someone has a write lock */
-		return 0;
-
-	if ((rw)->lock & ~(1<<31)) {	/* someone has a read lock */
-		/* clear our write lock and wait for reads to go away */
-		clear_bit(31,&(rw)->lock);
+	if (cmpxchg(&rw->lock, 0, -1) != 0)
 		return 0;
-	}
 	wmb();
 	return 1;
 }
@@ -194,12 +178,12 @@
 
 void _raw_write_unlock(rwlock_t *rw)
 {
-	if ( !(rw->lock & (1<<31)) )
-		printk("_write_lock(): %s/%d (nip %08lX) lock %lx\n",
+	if (rw->lock >= 0)
+		printk("_write_lock(): %s/%d (nip %08lX) lock %d\n",
 		      current->comm,current->pid,current->thread.regs->nip,
 		      rw->lock);
 	wmb();
-	clear_bit(31,&(rw)->lock);
+	rw->lock = 0;
 }
 EXPORT_SYMBOL(_raw_write_unlock);
 
diff -Nru a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
--- a/arch/ppc/platforms/4xx/Kconfig	2004-11-02 06:40:33 -08:00
+++ b/arch/ppc/platforms/4xx/Kconfig	2005-02-03 06:42:41 -08:00
@@ -73,6 +73,11 @@
 	help
 	  This option enables support for the IBM PPC440GP evaluation board.
 
+config LUAN
+	bool "Luan"
+	help
+	  This option enables support for the IBM PPC440SP evaluation board.
+
 config OCOTEA
 	bool "Ocotea"
 	help
@@ -103,9 +108,14 @@
 	depends on OCOTEA
 	default y
 
+config 440SP
+	bool
+	depends on LUAN
+	default y
+
 config 440
 	bool
-	depends on 440GP
+	depends on 440GP || 440SP
 	default y
 
 config 440A
@@ -132,7 +142,7 @@
 
 config IBM_OCP
 	bool
-	depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+	depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
 	default y
 
 config XILINX_OCP
@@ -142,7 +152,7 @@
 
 config IBM_EMAC4
 	bool
-	depends on 440GX
+	depends on 440GX || 440SP
 	default y
 
 config BIOS_FIXUP
diff -Nru a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
--- a/arch/ppc/platforms/4xx/Makefile	2004-10-18 22:26:40 -07:00
+++ b/arch/ppc/platforms/4xx/Makefile	2005-02-03 06:42:41 -08:00
@@ -6,6 +6,7 @@
 obj-$(CONFIG_EBONY)		+= ebony.o
 obj-$(CONFIG_EP405)		+= ep405.o
 obj-$(CONFIG_BUBINGA)		+= bubinga.o
+obj-$(CONFIG_LUAN)		+= luan.o
 obj-$(CONFIG_OAK)		+= oak.o
 obj-$(CONFIG_OCOTEA)		+= ocotea.o
 obj-$(CONFIG_REDWOOD_5)		+= redwood5.o
@@ -20,6 +21,7 @@
 obj-$(CONFIG_REDWOOD_6)		+= ibmstbx25.o
 obj-$(CONFIG_440GP)		+= ibm440gp.o
 obj-$(CONFIG_440GX)		+= ibm440gx.o
+obj-$(CONFIG_440SP)		+= ibm440sp.o
 obj-$(CONFIG_405EP)		+= ibm405ep.o
 obj-$(CONFIG_405GPR)		+= ibm405gpr.o
 obj-$(CONFIG_VIRTEX_II_PRO)	+= virtex-ii_pro.o
diff -Nru a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
--- a/arch/ppc/platforms/4xx/ebony.c	2005-01-03 15:49:19 -08:00
+++ b/arch/ppc/platforms/4xx/ebony.c	2005-02-03 06:42:41 -08:00
@@ -4,7 +4,7 @@
  * Ebony board specific routines
  *
  * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2004 MontaVista Software Inc.
+ * Copyright 2002-2005 MontaVista Software Inc.
  *
  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  * Copyright (c) 2003, 2004 Zultys Technologies
@@ -140,7 +140,7 @@
 {
 	void *pcix_reg_base;
 
-	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
+	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 
 	/* Disable all windows */
 	PCIX_WRITEL(0, PCIX0_POM0SA);
diff -Nru a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/4xx/ibm440sp.c	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,131 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440sp.c
+ *
+ * PPC440SP I/O descriptions
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ibm440sp.h>
+#include <asm/ocp.h>
+
+static struct ocp_func_emac_data ibm440sp_emac0_def = {
+	.rgmii_idx	= -1,		/* No RGMII */
+	.rgmii_mux	= -1,		/* No RGMII */
+	.zmii_idx       = -1,           /* No ZMII */
+	.zmii_mux       = -1,           /* No ZMII */
+	.mal_idx        = 0,            /* MAL device index */
+	.mal_rx_chan    = 0,            /* MAL rx channel number */
+	.mal_tx_chan    = 0,            /* MAL tx channel number */
+	.wol_irq        = 61,  		/* WOL interrupt number */
+	.mdio_idx       = -1,           /* No shared MDIO */
+	.tah_idx	= -1,		/* No TAH */
+	.jumbo		= 1,		/* Jumbo frames supported */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ibm440sp_mal0_def = {
+	.num_tx_chans   = 4,    	/* Number of TX channels */
+	.num_rx_chans   = 4,    	/* Number of RX channels */
+	.txeob_irq	= 38,		/* TX End Of Buffer IRQ  */
+	.rxeob_irq	= 39,		/* RX End Of Buffer IRQ  */
+	.txde_irq	= 34,		/* TX Descriptor Error IRQ */
+	.rxde_irq	= 35,		/* RX Descriptor Error IRQ */
+	.serr_irq	= 33,		/* MAL System Error IRQ    */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ibm440sp_iic0_def = {
+	.fast_mode	= 0,		/* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ibm440sp_iic1_def = {
+	.fast_mode	= 0,		/* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_OPB,
+	  .index	= 0,
+	  .paddr	= 0x0000000140000000ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 0,
+	  .paddr	= PPC440SP_UART0_ADDR,
+	  .irq		= UART0_INT,
+	  .pm		= IBM_CPM_UART0,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 1,
+	  .paddr	= PPC440SP_UART1_ADDR,
+	  .irq		= UART1_INT,
+	  .pm		= IBM_CPM_UART1,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 2,
+	  .paddr	= PPC440SP_UART2_ADDR,
+	  .irq		= UART2_INT,
+	  .pm		= IBM_CPM_UART2,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_IIC,
+	  .index	= 0,
+	  .paddr	= 0x00000001f0000400ULL,
+	  .irq		= 2,
+	  .pm		= IBM_CPM_IIC0,
+	  .additions	= &ibm440sp_iic0_def,
+	  .show		= &ocp_show_iic_data
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_IIC,
+	  .index	= 1,
+	  .paddr	= 0x00000001f0000500ULL,
+	  .irq		= 3,
+	  .pm		= IBM_CPM_IIC1,
+	  .additions	= &ibm440sp_iic1_def,
+	  .show		= &ocp_show_iic_data
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_GPIO,
+	  .index	= 0,
+	  .paddr	= 0x00000001f0000700ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= IBM_CPM_GPIO0,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_MAL,
+	  .paddr	= OCP_PADDR_NA,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	  .additions	= &ibm440sp_mal0_def,
+	  .show		= &ocp_show_mal_data,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_EMAC,
+	  .index	= 0,
+	  .paddr	= 0x00000001f0000800ULL,
+	  .irq		= 60,
+	  .pm		= OCP_CPM_NA,
+	  .additions	= &ibm440sp_emac0_def,
+	  .show		= &ocp_show_emac_data,
+	},
+	{ .vendor	= OCP_VENDOR_INVALID
+	}
+};
diff -Nru a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/4xx/ibm440sp.h	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,64 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440sp.h
+ *
+ * PPC440SP definitions
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * Copyright 2004-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_IBM440SP_H
+#define __PPC_PLATFORMS_IBM440SP_H
+
+#include <linux/config.h>
+
+#include <asm/ibm44x.h>
+
+/* UART */
+#define PPC440SP_UART0_ADDR	0x00000001f0000200ULL
+#define PPC440SP_UART1_ADDR	0x00000001f0000300ULL
+#define PPC440SP_UART2_ADDR	0x00000001f0000600ULL
+#define UART0_INT		0
+#define UART1_INT		1
+#define UART2_INT		2
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
+#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
+#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
+#define IBM_CPM_CPU		    0x02000000	/* processor core */
+#define IBM_CPM_DMA		    0x01000000	/* DMA controller */
+#define IBM_CPM_BGO		    0x00800000	/* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI		    0x00400000	/* OPB to PLB bridge */
+#define IBM_CPM_EBC		    0x00200000	/* External Bux Controller */
+#define IBM_CPM_EBM		    0x00100000	/* Ext Bus Master Interface */
+#define IBM_CPM_DMC		    0x00080000	/* SDRAM peripheral controller */
+#define IBM_CPM_PLB		    0x00040000	/* PLB bus arbiter */
+#define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
+#define IBM_CPM_PPM		    0x00002000	/* PLB Performance Monitor */
+#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
+#define IBM_CPM_GPT		    0x00000400	/* General Purpose Timers  */
+#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
+#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
+#define IBM_CPM_UART2		0x00000100	/* serial port 1 */
+#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
+#define IBM_CPM_EMAC0  		0x00000020	/* EMAC 0     */
+
+#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
+				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
+				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
+				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
+				| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
+				| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
+			  	| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
+#endif /* __PPC_PLATFORMS_IBM440SP_H */
+#endif /* __KERNEL__ */
diff -Nru a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/4xx/luan.c	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,387 @@
+/*
+ * arch/ppc/platforms/4xx/luan.c
+ *
+ * Luan board specific routines
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * Copyright 2004-2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/ibm44x_common.h>
+#include <syslib/ibm440gx_common.h>
+#include <syslib/ibm440sp_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the  standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+
+bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+static void __init
+luan_calibrate_decr(void)
+{
+	unsigned int freq;
+
+	if (mfspr(SPRN_CCR1) & CCR1_TCS)
+		freq = LUAN_TMR_CLK;
+	else
+		freq = clocks.cpu;
+
+	ibm44x_calibrate_decr(freq);
+}
+
+static int
+luan_show_cpuinfo(struct seq_file *m)
+{
+	seq_printf(m, "vendor\t\t: IBM\n");
+	seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
+
+	return 0;
+}
+
+static inline int
+luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
+
+	/* PCIX0 in adapter mode, no host interrupt routing */
+
+	/* PCIX1 */
+	if (hose->index == 0) {
+		static char pci_irq_table[][4] =
+		/*
+		 *	PCI IDSEL/INTPIN->INTLINE
+		 *	  A   B   C   D
+		 */
+		{
+			{ 49, 49, 49, 49 },	/* IDSEL 1 - PCIX1 Slot 0 */
+			{ 49, 49, 49, 49 },	/* IDSEL 2 - PCIX1 Slot 1 */
+			{ 49, 49, 49, 49 },	/* IDSEL 3 - PCIX1 Slot 2 */
+			{ 49, 49, 49, 49 },	/* IDSEL 4 - PCIX1 Slot 3 */
+		};
+		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+		return PCI_IRQ_TABLE_LOOKUP;
+	/* PCIX2 */
+	} else if (hose->index == 1) {
+		static char pci_irq_table[][4] =
+		/*
+		 *	PCI IDSEL/INTPIN->INTLINE
+		 *	  A   B   C   D
+		 */
+		{
+			{ 50, 50, 50, 50 },	/* IDSEL 1 - PCIX2 Slot 0 */
+			{ 50, 50, 50, 50 },	/* IDSEL 2 - PCIX2 Slot 1 */
+			{ 50, 50, 50, 50 },	/* IDSEL 3 - PCIX2 Slot 2 */
+			{ 50, 50, 50, 50 },	/* IDSEL 4 - PCIX2 Slot 3 */
+		};
+		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+		return PCI_IRQ_TABLE_LOOKUP;
+	}
+	return -1;
+}
+
+static void __init luan_set_emacdata(void)
+{
+	struct ocp_def *def;
+	struct ocp_func_emac_data *emacdata;
+
+	/* Set phy_map, phy_mode, and mac_addr for the EMAC */
+	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+	emacdata = def->additions;
+	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
+	emacdata->phy_mode = PHY_MODE_GMII;
+	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+}
+
+#define PCIX_READW(offset) \
+	(readw((void *)((u32)pcix_reg_base+offset)))
+
+#define PCIX_WRITEW(value, offset) \
+	(writew(value, (void *)((u32)pcix_reg_base+offset)))
+
+#define PCIX_WRITEL(value, offset) \
+	(writel(value, (void *)((u32)pcix_reg_base+offset)))
+
+static void __init
+luan_setup_pcix(void)
+{
+	int i;
+	void *pcix_reg_base;
+
+	for (i=0;i<3;i++) {
+		pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
+
+		/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
+		PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
+
+		/* Disable all windows */
+		PCIX_WRITEL(0, PCIX0_POM0SA);
+		PCIX_WRITEL(0, PCIX0_POM1SA);
+		PCIX_WRITEL(0, PCIX0_POM2SA);
+		PCIX_WRITEL(0, PCIX0_PIM0SA);
+		PCIX_WRITEL(0, PCIX0_PIM0SAH);
+		PCIX_WRITEL(0, PCIX0_PIM1SA);
+		PCIX_WRITEL(0, PCIX0_PIM2SA);
+		PCIX_WRITEL(0, PCIX0_PIM2SAH);
+
+		/*
+		 * Setup 512MB PLB->PCI outbound mem window
+		 * (a_n000_0000->0_n000_0000)
+		 * */
+		PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
+		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
+		PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
+		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
+		PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
+
+		/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
+		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
+		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
+		PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
+		PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
+
+		iounmap(pcix_reg_base);
+	}
+
+	eieio();
+}
+
+static void __init
+luan_setup_hose(struct pci_controller *hose,
+		int lower_mem,
+		int upper_mem,
+		int cfga,
+		int cfgd,
+		u64 pcix_io_base)
+{
+	char name[20];
+
+	sprintf(name, "PCIX%d host bridge", hose->index);
+
+	hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
+
+	pci_init_resource(&hose->io_resource,
+			LUAN_PCIX_LOWER_IO,
+			LUAN_PCIX_UPPER_IO,
+			IORESOURCE_IO,
+			name);
+
+	pci_init_resource(&hose->mem_resources[0],
+			lower_mem,
+			upper_mem,
+			IORESOURCE_MEM,
+			name);
+
+	hose->io_space.start = LUAN_PCIX_LOWER_IO;
+	hose->io_space.end = LUAN_PCIX_UPPER_IO;
+	hose->mem_space.start = lower_mem;
+	hose->mem_space.end = upper_mem;
+	isa_io_base =
+		(unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
+	hose->io_base_virt = (void *)isa_io_base;
+
+	setup_indirect_pci(hose, cfga, cfgd);
+	hose->set_cfg_type = 1;
+}
+
+static void __init
+luan_setup_hoses(void)
+{
+	struct pci_controller *hose1, *hose2;
+
+	/* Configure windows on the PCI-X host bridge */
+	luan_setup_pcix();
+
+	/* Allocate hoses for PCIX1 and PCIX2 */
+	hose1 = pcibios_alloc_controller();
+	hose2 = pcibios_alloc_controller();
+	if (!hose1 || !hose2)
+		return;
+
+	/* Setup PCIX1 */
+	hose1->first_busno = 0;
+	hose1->last_busno = 0xff;
+
+	luan_setup_hose(hose1,
+			LUAN_PCIX1_LOWER_MEM,
+			LUAN_PCIX1_UPPER_MEM,
+			PCIX1_CFGA,
+			PCIX1_CFGD,
+			PCIX1_IO_BASE);
+
+	hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
+
+	/* Setup PCIX2 */
+	hose2->first_busno = hose1->last_busno + 1;
+	hose2->last_busno = 0xff;
+
+	luan_setup_hose(hose2,
+			LUAN_PCIX2_LOWER_MEM,
+			LUAN_PCIX2_UPPER_MEM,
+			PCIX2_CFGA,
+			PCIX2_CFGD,
+			PCIX2_IO_BASE);
+
+	hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
+
+	ppc_md.pci_swizzle = common_swizzle;
+	ppc_md.pci_map_irq = luan_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+luan_early_serial_map(void)
+{
+	struct uart_port port;
+
+	/* Setup ioremapped serial port access */
+	memset(&port, 0, sizeof(port));
+	port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
+	port.irq = UART0_INT;
+	port.uartclk = clocks.uart0;
+	port.regshift = 0;
+	port.iotype = SERIAL_IO_MEM;
+	port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+	port.line = 0;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 0 failed\n");
+	}
+
+	port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
+	port.irq = UART1_INT;
+	port.uartclk = clocks.uart1;
+	port.line = 1;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 1 failed\n");
+	}
+
+	port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
+	port.irq = UART2_INT;
+	port.uartclk = BASE_BAUD;
+	port.line = 2;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 2 failed\n");
+	}
+}
+
+static void __init
+luan_setup_arch(void)
+{
+	luan_set_emacdata();
+
+#if !defined(CONFIG_BDI_SWITCH)
+	/*
+	 * The Abatron BDI JTAG debugger does not tolerate others
+	 * mucking with the debug registers.
+	 */
+        mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
+#endif
+
+	/*
+	 * Determine various clocks.
+	 * To be completely correct we should get SysClk
+	 * from FPGA, because it can be changed by on-board switches
+	 * --ebs
+	 */
+	/* 440GX and 440SP clocking is the same -mdp */
+	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+	ocp_sys_info.opb_bus_freq = clocks.opb;
+
+	/* init to some ~sane value until calibrate_delay() runs */
+        loops_per_jiffy = 50000000/HZ;
+
+	/* Setup PCIXn host bridges */
+	luan_setup_hoses();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	if (initrd_start)
+		ROOT_DEV = Root_RAM0;
+	else
+#endif
+#ifdef CONFIG_ROOT_NFS
+		ROOT_DEV = Root_NFS;
+#else
+		ROOT_DEV = Root_HDA1;
+#endif
+
+	luan_early_serial_map();
+
+	/* Identify the system */
+	printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+		unsigned long r5, unsigned long r6, unsigned long r7)
+{
+	parse_bootinfo(find_bootinfo());
+
+	/*
+	 * If we were passed in a board information, copy it into the
+	 * residual data area.
+	 */
+	if (r3)
+		__res = *(bd_t *)(r3 + KERNELBASE);
+
+	ibm44x_platform_init();
+
+	ppc_md.setup_arch = luan_setup_arch;
+	ppc_md.show_cpuinfo = luan_show_cpuinfo;
+	ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
+	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
+
+	ppc_md.calibrate_decr = luan_calibrate_decr;
+#ifdef CONFIG_KGDB
+	ppc_md.early_serial_map = luan_early_serial_map;
+#endif
+}
diff -Nru a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/4xx/luan.h	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,80 @@
+/*
+ * arch/ppc/platforms/4xx/luan.h
+ *
+ * Luan board definitions
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * Copyright 2004-2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_LUAN_H__
+#define __ASM_LUAN_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ibm440sp.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0	0xa0000800
+
+/* Location of MAC addresses in PIBS image */
+#define PIBS_FLASH_BASE		0xffe00000
+#define PIBS_MAC_BASE		(PIBS_FLASH_BASE+0x1b0400)
+
+/* External timer clock frequency */
+#define LUAN_TMR_CLK		25000000
+
+/* Flash */
+#define LUAN_FPGA_REG_0			0x0000000148300000ULL
+#define LUAN_BOOT_LARGE_FLASH(x)	(x & 0x40)
+#define LUAN_SMALL_FLASH_LOW		0x00000001ff900000ULL
+#define LUAN_SMALL_FLASH_HIGH		0x00000001ffe00000ULL
+#define LUAN_SMALL_FLASH_SIZE		0x100000
+#define LUAN_LARGE_FLASH_LOW		0x00000001ff800000ULL
+#define LUAN_LARGE_FLASH_HIGH		0x00000001ffc00000ULL
+#define LUAN_LARGE_FLASH_SIZE		0x400000
+
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE	3
+
+/* PIBS defined UART mappings, used before early_serial_setup */
+#define UART0_IO_BASE	(u8 *) 0xa0000200
+#define UART1_IO_BASE	(u8 *) 0xa0000300
+#define UART2_IO_BASE	(u8 *) 0xa0000600
+
+#define BASE_BAUD	11059200
+#define STD_UART_OP(num)					\
+	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
+		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
+		iomem_base: UART##num##_IO_BASE,		\
+		io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS	\
+	STD_UART_OP(0)		\
+	STD_UART_OP(1)		\
+	STD_UART_OP(2)
+
+/* PCI support */
+#define LUAN_PCIX_LOWER_IO	0x00000000
+#define LUAN_PCIX_UPPER_IO	0x0000ffff
+#define LUAN_PCIX0_LOWER_MEM	0x80000000
+#define LUAN_PCIX0_UPPER_MEM	0x9fffffff
+#define LUAN_PCIX1_LOWER_MEM	0xa0000000
+#define LUAN_PCIX1_UPPER_MEM	0xbfffffff
+#define LUAN_PCIX2_LOWER_MEM	0xc0000000
+#define LUAN_PCIX2_UPPER_MEM	0xdfffffff
+
+#define LUAN_PCIX_MEM_SIZE	0x20000000
+#define LUAN_PCIX_MEM_OFFSET	0x00000000
+
+#endif				/* __ASM_LUAN_H__ */
+#endif				/* __KERNEL__ */
diff -Nru a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
--- a/arch/ppc/platforms/4xx/ocotea.c	2005-01-03 15:49:19 -08:00
+++ b/arch/ppc/platforms/4xx/ocotea.c	2005-02-03 06:42:41 -08:00
@@ -5,7 +5,7 @@
  *
  * Matt Porter <mporter@kernel.crashing.org>
  *
- * Copyright 2003-2004 MontaVista Software Inc.
+ * Copyright 2003-2005 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -163,7 +163,7 @@
 {
 	void *pcix_reg_base;
 
-	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
+	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 
 	/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 	PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
diff -Nru a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
--- a/arch/ppc/platforms/4xx/ocotea.h	2004-10-05 23:05:22 -07:00
+++ b/arch/ppc/platforms/4xx/ocotea.h	2005-02-03 06:42:41 -08:00
@@ -3,9 +3,9 @@
  *
  * Ocotea board definitions
  *
- * Matt Porter <mporter@mvista.com>
+ * Matt Porter <mporter@kernel.crashing.org>
  *
- * Copyright 2003 MontaVista Software Inc.
+ * Copyright 2003-2005 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -22,13 +22,13 @@
 #include <platforms/4xx/ibm440gx.h>
 
 /* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0	0xE0000800
+#define PPC44x_EMAC0_MR0	0xe0000800
 
 /* Location of MAC addresses in PIBS image */
-#define OCOTEA_PIBS_FLASH	0xfff00000
-#define OCOTEA_PIBS_MAC_BASE	(OCOTEA_PIBS_FLASH+0xb0500)
-#define OCOTEA_PIBS_MAC_SIZE	0x200
-#define OCOTEA_PIBS_MAC_OFFSET	0x100
+#define PIBS_FLASH_BASE		0xfff00000
+#define PIBS_MAC_BASE		(PIBS_FLASH_BASE+0xb0500)
+#define PIBS_MAC_SIZE		0x200
+#define PIBS_MAC_OFFSET		0x100
 
 /* External timer clock frequency */
 #define OCOTEA_TMR_CLK	25000000
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile	2005-01-20 20:56:31 -08:00
+++ b/arch/ppc/syslib/Makefile	2005-02-03 06:42:41 -08:00
@@ -13,6 +13,7 @@
 obj-$(CONFIG_44x)		+= ibm44x_common.o
 obj-$(CONFIG_440GP)		+= ibm440gp_common.o
 obj-$(CONFIG_440GX)		+= ibm440gx_common.o
+obj-$(CONFIG_440SP)		+= ibm440gx_common.o ibm440sp_common.o
 ifeq ($(CONFIG_4xx),y)
 ifeq ($(CONFIG_VIRTEX_II_PRO),y)
 obj-$(CONFIG_40x)		+= xilinx_pic.o
@@ -52,6 +53,7 @@
 obj-$(CONFIG_K2)		+= i8259.o indirect_pci.o todc_time.o \
 					pci_auto.o
 obj-$(CONFIG_LOPEC)		+= i8259.o pci_auto.o todc_time.o
+obj-$(CONFIG_LUAN)		+= indirect_pci.o pci_auto.o todc_time.o
 obj-$(CONFIG_KATANA)		+= pci_auto.o
 obj-$(CONFIG_MCPN765)		+= todc_time.o indirect_pci.o pci_auto.o \
 					open_pic.o i8259.o hawk_common.o
diff -Nru a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/ibm440sp_common.c	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,71 @@
+/*
+ * arch/ppc/syslib/ibm440sp_common.c
+ *
+ * PPC440SP system library
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+
+#include <asm/param.h>
+#include <asm/ibm44x.h>
+#include <asm/mmu.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+#include <asm/ppc4xx_pic.h>
+
+/*
+ * Read the 440SP memory controller to get size of system memory.
+ */
+unsigned long __init ibm440sp_find_end_of_memory(void)
+{
+	u32 i;
+	u32 mem_size = 0;
+
+	/* Read two bank sizes and sum */
+	for (i=0; i<2; i++)
+		switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) {
+			case MQ0_CONFIG_SIZE_8M:
+				mem_size += PPC44x_MEM_SIZE_8M;
+				break;
+			case MQ0_CONFIG_SIZE_16M:
+				mem_size += PPC44x_MEM_SIZE_16M;
+				break;
+			case MQ0_CONFIG_SIZE_32M:
+				mem_size += PPC44x_MEM_SIZE_32M;
+				break;
+			case MQ0_CONFIG_SIZE_64M:
+				mem_size += PPC44x_MEM_SIZE_64M;
+				break;
+			case MQ0_CONFIG_SIZE_128M:
+				mem_size += PPC44x_MEM_SIZE_128M;
+				break;
+			case MQ0_CONFIG_SIZE_256M:
+				mem_size += PPC44x_MEM_SIZE_256M;
+				break;
+			case MQ0_CONFIG_SIZE_512M:
+				mem_size += PPC44x_MEM_SIZE_512M;
+				break;
+			case MQ0_CONFIG_SIZE_1G:
+				mem_size += PPC44x_MEM_SIZE_1G;
+				break;
+			case MQ0_CONFIG_SIZE_2G:
+				mem_size += PPC44x_MEM_SIZE_2G;
+				break;
+			default:
+				break;
+		}
+	return mem_size;
+}
diff -Nru a/arch/ppc/syslib/ibm440sp_common.h b/arch/ppc/syslib/ibm440sp_common.h
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/ibm440sp_common.h	2005-02-03 06:42:41 -08:00
@@ -0,0 +1,25 @@
+/*
+ * arch/ppc/syslib/ibm440sp_common.h
+ *
+ * PPC440SP system library
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2004-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __PPC_SYSLIB_IBM440SP_COMMON_H
+#define __PPC_SYSLIB_IBM440SP_COMMON_H
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long __init ibm440sp_find_end_of_memory(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __PPC_SYSLIB_IBM440SP_COMMON_H */
+#endif /* __KERNEL__ */
diff -Nru a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c
--- a/arch/ppc/syslib/ibm44x_common.c	2005-01-30 22:22:38 -08:00
+++ b/arch/ppc/syslib/ibm44x_common.c	2005-02-03 06:42:41 -08:00
@@ -4,7 +4,7 @@
  * PPC44x system library
  *
  * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2004 MontaVista Software Inc.
+ * Copyright 2002-2005 MontaVista Software Inc.
  *
  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  * Copyright (c) 2003, 2004 Zultys Technologies
@@ -39,11 +39,17 @@
 	 * address in the 440's 36-bit address space.  Fix
 	 * them up with the appropriate ERPN
 	 */
-	if ((addr >= PPC44x_IO_LO) && (addr < PPC44x_IO_HI))
+	if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
 		page_4gb = PPC44x_IO_PAGE;
-	else if ((addr >= PPC44x_PCICFG_LO) && (addr < PPC44x_PCICFG_HI))
+	else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
 		page_4gb = PPC44x_PCICFG_PAGE;
-	else if ((addr >= PPC44x_PCIMEM_LO) && (addr < PPC44x_PCIMEM_HI))
+#ifdef CONFIG_440SP
+	else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
+		page_4gb = PPC44x_PCICFG_PAGE;
+	else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
+		page_4gb = PPC44x_PCICFG_PAGE;
+#endif
+	else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
 		page_4gb = PPC44x_PCIMEM_PAGE;
 
 	return (page_4gb | addr);
diff -Nru a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
--- a/arch/ppc/syslib/mv64x60.c	2005-01-30 22:22:37 -08:00
+++ b/arch/ppc/syslib/mv64x60.c	2005-02-03 06:42:42 -08:00
@@ -32,7 +32,7 @@
 
 
 u8		mv64x60_pci_exclude_bridge = 1;
-spinlock_t	mv64x60_lock; /* Only really used by PIC code once init done */
+spinlock_t	mv64x60_lock = SPIN_LOCK_UNLOCKED;
 
 static phys_addr_t 	mv64x60_bridge_pbase = 0;
 static void 		*mv64x60_bridge_vbase = 0;
diff -Nru a/arch/ppc/syslib/ppc4xx_dma.c b/arch/ppc/syslib/ppc4xx_dma.c
--- a/arch/ppc/syslib/ppc4xx_dma.c	2005-01-07 21:44:28 -08:00
+++ b/arch/ppc/syslib/ppc4xx_dma.c	2005-02-03 06:42:41 -08:00
@@ -512,6 +512,8 @@
 		return DMA_STATUS_BAD_CHANNEL;
 	}
 
+	memcpy(p_dma_ch, &dma_channels[dmanr], sizeof (ppc_dma_ch_t));
+
 #if DCRN_POL > 0
 	polarity = mfdcr(DCRN_POL);
 #else
@@ -604,6 +606,84 @@
 	return (GET_DMA_PW(control));
 }
 
+/*
+ * Clears the channel status bits
+ */
+int
+ppc4xx_clr_dma_status(unsigned int dmanr)
+{
+	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
+		printk(KERN_ERR "ppc4xx_clr_dma_status: bad channel: %d\n", dmanr);
+		return DMA_STATUS_BAD_CHANNEL;
+	}
+	mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr);
+	return DMA_STATUS_GOOD;
+}
+
+/*
+ * Enables the burst on the channel (BTEN bit in the control/count register)
+ * Note:
+ * For scatter/gather dma, this function MUST be called before the
+ * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
+ * sgl list and used as each sgl element is added.
+ */
+int
+ppc4xx_enable_burst(unsigned int dmanr)
+{
+	unsigned int ctc;
+	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
+		printk(KERN_ERR "ppc4xx_enable_burst: bad channel: %d\n", dmanr);
+		return DMA_STATUS_BAD_CHANNEL;
+	}
+        ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) | DMA_CTC_BTEN;
+	mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
+	return DMA_STATUS_GOOD;
+}
+/*
+ * Disables the burst on the channel (BTEN bit in the control/count register)
+ * Note:
+ * For scatter/gather dma, this function MUST be called before the
+ * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
+ * sgl list and used as each sgl element is added.
+ */
+int
+ppc4xx_disable_burst(unsigned int dmanr)
+{
+	unsigned int ctc;
+	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
+		printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr);
+		return DMA_STATUS_BAD_CHANNEL;
+	}
+	ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN;
+	mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
+	return DMA_STATUS_GOOD;
+}
+/*
+ * Sets the burst size (number of peripheral widths) for the channel
+ * (BSIZ bits in the control/count register))
+ * must be one of:
+ *    DMA_CTC_BSIZ_2
+ *    DMA_CTC_BSIZ_4
+ *    DMA_CTC_BSIZ_8
+ *    DMA_CTC_BSIZ_16
+ * Note:
+ * For scatter/gather dma, this function MUST be called before the
+ * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
+ * sgl list and used as each sgl element is added.
+ */
+int
+ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize)
+{
+	unsigned int ctc;
+	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
+		printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr);
+		return DMA_STATUS_BAD_CHANNEL;
+	}
+	ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK;
+	ctc |= (bsize & DMA_CTC_BSIZ_MSK);
+	mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
+	return DMA_STATUS_GOOD;
+}
 
 EXPORT_SYMBOL(ppc4xx_init_dma_channel);
 EXPORT_SYMBOL(ppc4xx_get_channel_config);
@@ -622,3 +702,7 @@
 EXPORT_SYMBOL(ppc4xx_enable_dma_interrupt);
 EXPORT_SYMBOL(ppc4xx_disable_dma_interrupt);
 EXPORT_SYMBOL(ppc4xx_get_dma_status);
+EXPORT_SYMBOL(ppc4xx_clr_dma_status);
+EXPORT_SYMBOL(ppc4xx_enable_burst);
+EXPORT_SYMBOL(ppc4xx_disable_burst);
+EXPORT_SYMBOL(ppc4xx_set_burst_size);
diff -Nru a/arch/ppc/syslib/ppc4xx_sgdma.c b/arch/ppc/syslib/ppc4xx_sgdma.c
--- a/arch/ppc/syslib/ppc4xx_sgdma.c	2004-08-07 15:02:29 -07:00
+++ b/arch/ppc/syslib/ppc4xx_sgdma.c	2005-02-03 06:42:41 -08:00
@@ -120,6 +120,12 @@
 		psgl->ptail = psgl->phead;
 		psgl->ptail_dma = psgl->phead_dma;
 	} else {
+		if(p_dma_ch->int_on_final_sg) {
+			/* mask out all dma interrupts, except error, on tail
+			before adding new tail. */
+			psgl->ptail->control_count &=
+				~(SG_TCI_ENABLE | SG_ETI_ENABLE);
+		}
 		psgl->ptail->next = psgl->ptail_dma + sizeof(ppc_sgl_t);
 		psgl->ptail++;
 		psgl->ptail_dma += sizeof(ppc_sgl_t);
@@ -217,7 +223,7 @@
 	}
 
 	sgl_addr = (ppc_sgl_t *) __va(mfdcr(DCRN_ASG0 + (psgl->dmanr * 0x8)));
-	count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8));
+	count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8)) & SG_COUNT_MASK;
 
 	if (!sgl_addr) {
 		printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n");
@@ -351,10 +357,11 @@
 int
 ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
 {
-	sgl_list_info_t *psgl;
+	sgl_list_info_t *psgl=NULL;
 	dma_addr_t dma_addr;
 	ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
 	uint32_t sg_command;
+	uint32_t ctc_settings;
 	void *ret;
 
 	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
@@ -411,6 +418,11 @@
 	/* Enable SGL control access */
 	mtdcr(DCRN_ASGC, sg_command);
 	psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
+
+	/* keep control count register settings */
+	ctc_settings = mfdcr(DCRN_DMACT0 + (dmanr * 0x8))
+		& (DMA_CTC_BSIZ_MSK | DMA_CTC_BTEN); /*burst mode settings*/
+	psgl->sgl_control |= ctc_settings;
 
 	if (p_dma_ch->int_enable) {
 		if (p_dma_ch->tce_enable)
diff -Nru a/arch/ppc64/kernel/entry.S b/arch/ppc64/kernel/entry.S
--- a/arch/ppc64/kernel/entry.S	2005-01-25 13:50:15 -08:00
+++ b/arch/ppc64/kernel/entry.S	2005-02-04 17:23:05 -08:00
@@ -231,6 +231,7 @@
 syscall_exit_trace:
 	std	r3,GPR3(r1)
 	bl	.save_nvgprs
+	addi	r3,r1,STACK_FRAME_OVERHEAD
 	bl	.do_syscall_trace_leave
 	REST_NVGPRS(r1)
 	ld	r3,GPR3(r1)
@@ -324,6 +325,7 @@
 	ld	r4,TI_FLAGS(r4)
 	andi.	r4,r4,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
 	beq+	81f
+	addi	r3,r1,STACK_FRAME_OVERHEAD
 	bl	.do_syscall_trace_leave
 81:	b	.ret_from_except
 
diff -Nru a/arch/ppc64/kernel/ptrace.c b/arch/ppc64/kernel/ptrace.c
--- a/arch/ppc64/kernel/ptrace.c	2004-12-17 00:09:09 -08:00
+++ b/arch/ppc64/kernel/ptrace.c	2005-02-04 17:23:05 -08:00
@@ -313,10 +313,10 @@
 		do_syscall_trace();
 }
 
-void do_syscall_trace_leave(void)
+void do_syscall_trace_leave(struct pt_regs *regs)
 {
 	if (unlikely(current->audit_context))
-		audit_syscall_exit(current, 0);	/* FIXME: pass pt_regs */
+		audit_syscall_exit(current, regs->result);
 
 	if ((test_thread_flag(TIF_SYSCALL_TRACE)
 	     || test_thread_flag(TIF_SINGLESTEP))
diff -Nru a/arch/ppc64/kernel/sysfs.c b/arch/ppc64/kernel/sysfs.c
--- a/arch/ppc64/kernel/sysfs.c	2005-01-04 18:48:02 -08:00
+++ b/arch/ppc64/kernel/sysfs.c	2005-02-04 17:23:05 -08:00
@@ -387,7 +387,7 @@
 {
 	struct cpu *cpu = container_of(dev, struct cpu, sysdev);
 
-	return sprintf(buf, "%u\n", get_hard_smp_processor_id(cpu->sysdev.id));
+	return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->sysdev.id));
 }
 static SYSDEV_ATTR(physical_id, 0444, show_physical_id, NULL);
 
diff -Nru a/arch/s390/defconfig b/arch/s390/defconfig
--- a/arch/s390/defconfig	2005-01-15 14:01:57 -08:00
+++ b/arch/s390/defconfig	2005-02-03 06:42:42 -08:00
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc1
-# Fri Jan 14 14:56:51 2005
+# Linux kernel version: 2.6.11-rc2
+# Mon Jan 31 16:27:12 2005
 #
 CONFIG_MMU=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -156,6 +156,7 @@
 #
 # Block devices
 #
+# CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 CONFIG_BLK_DEV_NBD=m
@@ -579,5 +580,5 @@
 # Library routines
 #
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC32 is not set
+CONFIG_CRC32=m
 # CONFIG_LIBCRC32C is not set
diff -Nru a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
--- a/arch/s390/kernel/compat_linux.c	2005-01-25 13:50:22 -08:00
+++ b/arch/s390/kernel/compat_linux.c	2005-02-03 06:42:43 -08:00
@@ -355,136 +355,6 @@
 		return sys_ftruncate(fd, (high << 32) | low);
 }
 
-/* readdir & getdents */
-
-#define NAME_OFFSET(de) ((int) ((de)->d_name - (char *) (de)))
-#define ROUND_UP(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1))
-
-struct old_linux_dirent32 {
-	u32		d_ino;
-	u32		d_offset;
-	unsigned short	d_namlen;
-	char		d_name[1];
-};
-
-struct readdir_callback32 {
-	struct old_linux_dirent32 * dirent;
-	int count;
-};
-
-static int fillonedir(void * __buf, const char * name, int namlen,
-		      loff_t offset, ino_t ino, unsigned int d_type)
-{
-	struct readdir_callback32 * buf = (struct readdir_callback32 *) __buf;
-	struct old_linux_dirent32 * dirent;
-
-	if (buf->count)
-		return -EINVAL;
-	buf->count++;
-	dirent = buf->dirent;
-	put_user(ino, &dirent->d_ino);
-	put_user(offset, &dirent->d_offset);
-	put_user(namlen, &dirent->d_namlen);
-	copy_to_user(dirent->d_name, name, namlen);
-	put_user(0, dirent->d_name + namlen);
-	return 0;
-}
-
-asmlinkage long old32_readdir(unsigned int fd, struct old_linux_dirent32 *dirent, unsigned int count)
-{
-	int error = -EBADF;
-	struct file * file;
-	struct readdir_callback32 buf;
-
-	file = fget(fd);
-	if (!file)
-		goto out;
-
-	buf.count = 0;
-	buf.dirent = dirent;
-
-	error = vfs_readdir(file, fillonedir, &buf);
-	if (error < 0)
-		goto out_putf;
-	error = buf.count;
-
-out_putf:
-	fput(file);
-out:
-	return error;
-}
-
-struct linux_dirent32 {
-	u32		d_ino;
-	u32		d_off;
-	unsigned short	d_reclen;
-	char		d_name[1];
-};
-
-struct getdents_callback32 {
-	struct linux_dirent32 * current_dir;
-	struct linux_dirent32 * previous;
-	int count;
-	int error;
-};
-
-static int filldir(void * __buf, const char * name, int namlen, loff_t offset, ino_t ino,
-		   unsigned int d_type)
-{
-	struct linux_dirent32 * dirent;
-	struct getdents_callback32 * buf = (struct getdents_callback32 *) __buf;
-	int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
-
-	buf->error = -EINVAL;	/* only used if we fail.. */
-	if (reclen > buf->count)
-		return -EINVAL;
-	dirent = buf->previous;
-	if (dirent)
-		put_user(offset, &dirent->d_off);
-	dirent = buf->current_dir;
-	buf->previous = dirent;
-	put_user(ino, &dirent->d_ino);
-	put_user(reclen, &dirent->d_reclen);
-	copy_to_user(dirent->d_name, name, namlen);
-	put_user(0, dirent->d_name + namlen);
-	buf->current_dir = ((void *)dirent) + reclen;
-	buf->count -= reclen;
-	return 0;
-}
-
-asmlinkage long sys32_getdents(unsigned int fd, struct linux_dirent32 *dirent, unsigned int count)
-{
-	struct file * file;
-	struct linux_dirent32 * lastdirent;
-	struct getdents_callback32 buf;
-	int error = -EBADF;
-
-	file = fget(fd);
-	if (!file)
-		goto out;
-
-	buf.current_dir = dirent;
-	buf.previous = NULL;
-	buf.count = count;
-	buf.error = 0;
-
-	error = vfs_readdir(file, filldir, &buf);
-	if (error < 0)
-		goto out_putf;
-	lastdirent = buf.previous;
-	error = buf.error;
-	if(lastdirent) {
-		put_user(file->f_pos, &lastdirent->d_off);
-		error = count - buf.count;
-	}
-out_putf:
-	fput(file);
-out:
-	return error;
-}
-
-/* end of readdir & getdents */
-
 int cp_compat_stat(struct kstat *stat, struct compat_stat *statbuf)
 {
 	int err;
diff -Nru a/arch/s390/kernel/compat_linux.h b/arch/s390/kernel/compat_linux.h
--- a/arch/s390/kernel/compat_linux.h	2005-01-04 18:48:19 -08:00
+++ b/arch/s390/kernel/compat_linux.h	2005-02-03 06:42:43 -08:00
@@ -50,9 +50,10 @@
 
 		/* POSIX.1b timers */
 		struct {
-			unsigned int	_timer1;
-			unsigned int	_timer2;
-                
+			timer_t _tid;		/* timer id */
+			int _overrun;		/* overrun count */
+			sigval_t _sigval;	/* same as below */
+			int _sys_private;       /* not to be passed to user */
 		} _timer;
 
 		/* POSIX.1b signals */
@@ -98,6 +99,8 @@
 #define si_addr		_sifields._sigfault._addr
 #define si_band		_sifields._sigpoll._band
 #define si_fd		_sifields._sigpoll._fd    
+#define si_tid		_sifields._timer._tid
+#define si_overrun	_sifields._timer._overrun
 
 /* asm/sigcontext.h */
 typedef union
diff -Nru a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
--- a/arch/s390/kernel/compat_signal.c	2005-01-04 18:48:19 -08:00
+++ b/arch/s390/kernel/compat_signal.c	2005-02-03 06:42:43 -08:00
@@ -95,10 +95,14 @@
 					  &to->si_addr);
 			break;
 		case __SI_POLL >> 16:
-		case __SI_TIMER >> 16:
 			err |= __put_user(from->si_band, &to->si_band);
 			err |= __put_user(from->si_fd, &to->si_fd);
 			break;
+		case __SI_TIMER >> 16:
+			err |= __put_user(from->si_tid, &to->si_tid);
+			err |= __put_user(from->si_overrun, &to->si_overrun);
+			err |= __put_user(from->si_int, &to->si_int);
+			break;
 		default:
 			break;
 		}
@@ -142,9 +146,13 @@
 			to->si_addr = (void *)(u64) (tmp & PSW32_ADDR_INSN);
 			break;
 		case __SI_POLL >> 16:
-		case __SI_TIMER >> 16:
 			err |= __get_user(to->si_band, &from->si_band);
 			err |= __get_user(to->si_fd, &from->si_fd);
+			break;
+		case __SI_TIMER >> 16:
+			err |= __get_user(to->si_tid, &from->si_tid);
+			err |= __get_user(to->si_overrun, &from->si_overrun);
+			err |= __get_user(to->si_int, &from->si_int);
 			break;
 		default:
 			break;
diff -Nru a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
--- a/arch/s390/kernel/compat_wrapper.S	2005-01-14 11:56:05 -08:00
+++ b/arch/s390/kernel/compat_wrapper.S	2005-02-03 06:42:43 -08:00
@@ -391,7 +391,7 @@
 	llgfr	%r2,%r2			# unsigned int
 	llgtr	%r3,%r3			# void *
 	llgfr	%r4,%r4			# unsigned int
-	jg	old32_readdir		# branch to system call
+	jg	compat_sys_old_readdir	# branch to system call
 
 	.globl  old32_mmap_wrapper 
 old32_mmap_wrapper:
@@ -639,7 +639,7 @@
 	llgfr	%r2,%r2			# unsigned int
 	llgtr	%r3,%r3			# void *
 	llgfr	%r4,%r4			# unsigned int
-	jg	sys32_getdents		# branch to system call
+	jg	compat_sys_getdents	# branch to system call
 
 	.globl  compat_sys_select_wrapper
 compat_sys_select_wrapper:
diff -Nru a/arch/s390/kernel/cpcmd.c b/arch/s390/kernel/cpcmd.c
--- a/arch/s390/kernel/cpcmd.c	2005-01-20 21:02:10 -08:00
+++ b/arch/s390/kernel/cpcmd.c	2005-02-03 06:42:42 -08:00
@@ -4,34 +4,41 @@
  *  S390 version
  *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Christian Borntraeger (cborntra@de.ibm.com),
  */
 
-#include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/stddef.h>
 #include <linux/string.h>
 #include <asm/ebcdic.h>
-#include <linux/spinlock.h>
 #include <asm/cpcmd.h>
 #include <asm/system.h>
 
 static DEFINE_SPINLOCK(cpcmd_lock);
 static char cpcmd_buf[240];
 
-void cpcmd(char *cmd, char *response, int rlen)
+/*
+ * the caller of __cpcmd has to ensure that the response buffer is below 2 GB
+ */
+void __cpcmd(char *cmd, char *response, int rlen)
 {
-        const int mask = 0x40000000L;
+	const int mask = 0x40000000L;
 	unsigned long flags;
-        int cmdlen;
+	int cmdlen;
 
 	spin_lock_irqsave(&cpcmd_lock, flags);
 	cmdlen = strlen(cmd);
-	BUG_ON(cmdlen>240);
+	BUG_ON(cmdlen > 240);
 	strcpy(cpcmd_buf, cmd);
 	ASCEBC(cpcmd_buf, cmdlen);
 
 	if (response != NULL && rlen > 0) {
+		memset(response, 0, rlen);
 #ifndef CONFIG_ARCH_S390X
-                asm volatile ("LRA   2,0(%0)\n\t"
+		asm volatile ("LRA   2,0(%0)\n\t"
                               "LR    4,%1\n\t"
                               "O     4,%4\n\t"
                               "LRA   3,0(%2)\n\t"
@@ -78,3 +85,27 @@
 	spin_unlock_irqrestore(&cpcmd_lock, flags);
 }
 
+EXPORT_SYMBOL(__cpcmd);
+
+#ifdef CONFIG_ARCH_S390X
+void cpcmd(char *cmd, char *response, int rlen)
+{
+	char *lowbuf;
+	if ((rlen == 0) || (response == NULL)
+	    || !((unsigned long)response >> 31))
+		__cpcmd(cmd, response, rlen);
+	else {
+		lowbuf = kmalloc(rlen, GFP_KERNEL | GFP_DMA);
+		if (!lowbuf) {
+			printk(KERN_WARNING
+				"cpcmd: could not allocate response buffer\n");
+			return;
+		}
+		__cpcmd(cmd, lowbuf, rlen);
+		memcpy(response, lowbuf, rlen);
+		kfree(lowbuf);
+	}
+}
+
+EXPORT_SYMBOL(cpcmd);
+#endif		/* CONFIG_ARCH_S390X */
diff -Nru a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
--- a/arch/s390/kernel/debug.c	2004-10-25 12:47:52 -07:00
+++ b/arch/s390/kernel/debug.c	2005-02-03 06:42:42 -08:00
@@ -931,7 +931,7 @@
 	int rc = 0;
 	int i;
 	unsigned long flags;
-	mode_t mode = S_IFREG;
+	mode_t mode = S_IFREG | S_IRUSR | S_IWUSR;
 	struct proc_dir_entry *pde;
 
 	if (!id)
diff -Nru a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
--- a/arch/s390/kernel/module.c	2004-05-14 19:00:18 -07:00
+++ b/arch/s390/kernel/module.c	2005-02-03 06:42:42 -08:00
@@ -396,8 +396,7 @@
 		    const Elf_Shdr *sechdrs,
 		    struct module *me)
 {
-	if (me->arch.syminfo)
-		vfree(me->arch.syminfo);
+	vfree(me->arch.syminfo);
 	return 0;
 }
 
diff -Nru a/arch/s390/kernel/s390_ksyms.c b/arch/s390/kernel/s390_ksyms.c
--- a/arch/s390/kernel/s390_ksyms.c	2004-10-09 14:13:56 -07:00
+++ b/arch/s390/kernel/s390_ksyms.c	2005-02-03 06:42:42 -08:00
@@ -63,4 +63,3 @@
 EXPORT_SYMBOL(console_devno);
 EXPORT_SYMBOL(console_irq);
 EXPORT_SYMBOL(sys_wait4);
-EXPORT_SYMBOL(cpcmd);
diff -Nru a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
--- a/arch/s390/kernel/setup.c	2005-01-30 22:20:14 -08:00
+++ b/arch/s390/kernel/setup.c	2005-02-03 06:42:42 -08:00
@@ -76,8 +76,15 @@
 
 static char command_line[COMMAND_LINE_SIZE] = { 0, };
 
-static struct resource code_resource = { "Kernel code", 0x100000, 0 };
-static struct resource data_resource = { "Kernel data", 0, 0 };
+static struct resource code_resource = {
+	.name  = "Kernel code",
+	.flags = IORESOURCE_BUSY | IORESOURCE_MEM,
+};
+
+static struct resource data_resource = {
+	.name = "Kernel data",
+	.flags = IORESOURCE_BUSY | IORESOURCE_MEM,
+};
 
 /*
  * cpu_init() initializes state that is per-CPU.
@@ -184,11 +191,11 @@
 	char *ptr;
 
         if (MACHINE_IS_VM) {
-		cpcmd("QUERY CONSOLE", query_buffer, 1024);
+		__cpcmd("QUERY CONSOLE", query_buffer, 1024);
 		console_devno = simple_strtoul(query_buffer + 5, NULL, 16);
 		ptr = strstr(query_buffer, "SUBCHANNEL =");
 		console_irq = simple_strtoul(ptr + 13, NULL, 16);
-		cpcmd("QUERY TERM", query_buffer, 1024);
+		__cpcmd("QUERY TERM", query_buffer, 1024);
 		ptr = strstr(query_buffer, "CONMODE");
 		/*
 		 * Set the conmode to 3215 so that the device recognition 
@@ -197,7 +204,7 @@
 		 * 3215 and the 3270 driver will try to access the console
 		 * device (3215 as console and 3270 as normal tty).
 		 */
-		cpcmd("TERM CONMODE 3215", NULL, 0);
+		__cpcmd("TERM CONMODE 3215", NULL, 0);
 		if (ptr == NULL) {
 #if defined(CONFIG_SCLP_CONSOLE)
 			SET_CONSOLE_SCLP;
@@ -314,7 +321,6 @@
         unsigned long bootmap_size;
         unsigned long memory_start, memory_end;
         char c = ' ', cn, *to = command_line, *from = COMMAND_LINE;
-	struct resource *res;
 	unsigned long start_pfn, end_pfn;
         static unsigned int smptrap=0;
         unsigned long delay = 0;
@@ -472,6 +478,30 @@
         }
 #endif
 
+	for (i = 0; i < 16 && memory_chunk[i].size > 0; i++) {
+		struct resource *res;
+
+		res = alloc_bootmem_low(sizeof(struct resource));
+		res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
+
+		switch (memory_chunk[i].type) {
+		case CHUNK_READ_WRITE:
+			res->name = "System RAM";
+			break;
+		case CHUNK_READ_ONLY:
+			res->name = "System ROM";
+			res->flags |= IORESOURCE_READONLY;
+			break;
+		default:
+			res->name = "reserved";
+		}
+		res->start = memory_chunk[i].addr;
+		res->end = memory_chunk[i].addr +  memory_chunk[i].size - 1;
+		request_resource(&iomem_resource, res);
+		request_resource(res, &code_resource);
+		request_resource(res, &data_resource);
+	}
+
         /*
          * Setup lowcore for boot cpu
          */
@@ -523,14 +553,6 @@
 	 * Create kernel page tables and switch to virtual addressing.
 	 */
         paging_init();
-
-	res = alloc_bootmem_low(sizeof(struct resource));
-	res->start = 0;
-	res->end = memory_end;
-	res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-	request_resource(&iomem_resource, res);
-	request_resource(res, &code_resource);
-	request_resource(res, &data_resource);
 
         /* Setup default console */
 	conmode_default();
diff -Nru a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c
--- a/arch/s390/mm/cmm.c	2005-01-15 14:01:57 -08:00
+++ b/arch/s390/mm/cmm.c	2005-02-03 06:42:42 -08:00
@@ -19,7 +19,6 @@
 
 #include <asm/pgalloc.h>
 #include <asm/uaccess.h>
-#include <asm/smp.h>
 
 #include "../../../drivers/s390/net/smsgiucv.h"
 
diff -Nru a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
--- a/arch/s390/mm/extmem.c	2005-01-30 22:33:46 -08:00
+++ b/arch/s390/mm/extmem.c	2005-02-03 06:42:42 -08:00
@@ -576,8 +576,8 @@
 			segtype_string[seg->range[i].start & 0xff]);
 	}
 	sprintf(cmd2, "SAVESEG %s", name);
-	cpcmd(cmd1, NULL, 80);
-	cpcmd(cmd2, NULL, 80);
+	cpcmd(cmd1, NULL, 0);
+	cpcmd(cmd2, NULL, 0);
 	spin_unlock(&dcss_lock);
 }
 
diff -Nru a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
--- a/arch/s390/mm/mmap.c	2004-10-18 22:26:36 -07:00
+++ b/arch/s390/mm/mmap.c	2005-02-03 06:42:42 -08:00
@@ -26,6 +26,7 @@
 
 #include <linux/personality.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 
 /*
  * Top of mmap area (just below the process stack).
@@ -81,3 +82,5 @@
 		mm->unmap_area = arch_unmap_area_topdown;
 	}
 }
+EXPORT_SYMBOL_GPL(arch_pick_mmap_layout);
+
diff -Nru a/arch/sparc64/defconfig b/arch/sparc64/defconfig
--- a/arch/sparc64/defconfig	2005-01-21 20:03:35 -08:00
+++ b/arch/sparc64/defconfig	2005-02-07 15:29:11 -08:00
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc1
-# Fri Jan 21 20:03:21 2005
+# Linux kernel version: 2.6.11-rc3
+# Mon Feb  7 15:29:00 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -845,6 +845,7 @@
 CONFIG_BT_HCIUART_BCSP=y
 CONFIG_BT_HCIUART_BCSP_TXCRC=y
 CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
 CONFIG_BT_HCIBFUSB=m
 CONFIG_BT_HCIVHCI=m
 CONFIG_NETDEVICES=y
@@ -1245,7 +1246,12 @@
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
+
+#
+# XFS support
+#
 CONFIG_XFS_FS=m
+CONFIG_XFS_EXPORT=y
 # CONFIG_XFS_RT is not set
 CONFIG_XFS_QUOTA=y
 CONFIG_XFS_SECURITY=y
@@ -1520,6 +1526,11 @@
 CONFIG_DVB_VES1820=m
 CONFIG_DVB_TDA10021=m
 CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terresterial DTV) frontends
+#
+CONFIG_DVB_NXT2002=m
 CONFIG_VIDEO_SAA7146=m
 CONFIG_VIDEO_SAA7146_VV=m
 CONFIG_VIDEO_VIDEOBUF=m
@@ -1527,6 +1538,7 @@
 CONFIG_VIDEO_BUF=m
 CONFIG_VIDEO_BTCX=m
 CONFIG_VIDEO_IR=m
+CONFIG_VIDEO_TVEEPROM=m
 
 #
 # Sound
diff -Nru a/arch/sparc64/kernel/binfmt_aout32.c b/arch/sparc64/kernel/binfmt_aout32.c
--- a/arch/sparc64/kernel/binfmt_aout32.c	2005-01-11 17:37:28 -08:00
+++ b/arch/sparc64/kernel/binfmt_aout32.c	2005-02-05 14:53:05 -08:00
@@ -333,9 +333,8 @@
 	current->mm->start_stack =
 		(unsigned long) create_aout32_tables((char __user *)bprm->p, bprm);
 	if (!(orig_thr_flags & _TIF_32BIT)) {
-		unsigned long pgd_cache;
+		unsigned long pgd_cache = get_pgd_cache(current->mm->pgd);
 
-		pgd_cache = ((unsigned long)current->mm->pgd[0])<<11UL;
 		__asm__ __volatile__("stxa\t%0, [%1] %2\n\t"
 				     "membar #Sync"
 				     : /* no outputs */
diff -Nru a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
--- a/arch/sparc64/kernel/process.c	2005-02-02 04:05:45 -08:00
+++ b/arch/sparc64/kernel/process.c	2005-02-05 14:53:05 -08:00
@@ -440,7 +440,7 @@
 				pmd_t *page = pmd_alloc_one(mm, 0);
 				pud_set(pud0, page);
 			}
-			pgd_cache = ((unsigned long) pud_val(*pud0)) << 11UL;
+			pgd_cache = get_pgd_cache(pgd0);
 		}
 		__asm__ __volatile__("stxa %0, [%1] %2\n\t"
 				     "membar #Sync"
diff -Nru a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
--- a/arch/sparc64/kernel/smp.c	2005-01-20 21:02:14 -08:00
+++ b/arch/sparc64/kernel/smp.c	2005-02-05 15:23:23 -08:00
@@ -894,9 +894,8 @@
 
 void smp_capture(void)
 {
-	int result = __atomic_add(1, &smp_capture_depth);
+	int result = atomic_add_ret(1, &smp_capture_depth);
 
-	membar("#StoreStore | #LoadStore");
 	if (result == 1) {
 		int ncpus = num_online_cpus();
 
diff -Nru a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
--- a/arch/sparc64/kernel/sparc64_ksyms.c	2005-02-02 04:05:45 -08:00
+++ b/arch/sparc64/kernel/sparc64_ksyms.c	2005-02-05 15:23:23 -08:00
@@ -172,18 +172,25 @@
 EXPORT_SYMBOL(up);
 
 /* Atomic counter implementation. */
-EXPORT_SYMBOL(__atomic_add);
-EXPORT_SYMBOL(__atomic_sub);
-EXPORT_SYMBOL(__atomic64_add);
-EXPORT_SYMBOL(__atomic64_sub);
+EXPORT_SYMBOL(atomic_add);
+EXPORT_SYMBOL(atomic_add_ret);
+EXPORT_SYMBOL(atomic_sub);
+EXPORT_SYMBOL(atomic_sub_ret);
+EXPORT_SYMBOL(atomic64_add);
+EXPORT_SYMBOL(atomic64_add_ret);
+EXPORT_SYMBOL(atomic64_sub);
+EXPORT_SYMBOL(atomic64_sub_ret);
 #ifdef CONFIG_SMP
 EXPORT_SYMBOL(_atomic_dec_and_lock);
 #endif
 
 /* Atomic bit operations. */
-EXPORT_SYMBOL(___test_and_set_bit);
-EXPORT_SYMBOL(___test_and_clear_bit);
-EXPORT_SYMBOL(___test_and_change_bit);
+EXPORT_SYMBOL(test_and_set_bit);
+EXPORT_SYMBOL(test_and_clear_bit);
+EXPORT_SYMBOL(test_and_change_bit);
+EXPORT_SYMBOL(set_bit);
+EXPORT_SYMBOL(clear_bit);
+EXPORT_SYMBOL(change_bit);
 
 /* Bit searching */
 EXPORT_SYMBOL(find_next_bit);
diff -Nru a/arch/sparc64/lib/atomic.S b/arch/sparc64/lib/atomic.S
--- a/arch/sparc64/lib/atomic.S	2005-02-01 12:21:18 -08:00
+++ b/arch/sparc64/lib/atomic.S	2005-02-05 15:23:23 -08:00
@@ -4,73 +4,136 @@
  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  */
 
+#include <linux/config.h>
 #include <asm/asi.h>
 
+	/* On SMP we need to use memory barriers to ensure
+	 * correct memory operation ordering, nop these out
+	 * for uniprocessor.
+	 */
+#ifdef CONFIG_SMP
+#define ATOMIC_PRE_BARRIER	membar #StoreLoad | #LoadLoad
+#define ATOMIC_POST_BARRIER	membar #StoreLoad | #StoreStore
+#else
+#define ATOMIC_PRE_BARRIER	nop
+#define ATOMIC_POST_BARRIER	nop
+#endif
+
 	.text
 
-	/* We use these stubs for the uncommon case
-	 * of contention on the atomic value.  This is
-	 * so that we can keep the main fast path 8
-	 * instructions long and thus fit into a single
-	 * L2 cache line.
+	/* Two versions of the atomic routines, one that
+	 * does not return a value and does not perform
+	 * memory barriers, and a second which returns
+	 * a value and does the barriers.
 	 */
-__atomic_add_membar:
-	ba,pt	%xcc, __atomic_add
-	 membar	#StoreLoad | #StoreStore
-
-__atomic_sub_membar:
-	ba,pt	%xcc, __atomic_sub
-	 membar	#StoreLoad | #StoreStore
-
-	.align	64
-	.globl	__atomic_add
-	.type	__atomic_add,#function
-__atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
-	lduw	[%o1], %g5
+	.globl	atomic_add
+	.type	atomic_add,#function
+atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
+1:	lduw	[%o1], %g5
+	add	%g5, %o0, %g7
+	cas	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%icc, 1b
+	 nop
+	retl
+	 nop
+	.size	atomic_add, .-atomic_add
+
+	.globl	atomic_sub
+	.type	atomic_sub,#function
+atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
+1:	lduw	[%o1], %g5
+	sub	%g5, %o0, %g7
+	cas	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%icc, 1b
+	 nop
+	retl
+	 nop
+	.size	atomic_sub, .-atomic_sub
+
+	.globl	atomic_add_ret
+	.type	atomic_add_ret,#function
+atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	lduw	[%o1], %g5
 	add	%g5, %o0, %g7
 	cas	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%icc, __atomic_add_membar
+	bne,pn	%icc, 1b
 	 add	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
 	retl
 	 sra	%g7, 0, %o0
-	.size	__atomic_add, .-__atomic_add
+	.size	atomic_add_ret, .-atomic_add_ret
 
-	.globl	__atomic_sub
-	.type	__atomic_sub,#function
-__atomic_sub: /* %o0 = increment, %o1 = atomic_ptr */
-	lduw	[%o1], %g5
+	.globl	atomic_sub_ret
+	.type	atomic_sub_ret,#function
+atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	lduw	[%o1], %g5
 	sub	%g5, %o0, %g7
 	cas	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%icc, __atomic_sub_membar
+	bne,pn	%icc, 1b
 	 sub	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
 	retl
 	 sra	%g7, 0, %o0
-	.size	__atomic_sub, .-__atomic_sub
+	.size	atomic_sub_ret, .-atomic_sub_ret
 
-	.globl	__atomic64_add
-	.type	__atomic64_add,#function
-__atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */
-	ldx	[%o1], %g5
+	.globl	atomic64_add
+	.type	atomic64_add,#function
+atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */
+1:	ldx	[%o1], %g5
 	add	%g5, %o0, %g7
 	casx	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%xcc, __atomic64_add
-	 membar	#StoreLoad | #StoreStore
+	bne,pn	%xcc, 1b
+	 nop
 	retl
-	 add	%g7, %o0, %o0
-	.size	__atomic64_add, .-__atomic64_add
+	 nop
+	.size	atomic64_add, .-atomic64_add
 
-	.globl	__atomic64_sub
-	.type	__atomic64_sub,#function
-__atomic64_sub: /* %o0 = increment, %o1 = atomic_ptr */
-	ldx	[%o1], %g5
+	.globl	atomic64_sub
+	.type	atomic64_sub,#function
+atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
+1:	ldx	[%o1], %g5
 	sub	%g5, %o0, %g7
 	casx	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%xcc, __atomic64_sub
-	 membar	#StoreLoad | #StoreStore
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	atomic64_sub, .-atomic64_sub
+
+	.globl	atomic64_add_ret
+	.type	atomic64_add_ret,#function
+atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	ldx	[%o1], %g5
+	add	%g5, %o0, %g7
+	casx	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%xcc, 1b
+	 add	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
+	retl
+	 mov	%g7, %o0
+	.size	atomic64_add_ret, .-atomic64_add_ret
+
+	.globl	atomic64_sub_ret
+	.type	atomic64_sub_ret,#function
+atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	ldx	[%o1], %g5
+	sub	%g5, %o0, %g7
+	casx	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%xcc, 1b
+	 sub	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
 	retl
-	 sub	%g7, %o0, %o0
-	.size	__atomic64_sub, .-__atomic64_sub
+	 mov	%g7, %o0
+	.size	atomic64_sub_ret, .-atomic64_sub_ret
diff -Nru a/arch/sparc64/lib/bitops.S b/arch/sparc64/lib/bitops.S
--- a/arch/sparc64/lib/bitops.S	2004-08-26 14:34:13 -07:00
+++ b/arch/sparc64/lib/bitops.S	2005-02-05 15:23:23 -08:00
@@ -4,69 +4,142 @@
  * Copyright (C) 2000 David S. Miller (davem@redhat.com)
  */
 
+#include <linux/config.h>
 #include <asm/asi.h>
 
+	/* On SMP we need to use memory barriers to ensure
+	 * correct memory operation ordering, nop these out
+	 * for uniprocessor.
+	 */
+#ifdef CONFIG_SMP
+#define BITOP_PRE_BARRIER	membar #StoreLoad | #LoadLoad
+#define BITOP_POST_BARRIER	membar #StoreLoad | #StoreStore
+#else
+#define BITOP_PRE_BARRIER	nop
+#define BITOP_POST_BARRIER	nop
+#endif
+
 	.text
-	.align	64
-	.globl	___test_and_set_bit
-	.type	___test_and_set_bit,#function
-___test_and_set_bit:	/* %o0=nr, %o1=addr */
+
+	.globl	test_and_set_bit
+	.type	test_and_set_bit,#function
+test_and_set_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	or	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_set_bit, .-test_and_set_bit
+
+	.globl	test_and_clear_bit
+	.type	test_and_clear_bit,#function
+test_and_clear_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	andn	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_clear_bit, .-test_and_clear_bit
+
+	.globl	test_and_change_bit
+	.type	test_and_change_bit,#function
+test_and_change_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	xor	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_change_bit, .-test_and_change_bit
+
+	.globl	set_bit
+	.type	set_bit,#function
+set_bit:		/* %o0=nr, %o1=addr */
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	andcc	%g7, %g5, %o0
-	bne,pn	%xcc, 2f
-	 xor	%g7, %g5, %g1
+1:	ldx	[%o1], %g7
+	or	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-	.size	___test_and_set_bit, .-___test_and_set_bit
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	set_bit, .-set_bit
 
-	.globl	___test_and_clear_bit
-	.type	___test_and_clear_bit,#function
-___test_and_clear_bit:	/* %o0=nr, %o1=addr */
+	.globl	clear_bit
+	.type	clear_bit,#function
+clear_bit:		/* %o0=nr, %o1=addr */
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	andcc	%g7, %g5, %o0
-	be,pn	%xcc, 2f
-	 xor	%g7, %g5, %g1
+1:	ldx	[%o1], %g7
+	andn	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-	.size	___test_and_clear_bit, .-___test_and_clear_bit
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	clear_bit, .-clear_bit
 
-	.globl	___test_and_change_bit
-	.type	___test_and_change_bit,#function
-___test_and_change_bit:	/* %o0=nr, %o1=addr */
+	.globl	change_bit
+	.type	change_bit,#function
+change_bit:		/* %o0=nr, %o1=addr */
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	and	%g7, %g5, %o0
+1:	ldx	[%o1], %g7
 	xor	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-	nop
-	.size	___test_and_change_bit, .-___test_and_change_bit
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	change_bit, .-change_bit
diff -Nru a/arch/sparc64/lib/debuglocks.c b/arch/sparc64/lib/debuglocks.c
--- a/arch/sparc64/lib/debuglocks.c	2004-09-03 16:55:27 -07:00
+++ b/arch/sparc64/lib/debuglocks.c	2005-02-06 20:50:51 -08:00
@@ -172,6 +172,7 @@
 runlock_again:
 	/* Spin trying to decrement the counter using casx.  */
 	__asm__ __volatile__(
+"	membar	#StoreLoad | #LoadLoad\n"
 "	ldx	[%0], %%g5\n"
 "	sub	%%g5, 1, %%g7\n"
 "	casx	[%0], %%g5, %%g7\n"
@@ -290,6 +291,7 @@
 	current->thread.smp_lock_count--;
 wlock_again:
 	__asm__ __volatile__(
+"	membar	#StoreLoad | #LoadLoad\n"
 "	mov	1, %%g3\n"
 "	sllx	%%g3, 63, %%g3\n"
 "	ldx	[%0], %%g5\n"
diff -Nru a/arch/sparc64/lib/user_fixup.c b/arch/sparc64/lib/user_fixup.c
--- a/arch/sparc64/lib/user_fixup.c	2004-08-23 14:32:55 -07:00
+++ b/arch/sparc64/lib/user_fixup.c	2005-02-07 11:34:13 -08:00
@@ -20,11 +20,12 @@
 	char *dst = to;
 	const char __user *src = from;
 
-	while (size--) {
+	while (size) {
 		if (__get_user(*dst, src))
 			break;
 		dst++;
 		src++;
+		size--;
 	}
 
 	if (size)
@@ -38,11 +39,12 @@
 	char __user *dst = to;
 	const char *src = from;
 
-	while (size--) {
+	while (size) {
 		if (__put_user(*src, dst))
 			break;
 		dst++;
 		src++;
+		size--;
 	}
 
 	return size;
@@ -53,7 +55,7 @@
 	char __user *dst = to;
 	char __user *src = from;
 
-	while (size--) {
+	while (size) {
 		char tmp;
 
 		if (__get_user(tmp, src))
@@ -62,6 +64,7 @@
 			break;
 		dst++;
 		src++;
+		size--;
 	}
 
 	return size;
diff -Nru a/arch/um/Kconfig b/arch/um/Kconfig
--- a/arch/um/Kconfig	2005-01-15 14:31:06 -08:00
+++ b/arch/um/Kconfig	2005-02-04 17:23:04 -08:00
@@ -313,11 +313,9 @@
 	source "drivers/mtd/Kconfig"
 endif
 
+#This is just to shut up some Kconfig warnings, so no prompt.
 config INPUT
-	bool "Dummy option"
-	depends BROKEN
+	bool
 	default n
-	help
-	This is a dummy option to get rid of warnings.
 
 source "arch/um/Kconfig.debug"
diff -Nru a/arch/um/Kconfig_arch b/arch/um/Kconfig_arch
--- a/arch/um/Kconfig_arch	2005-01-11 16:42:52 -08:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,16 +0,0 @@
-config 64_BIT
-	bool
-	default n
-
-config TOP_ADDR
- 	hex
- 	default 0xc0000000 if !HOST_2G_2G
- 	default 0x80000000 if HOST_2G_2G
-
-config 3_LEVEL_PGTABLES
-	bool "Three-level pagetables"
-	default n
-	help
-	Three-level pagetables will let UML have more than 4G of physical
-	memory.  All the memory that can't be mapped directly will be treated
-	as high memory.
diff -Nru a/arch/um/Kconfig_i386 b/arch/um/Kconfig_i386
--- a/arch/um/Kconfig_i386	2005-01-11 16:42:55 -08:00
+++ b/arch/um/Kconfig_i386	2005-02-04 17:23:04 -08:00
@@ -18,3 +18,7 @@
 config ARCH_HAS_SC_SIGNALS
 	bool
 	default y
+
+config ARCH_REUSE_HOST_VSYSCALL_AREA
+	bool
+	default y
diff -Nru a/arch/um/Kconfig_x86_64 b/arch/um/Kconfig_x86_64
--- a/arch/um/Kconfig_x86_64	2005-01-11 16:42:55 -08:00
+++ b/arch/um/Kconfig_x86_64	2005-02-04 17:23:04 -08:00
@@ -9,3 +9,7 @@
 config ARCH_HAS_SC_SIGNALS
 	bool
 	default n
+
+config ARCH_REUSE_HOST_VSYSCALL_AREA
+	bool
+	default n
diff -Nru a/arch/um/Makefile b/arch/um/Makefile
--- a/arch/um/Makefile	2005-01-15 14:01:55 -08:00
+++ b/arch/um/Makefile	2005-02-04 17:23:05 -08:00
@@ -20,8 +20,11 @@
 	arch-signal.h module.h vm-flags.h
 SYMLINK_HEADERS := $(foreach header,$(SYMLINK_HEADERS),include/asm-um/$(header))
 
-# The "os" symlink is only used by arch/um/include/os.h, which includes
+# XXX: The "os" symlink is only used by arch/um/include/os.h, which includes
 # ../os/include/file.h
+#
+# These are cleaned up during mrproper. Please DO NOT fix it again, this is
+# the Correct Thing(tm) to do!
 ARCH_SYMLINKS = include/asm-um/arch $(ARCH_DIR)/include/sysdep $(ARCH_DIR)/os \
 	$(SYMLINK_HEADERS) $(ARCH_DIR)/include/uml-config.h
 
@@ -58,7 +61,7 @@
 
 USER_CFLAGS := $(patsubst -I%,,$(CFLAGS))
 USER_CFLAGS := $(patsubst -D__KERNEL__,,$(USER_CFLAGS)) $(ARCH_INCLUDE) \
-	$(MODE_INCLUDE)
+	$(MODE_INCLUDE) $(ARCH_USER_CFLAGS)
 CFLAGS += -Derrno=kernel_errno -Dsigprocmask=kernel_sigprocmask
 CFLAGS += $(call cc-option,-fno-unit-at-a-time,)
 
@@ -134,7 +137,8 @@
 	$(GEN_HEADERS) $(ARCH_DIR)/include/skas_ptregs.h
 
 MRPROPER_FILES += $(SYMLINK_HEADERS) $(ARCH_SYMLINKS) \
-	$(addprefix $(ARCH_DIR)/kernel/,$(KERN_SYMLINKS)) $(ARCH_DIR)/os
+	$(addprefix $(ARCH_DIR)/kernel/,$(KERN_SYMLINKS)) $(ARCH_DIR)/os \
+	$(ARCH_DIR)/Kconfig_arch
 
 archclean:
 	$(Q)$(MAKE) $(clean)=$(ARCH_DIR)/util
diff -Nru a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
--- a/arch/um/kernel/mem.c	2005-01-11 16:42:55 -08:00
+++ b/arch/um/kernel/mem.c	2005-02-04 17:23:05 -08:00
@@ -79,7 +79,7 @@
 	uml_reserved = brk_end;
 
 	/* Fill in any hole at the start of the binary */
-	start = (unsigned long) &__binary_start;
+	start = (unsigned long) &__binary_start & PAGE_MASK;
 	if(uml_physmem != start){
 		map_memory(uml_physmem, __pa(uml_physmem), start - uml_physmem,
 			   1, 1, 0);
@@ -152,6 +152,7 @@
 static void init_highmem(void)
 {
 	pgd_t *pgd;
+	pud_t *pud;
 	pmd_t *pmd;
 	pte_t *pte;
 	unsigned long vaddr;
@@ -163,7 +164,8 @@
 	fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, swapper_pg_dir);
 
 	pgd = swapper_pg_dir + pgd_index(vaddr);
-	pmd = pmd_offset(pgd, vaddr);
+	pud = pud_offset(pgd, vaddr);
+	pmd = pmd_offset(pud, vaddr);
 	pte = pte_offset_kernel(pmd, vaddr);
 	pkmap_page_table = pte;
 
@@ -173,9 +175,10 @@
 
 static void __init fixaddr_user_init( void)
 {
-#if FIXADDR_USER_START != 0
+#if CONFIG_ARCH_REUSE_HOST_VSYSCALL_AREA
 	long size = FIXADDR_USER_END - FIXADDR_USER_START;
 	pgd_t *pgd;
+	pud_t *pud;
 	pmd_t *pmd;
 	pte_t *pte;
 	unsigned long paddr, vaddr = FIXADDR_USER_START;
@@ -187,9 +190,10 @@
 	paddr = (unsigned long)alloc_bootmem_low_pages( size);
 	memcpy( (void *)paddr, (void *)FIXADDR_USER_START, size);
 	paddr = __pa(paddr);
-	for ( ; size > 0; size-=PAGE_SIZE, vaddr+=PAGE_SIZE, paddr+=PAGE_SIZE) {
+	for ( ; size > 0; size-=PAGE_SIZE, vaddr+=PAGE_SIZE, paddr+=PAGE_SIZE){
 		pgd = swapper_pg_dir + pgd_index(vaddr);
-		pmd = pmd_offset(pgd, vaddr);
+		pud = pud_offset(pgd, vaddr);
+		pmd = pmd_offset(pud, vaddr);
 		pte = pte_offset_kernel(pmd, vaddr);
 		pte_set_val( (*pte), paddr, PAGE_READONLY);
 	}
diff -Nru a/arch/um/kernel/process.c b/arch/um/kernel/process.c
--- a/arch/um/kernel/process.c	2005-01-15 14:01:55 -08:00
+++ b/arch/um/kernel/process.c	2005-02-04 17:23:04 -08:00
@@ -13,6 +13,10 @@
 #include <setjmp.h>
 #include <sys/time.h>
 #include <sys/ptrace.h>
+
+/*Userspace header, must be after sys/ptrace.h, and both must be included. */
+#include <linux/ptrace.h>
+
 #include <sys/wait.h>
 #include <sys/mman.h>
 #include <asm/unistd.h>
@@ -422,14 +426,3 @@
 	return(0);
 }
 #endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -Nru a/arch/um/kernel/skas/Makefile b/arch/um/kernel/skas/Makefile
--- a/arch/um/kernel/skas/Makefile	2005-01-11 16:42:51 -08:00
+++ b/arch/um/kernel/skas/Makefile	2005-02-07 18:25:10 -08:00
@@ -11,3 +11,5 @@
 
 $(USER_OBJS) : %.o: %.c
 	$(CC) $(CFLAGS_$(notdir $@)) $(USER_CFLAGS) -c -o $@ $<
+
+subdir- := util
diff -Nru a/arch/um/kernel/skas/trap_user.c b/arch/um/kernel/skas/trap_user.c
--- a/arch/um/kernel/skas/trap_user.c	2005-01-11 16:42:53 -08:00
+++ b/arch/um/kernel/skas/trap_user.c	2005-02-04 17:23:04 -08:00
@@ -20,6 +20,14 @@
 	int save_errno = errno;
 	int save_user;
 
+	/* This is done because to allow SIGSEGV to be delivered inside a SEGV
+	 * handler.  This can happen in copy_user, and if SEGV is disabled,
+	 * the process will die.
+	 * XXX Figure out why this is better than SA_NODEFER
+	 */
+	if(sig == SIGSEGV)
+		change_sig(SIGSEGV, 1);
+
 	r = &TASK_REGS(get_current())->skas;
 	save_user = r->is_user;
 	r->is_user = 0;
diff -Nru a/arch/um/kernel/sys_call_table.c b/arch/um/kernel/sys_call_table.c
--- a/arch/um/kernel/sys_call_table.c	2005-01-11 16:42:56 -08:00
+++ b/arch/um/kernel/sys_call_table.c	2005-02-04 17:23:04 -08:00
@@ -20,7 +20,7 @@
 #define NFSSERVCTL sys_ni_syscall
 #endif
 
-#define LAST_GENERIC_SYSCALL __NR_vperfctr_read
+#define LAST_GENERIC_SYSCALL __NR_keyctl
 
 #if LAST_GENERIC_SYSCALL > LAST_ARCH_SYSCALL
 #define LAST_SYSCALL LAST_GENERIC_SYSCALL
@@ -52,13 +52,7 @@
 extern syscall_handler_t sys_mbind;
 extern syscall_handler_t sys_get_mempolicy;
 extern syscall_handler_t sys_set_mempolicy;
-extern syscall_handler_t sys_sys_kexec_load;
 extern syscall_handler_t sys_sys_setaltroot;
-extern syscall_handler_t sys_vperfctr_open;
-extern syscall_handler_t sys_vperfctr_control;
-extern syscall_handler_t sys_vperfctr_unlink;
-extern syscall_handler_t sys_vperfctr_iresume;
-extern syscall_handler_t sys_vperfctr_read;
 
 syscall_handler_t *sys_call_table[] = {
 	[ __NR_restart_syscall ] = (syscall_handler_t *) sys_restart_syscall,
@@ -273,32 +267,14 @@
 	[ __NR_mq_timedreceive ] = (syscall_handler_t *) sys_mq_timedreceive,
 	[ __NR_mq_notify ] = (syscall_handler_t *) sys_mq_notify,
 	[ __NR_mq_getsetattr ] = (syscall_handler_t *) sys_mq_getsetattr,
-	[ __NR_sys_kexec_load ] = (syscall_handler_t *) sys_kexec_load,
+	[ __NR_sys_kexec_load ] = (syscall_handler_t *) sys_ni_syscall,
 	[ __NR_waitid ] = (syscall_handler_t *) sys_waitid,
-#if 0
-	[ __NR_sys_setaltroot ] = (syscall_handler_t *) sys_sys_setaltroot,
-#endif
+	[ 285 ] = (syscall_handler_t *) sys_ni_syscall,
 	[ __NR_add_key ] = (syscall_handler_t *) sys_add_key,
 	[ __NR_request_key ] = (syscall_handler_t *) sys_request_key,
 	[ __NR_keyctl ] = (syscall_handler_t *) sys_keyctl,
-	[ __NR_vperfctr_open ] = (syscall_handler_t *) sys_vperfctr_open,
-	[ __NR_vperfctr_control ] = (syscall_handler_t *) sys_vperfctr_control,
-	[ __NR_vperfctr_unlink ] = (syscall_handler_t *) sys_vperfctr_unlink,
-	[ __NR_vperfctr_iresume ] = (syscall_handler_t *) sys_vperfctr_iresume,
-	[ __NR_vperfctr_read ] = (syscall_handler_t *) sys_vperfctr_read,
 
 	ARCH_SYSCALLS
 	[ LAST_SYSCALL + 1 ... NR_syscalls ] = 
 	        (syscall_handler_t *) sys_ni_syscall
 };
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -Nru a/arch/um/kernel/time_kern.c b/arch/um/kernel/time_kern.c
--- a/arch/um/kernel/time_kern.c	2005-01-20 21:02:11 -08:00
+++ b/arch/um/kernel/time_kern.c	2005-02-04 17:23:04 -08:00
@@ -22,7 +22,7 @@
 #include "mode.h"
 #include "os.h"
 
-u64 jiffies_64;
+u64 jiffies_64 = INITIAL_JIFFIES;
 
 EXPORT_SYMBOL(jiffies_64);
 
diff -Nru a/arch/um/kernel/trap_kern.c b/arch/um/kernel/trap_kern.c
--- a/arch/um/kernel/trap_kern.c	2005-01-20 21:02:11 -08:00
+++ b/arch/um/kernel/trap_kern.c	2005-02-04 17:23:04 -08:00
@@ -48,6 +48,8 @@
 		goto good_area;
 	else if(!(vma->vm_flags & VM_GROWSDOWN)) 
 		goto out;
+	else if(!ARCH_IS_STACKGROW(address))
+		goto out;
 	else if(expand_stack(vma, address)) 
 		goto out;
 
diff -Nru a/arch/x86_64/kernel/setup64.c b/arch/x86_64/kernel/setup64.c
--- a/arch/x86_64/kernel/setup64.c	2005-01-15 14:01:53 -08:00
+++ b/arch/x86_64/kernel/setup64.c	2005-02-05 12:54:22 -08:00
@@ -52,10 +52,10 @@
 */ 
 void __init nonx_setup(const char *str)
 {
-	if (!strcmp(str, "on")) {
+	if (!strncmp(str, "on", 2)) {
                 __supported_pte_mask |= _PAGE_NX; 
  		do_not_nx = 0; 
-	} else if (!strcmp(str, "off")) {
+	} else if (!strncmp(str, "off", 3)) {
 		do_not_nx = 1;
 		__supported_pte_mask &= ~_PAGE_NX;
         } 
diff -Nru a/drivers/atm/horizon.c b/drivers/atm/horizon.c
--- a/drivers/atm/horizon.c	2005-01-18 12:58:23 -08:00
+++ b/drivers/atm/horizon.c	2005-02-06 22:17:26 -08:00
@@ -39,6 +39,7 @@
 #include <linux/uio.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
+#include <linux/wait.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -1089,13 +1090,11 @@
 /********** (queue to) become the next TX thread **********/
 
 static inline int tx_hold (hrz_dev * dev) {
-  while (test_and_set_bit (tx_busy, &dev->flags)) {
-    PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
-    interruptible_sleep_on (&dev->tx_queue);
-    PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
-    if (signal_pending (current))
-      return -1;
-  }
+  PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
+  wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
+  PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
+  if (signal_pending (current))
+    return -1;
   PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
   return 0;
 }
diff -Nru a/drivers/atm/iphase.c b/drivers/atm/iphase.c
--- a/drivers/atm/iphase.c	2004-12-27 18:07:47 -08:00
+++ b/drivers/atm/iphase.c	2005-02-06 22:18:18 -08:00
@@ -53,6 +53,7 @@
 #include <linux/delay.h>  
 #include <linux/uio.h>  
 #include <linux/init.h>  
+#include <linux/wait.h>
 #include <asm/system.h>  
 #include <asm/io.h>  
 #include <asm/atomic.h>  
@@ -2586,14 +2587,14 @@
 }  
   
 static void ia_close(struct atm_vcc *vcc)  
-{  
+{
+	DEFINE_WAIT(wait);
         u16 *vc_table;
         IADEV *iadev;
         struct ia_vcc *ia_vcc;
         struct sk_buff *skb = NULL;
         struct sk_buff_head tmp_tx_backlog, tmp_vcc_backlog;
         unsigned long closetime, flags;
-        int ctimeout;
 
         iadev = INPH_IA_DEV(vcc->dev);
         ia_vcc = INPH_IA_VCC(vcc);
@@ -2606,7 +2607,9 @@
         skb_queue_head_init (&tmp_vcc_backlog); 
         if (vcc->qos.txtp.traffic_class != ATM_NONE) {
            iadev->close_pending++;
-           sleep_on_timeout(&iadev->timeout_wait, 50);
+	   prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
+	   schedule_timeout(50);
+	   finish_wait(&iadev->timeout_wait, &wait);
            spin_lock_irqsave(&iadev->tx_lock, flags); 
            while((skb = skb_dequeue(&iadev->tx_backlog))) {
               if (ATM_SKB(skb)->vcc == vcc){ 
@@ -2619,17 +2622,12 @@
            while((skb = skb_dequeue(&tmp_tx_backlog))) 
              skb_queue_tail(&iadev->tx_backlog, skb);
            IF_EVENT(printk("IA TX Done decs_cnt = %d\n", ia_vcc->vc_desc_cnt);) 
-           closetime = jiffies;
-           ctimeout = 300000 / ia_vcc->pcr;
-           if (ctimeout == 0)
-              ctimeout = 1;
-           while (ia_vcc->vc_desc_cnt > 0){
-              if ((jiffies - closetime) >= ctimeout) 
-                 break;
-              spin_unlock_irqrestore(&iadev->tx_lock, flags);
-              sleep_on(&iadev->close_wait);
-              spin_lock_irqsave(&iadev->tx_lock, flags);
-           }    
+           closetime = 300000 / ia_vcc->pcr;
+           if (closetime == 0)
+              closetime = 1;
+           spin_unlock_irqrestore(&iadev->tx_lock, flags);
+           wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
+           spin_lock_irqsave(&iadev->tx_lock, flags);
            iadev->close_pending--;
            iadev->testTable[vcc->vci]->lastTime = 0;
            iadev->testTable[vcc->vci]->fract = 0; 
diff -Nru a/drivers/atm/zatm.c b/drivers/atm/zatm.c
--- a/drivers/atm/zatm.c	2004-12-26 22:04:22 -08:00
+++ b/drivers/atm/zatm.c	2005-02-06 22:19:00 -08:00
@@ -22,6 +22,7 @@
 #include <linux/atm_zatm.h>
 #include <linux/capability.h>
 #include <linux/bitops.h>
+#include <linux/wait.h>
 #include <asm/byteorder.h>
 #include <asm/system.h>
 #include <asm/string.h>
@@ -867,31 +868,21 @@
 	struct zatm_vcc *zatm_vcc;
 	unsigned long flags;
 	int chan;
-struct sk_buff *skb;
-int once = 1;
 
 	zatm_vcc = ZATM_VCC(vcc);
 	zatm_dev = ZATM_DEV(vcc->dev);
 	chan = zatm_vcc->tx_chan;
 	if (!chan) return;
 	DPRINTK("close_tx\n");
-	while (skb_peek(&zatm_vcc->backlog)) {
-if (once) {
-printk("waiting for backlog to drain ...\n");
-event_dump();
-once = 0;
-}
-		sleep_on(&zatm_vcc->tx_wait);
-	}
-once = 1;
-	while ((skb = skb_peek(&zatm_vcc->tx_queue))) {
-if (once) {
-printk("waiting for TX queue to drain ... %p\n",skb);
-event_dump();
-once = 0;
-}
-		DPRINTK("waiting for TX queue to drain ... %p\n",skb);
-		sleep_on(&zatm_vcc->tx_wait);
+	if (skb_peek(&zatm_vcc->backlog)) {
+		printk("waiting for backlog to drain ...\n");
+		event_dump();
+		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->backlog));
+	}
+	if (skb_peek(&zatm_vcc->tx_queue)) {
+		printk("waiting for TX queue to drain ...\n");
+		event_dump();
+		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->tx_queue));
 	}
 	spin_lock_irqsave(&zatm_dev->lock, flags);
 #if 0
diff -Nru a/drivers/block/sx8.c b/drivers/block/sx8.c
--- a/drivers/block/sx8.c	2005-01-08 17:05:19 -08:00
+++ b/drivers/block/sx8.c	2005-02-06 23:59:54 -08:00
@@ -1503,7 +1503,8 @@
 		}
 
 		port->disk = disk;
-		sprintf(disk->disk_name, DRV_NAME "/%u", (host->id * CARM_MAX_PORTS) + i);
+		sprintf(disk->disk_name, DRV_NAME "/%u",
+			(unsigned int) (host->id * CARM_MAX_PORTS) + i);
 		sprintf(disk->devfs_name, DRV_NAME "/%u_%u", host->id, i);
 		disk->major = host->major;
 		disk->first_minor = i * CARM_MINORS_PER_MAJOR;
diff -Nru a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
--- a/drivers/bluetooth/Kconfig	2004-04-08 16:19:50 -07:00
+++ b/drivers/bluetooth/Kconfig	2005-02-01 20:01:28 -08:00
@@ -75,6 +75,17 @@
 	  Say Y here to compile support for HCI BCM203x devices into the
 	  kernel or say M to compile it as module (bcm203x).
 
+config BT_HCIBPA10X
+	tristate "HCI BPA10x USB driver"
+	depends on USB
+	help
+	  Bluetooth HCI BPA10x USB driver.
+	  This driver provides support for the Digianswer BPA 100/105 Bluetooth
+	  sniffer devices.
+
+	  Say Y here to compile support for HCI BPA10x devices into the
+	  kernel or say M to compile it as module (bpa10x).
+
 config BT_HCIBFUSB
 	tristate "HCI BlueFRITZ! USB driver"
 	depends on USB
diff -Nru a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile
--- a/drivers/bluetooth/Makefile	2003-12-27 10:57:21 -08:00
+++ b/drivers/bluetooth/Makefile	2005-02-01 19:59:02 -08:00
@@ -6,6 +6,7 @@
 obj-$(CONFIG_BT_HCIVHCI)	+= hci_vhci.o
 obj-$(CONFIG_BT_HCIUART)	+= hci_uart.o
 obj-$(CONFIG_BT_HCIBCM203X)	+= bcm203x.o
+obj-$(CONFIG_BT_HCIBPA10X)	+= bpa10x.o
 obj-$(CONFIG_BT_HCIBFUSB)	+= bfusb.o
 obj-$(CONFIG_BT_HCIDTL1)	+= dtl1_cs.o
 obj-$(CONFIG_BT_HCIBT3C)	+= bt3c_cs.o
diff -Nru a/drivers/bluetooth/bpa10x.c b/drivers/bluetooth/bpa10x.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/drivers/bluetooth/bpa10x.c	2005-02-01 19:57:10 -08:00
@@ -0,0 +1,657 @@
+/*
+ *
+ *  Digianswer Bluetooth USB driver
+ *
+ *  Copyright (C) 2004-2005  Marcel Holtmann <marcel@holtmann.org>
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+
+#include <linux/usb.h>
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#ifndef CONFIG_BT_HCIBPA10X_DEBUG
+#undef  BT_DBG
+#define BT_DBG(D...)
+#endif
+
+#define VERSION "0.8"
+
+static int ignore = 0;
+
+static struct usb_device_id bpa10x_table[] = {
+	/* Tektronix BPA 100/105 (Digianswer) */
+	{ USB_DEVICE(0x08fd, 0x0002) },
+
+	{ }	/* Terminating entry */
+};
+
+MODULE_DEVICE_TABLE(usb, bpa10x_table);
+
+#define BPA10X_CMD_EP		0x00
+#define BPA10X_EVT_EP		0x81
+#define BPA10X_TX_EP		0x02
+#define BPA10X_RX_EP		0x82
+
+#define BPA10X_CMD_BUF_SIZE	252
+#define BPA10X_EVT_BUF_SIZE	16
+#define BPA10X_TX_BUF_SIZE	384
+#define BPA10X_RX_BUF_SIZE	384
+
+struct bpa10x_data {
+	struct hci_dev		*hdev;
+	struct usb_device	*udev;
+
+	rwlock_t		lock;
+
+	struct sk_buff_head	cmd_queue;
+	struct urb		*cmd_urb;
+	struct urb		*evt_urb;
+	struct sk_buff		*evt_skb;
+	unsigned int		evt_len;
+
+	struct sk_buff_head	tx_queue;
+	struct urb		*tx_urb;
+	struct urb		*rx_urb;
+};
+
+#define HCI_VENDOR_HDR_SIZE	5
+
+struct hci_vendor_hdr {
+	__u8	type;
+	__u16	snum;
+	__u16	dlen;
+} __attribute__ ((packed));
+
+static void bpa10x_recv_bulk(struct bpa10x_data *data, unsigned char *buf, int count)
+{
+	struct hci_acl_hdr *ah;
+	struct hci_sco_hdr *sh;
+	struct hci_vendor_hdr *vh;
+	struct sk_buff *skb;
+	int len;
+
+	while (count) {
+		switch (*buf++) {
+		case HCI_ACLDATA_PKT:
+			ah = (struct hci_acl_hdr *) buf;
+			len = HCI_ACL_HDR_SIZE + __le16_to_cpu(ah->dlen);
+			skb = bt_skb_alloc(len, GFP_ATOMIC);
+			if (skb) {
+				memcpy(skb_put(skb, len), buf, len);
+				skb->dev = (void *) data->hdev;
+				skb->pkt_type = HCI_ACLDATA_PKT;
+				hci_recv_frame(skb);
+			}
+			break;
+
+		case HCI_SCODATA_PKT:
+			sh = (struct hci_sco_hdr *) buf;
+			len = HCI_SCO_HDR_SIZE + sh->dlen;
+			skb = bt_skb_alloc(len, GFP_ATOMIC);
+			if (skb) {
+				memcpy(skb_put(skb, len), buf, len);
+				skb->dev = (void *) data->hdev;
+				skb->pkt_type = HCI_SCODATA_PKT;
+				hci_recv_frame(skb);
+			}
+			break;
+
+		case HCI_VENDOR_PKT:
+			vh = (struct hci_vendor_hdr *) buf;
+			len = HCI_VENDOR_HDR_SIZE + __le16_to_cpu(vh->dlen);
+			skb = bt_skb_alloc(len, GFP_ATOMIC);
+			if (skb) {
+				memcpy(skb_put(skb, len), buf, len);
+				skb->dev = (void *) data->hdev;
+				skb->pkt_type = HCI_VENDOR_PKT;
+				hci_recv_frame(skb);
+			}
+			break;
+
+		default:
+			len = count - 1;
+			break;
+		}
+
+		buf   += len;
+		count -= (len + 1);
+	}
+}
+
+static int bpa10x_recv_event(struct bpa10x_data *data, unsigned char *buf, int size)
+{
+	BT_DBG("data %p buf %p size %d", data, buf, size);
+
+	if (data->evt_skb) {
+		struct sk_buff *skb = data->evt_skb;
+
+		memcpy(skb_put(skb, size), buf, size);
+
+		if (skb->len == data->evt_len) {
+			data->evt_skb = NULL;
+			data->evt_len = 0;
+			hci_recv_frame(skb);
+		}
+	} else {
+		struct sk_buff *skb;
+		struct hci_event_hdr *hdr;
+		unsigned char pkt_type;
+		int pkt_len = 0;
+
+		if (size < HCI_EVENT_HDR_SIZE + 1) {
+			BT_ERR("%s event packet block with size %d is too short",
+							data->hdev->name, size);
+			return -EILSEQ;
+		}
+
+		pkt_type = *buf++;
+		size--;
+
+		if (pkt_type != HCI_EVENT_PKT) {
+			BT_ERR("%s unexpected event packet start byte 0x%02x",
+							data->hdev->name, pkt_type);
+			return -EPROTO;
+		}
+
+		hdr = (struct hci_event_hdr *) buf;
+		pkt_len = HCI_EVENT_HDR_SIZE + hdr->plen;
+
+		skb = bt_skb_alloc(pkt_len, GFP_ATOMIC);
+		if (!skb) {
+			BT_ERR("%s no memory for new event packet",
+							data->hdev->name);
+			return -ENOMEM;
+		}
+
+		skb->dev = (void *) data->hdev;
+		skb->pkt_type = pkt_type;
+
+		memcpy(skb_put(skb, size), buf, size);
+
+		if (pkt_len == size) {
+			hci_recv_frame(skb);
+		} else {
+			data->evt_skb = skb;
+			data->evt_len = pkt_len;
+		}
+	}
+
+	return 0;
+}
+
+static void bpa10x_wakeup(struct bpa10x_data *data)
+{
+	struct urb *urb;
+	struct sk_buff *skb;
+	int err;
+
+	BT_DBG("data %p", data);
+
+	urb = data->cmd_urb;
+	if (urb->status == -EINPROGRESS)
+		skb = NULL;
+	else
+		skb = skb_dequeue(&data->cmd_queue);
+
+	if (skb) {
+		struct usb_ctrlrequest *cr;
+
+		if (skb->len > BPA10X_CMD_BUF_SIZE) {
+			BT_ERR("%s command packet with size %d is too big",
+							data->hdev->name, skb->len);
+			kfree_skb(skb);
+			return;
+		}
+
+		cr = (struct usb_ctrlrequest *) urb->setup_packet;
+		cr->wLength = __cpu_to_le16(skb->len);
+
+		memcpy(urb->transfer_buffer, skb->data, skb->len);
+		urb->transfer_buffer_length = skb->len;
+
+		err = usb_submit_urb(urb, GFP_ATOMIC);
+		if (err < 0 && err != -ENODEV) {
+			BT_ERR("%s submit failed for command urb %p with error %d",
+							data->hdev->name, urb, err);
+			skb_queue_head(&data->cmd_queue, skb);
+		} else
+			kfree_skb(skb);
+	}
+
+	urb = data->tx_urb;
+	if (urb->status == -EINPROGRESS)
+		skb = NULL;
+	else
+		skb = skb_dequeue(&data->tx_queue);
+
+	if (skb) {
+		memcpy(urb->transfer_buffer, skb->data, skb->len);
+		urb->transfer_buffer_length = skb->len;
+
+		err = usb_submit_urb(urb, GFP_ATOMIC);
+		if (err < 0 && err != -ENODEV) {
+			BT_ERR("%s submit failed for command urb %p with error %d",
+							data->hdev->name, urb, err);
+			skb_queue_head(&data->tx_queue, skb);
+		} else
+			kfree_skb(skb);
+	}
+}
+
+static void bpa10x_complete(struct urb *urb, struct pt_regs *regs)
+{
+	struct bpa10x_data *data = urb->context;
+	unsigned char *buf = urb->transfer_buffer;
+	int err, count = urb->actual_length;
+
+	BT_DBG("data %p urb %p buf %p count %d", data, urb, buf, count);
+
+	read_lock(&data->lock);
+
+	if (!test_bit(HCI_RUNNING, &data->hdev->flags))
+		goto unlock;
+
+	if (urb->status < 0 || !count)
+		goto resubmit;
+
+	if (usb_pipein(urb->pipe)) {
+		data->hdev->stat.byte_rx += count;
+
+		if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
+			bpa10x_recv_event(data, buf, count);
+
+		if (usb_pipetype(urb->pipe) == PIPE_BULK)
+			bpa10x_recv_bulk(data, buf, count);
+	} else {
+		data->hdev->stat.byte_tx += count;
+
+		bpa10x_wakeup(data);
+	}
+
+resubmit:
+	if (usb_pipein(urb->pipe)) {
+		err = usb_submit_urb(urb, GFP_ATOMIC);
+		if (err < 0 && err != -ENODEV) {
+			BT_ERR("%s urb %p type %d resubmit status %d",
+				data->hdev->name, urb, usb_pipetype(urb->pipe), err);
+		}
+	}
+
+unlock:
+	read_unlock(&data->lock);
+}
+
+static inline struct urb *bpa10x_alloc_urb(struct usb_device *udev, unsigned int pipe, size_t size, int flags, void *data)
+{
+	struct urb *urb;
+	struct usb_ctrlrequest *cr;
+	unsigned char *buf;
+
+	BT_DBG("udev %p data %p", udev, data);
+
+	urb = usb_alloc_urb(0, flags);
+	if (!urb)
+		return NULL;
+
+	buf = kmalloc(size, flags);
+	if (!buf) {
+		usb_free_urb(urb);
+		return NULL;
+	}
+
+	switch (usb_pipetype(pipe)) {
+	case PIPE_CONTROL:
+		cr = kmalloc(sizeof(*cr), flags);
+		if (!cr) {
+			kfree(buf);
+			usb_free_urb(urb);
+			return NULL;
+		}
+
+		cr->bRequestType = USB_TYPE_VENDOR;
+		cr->bRequest     = 0;
+		cr->wIndex       = 0;
+		cr->wValue       = 0;
+		cr->wLength      = __cpu_to_le16(0);
+
+		usb_fill_control_urb(urb, udev, pipe, (void *) cr, buf, 0, bpa10x_complete, data);
+		break;
+
+	case PIPE_INTERRUPT:
+		usb_fill_int_urb(urb, udev, pipe, buf, size, bpa10x_complete, data, 1);
+		break;
+
+	case PIPE_BULK:
+		usb_fill_bulk_urb(urb, udev, pipe, buf, size, bpa10x_complete, data);
+		break;
+
+	default:
+		kfree(buf);
+		usb_free_urb(urb);
+		return NULL;
+	}
+
+	return urb;
+}
+
+static inline void bpa10x_free_urb(struct urb *urb)
+{
+	BT_DBG("urb %p", urb);
+
+	if (!urb)
+		return;
+
+	if (urb->setup_packet)
+		kfree(urb->setup_packet);
+
+	if (urb->transfer_buffer)
+		kfree(urb->transfer_buffer);
+
+	usb_free_urb(urb);
+}
+
+static int bpa10x_open(struct hci_dev *hdev)
+{
+	struct bpa10x_data *data = hdev->driver_data;
+	struct usb_device *udev = data->udev;
+	unsigned long flags;
+	int err;
+
+	BT_DBG("hdev %p data %p", hdev, data);
+
+	if (test_and_set_bit(HCI_RUNNING, &hdev->flags))
+		return 0;
+
+	data->cmd_urb = bpa10x_alloc_urb(udev, usb_sndctrlpipe(udev, BPA10X_CMD_EP),
+					BPA10X_CMD_BUF_SIZE, GFP_KERNEL, data);
+	if (!data->cmd_urb) {
+		err = -ENOMEM;
+		goto done;
+	}
+
+	data->evt_urb = bpa10x_alloc_urb(udev, usb_rcvintpipe(udev, BPA10X_EVT_EP),
+					BPA10X_EVT_BUF_SIZE, GFP_KERNEL, data);
+	if (!data->evt_urb) {
+		bpa10x_free_urb(data->cmd_urb);
+		err = -ENOMEM;
+		goto done;
+	}
+
+	data->rx_urb = bpa10x_alloc_urb(udev, usb_rcvbulkpipe(udev, BPA10X_RX_EP),
+					BPA10X_RX_BUF_SIZE, GFP_KERNEL, data);
+	if (!data->rx_urb) {
+		bpa10x_free_urb(data->evt_urb);
+		bpa10x_free_urb(data->cmd_urb);
+		err = -ENOMEM;
+		goto done;
+	}
+
+	data->tx_urb = bpa10x_alloc_urb(udev, usb_sndbulkpipe(udev, BPA10X_TX_EP),
+					BPA10X_TX_BUF_SIZE, GFP_KERNEL, data);
+	if (!data->rx_urb) {
+		bpa10x_free_urb(data->rx_urb);
+		bpa10x_free_urb(data->evt_urb);
+		bpa10x_free_urb(data->cmd_urb);
+		err = -ENOMEM;
+		goto done;
+	}
+
+	write_lock_irqsave(&data->lock, flags);
+
+	err = usb_submit_urb(data->evt_urb, GFP_ATOMIC);
+	if (err < 0) {
+		BT_ERR("%s submit failed for event urb %p with error %d",
+					data->hdev->name, data->evt_urb, err);
+	} else {
+		err = usb_submit_urb(data->rx_urb, GFP_ATOMIC);
+		if (err < 0) {
+			BT_ERR("%s submit failed for rx urb %p with error %d",
+					data->hdev->name, data->evt_urb, err);
+			usb_kill_urb(data->evt_urb);
+		}
+	}
+
+	write_unlock_irqrestore(&data->lock, flags);
+
+done:
+	if (err < 0)
+		clear_bit(HCI_RUNNING, &hdev->flags);
+
+	return err;
+}
+
+static int bpa10x_close(struct hci_dev *hdev)
+{
+	struct bpa10x_data *data = hdev->driver_data;
+	unsigned long flags;
+
+	BT_DBG("hdev %p data %p", hdev, data);
+
+	if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags))
+		return 0;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	skb_queue_purge(&data->cmd_queue);
+	usb_kill_urb(data->cmd_urb);
+	usb_kill_urb(data->evt_urb);
+	usb_kill_urb(data->rx_urb);
+	usb_kill_urb(data->tx_urb);
+
+	write_unlock_irqrestore(&data->lock, flags);
+
+	bpa10x_free_urb(data->cmd_urb);
+	bpa10x_free_urb(data->evt_urb);
+	bpa10x_free_urb(data->rx_urb);
+	bpa10x_free_urb(data->tx_urb);
+
+	return 0;
+}
+
+static int bpa10x_flush(struct hci_dev *hdev)
+{
+	struct bpa10x_data *data = hdev->driver_data;
+
+	BT_DBG("hdev %p data %p", hdev, data);
+
+	skb_queue_purge(&data->cmd_queue);
+
+	return 0;
+}
+
+static int bpa10x_send_frame(struct sk_buff *skb)
+{
+	struct hci_dev *hdev = (struct hci_dev *) skb->dev;
+	struct bpa10x_data *data;
+
+	BT_DBG("hdev %p skb %p type %d len %d", hdev, skb, skb->pkt_type, skb->len);
+
+	if (!hdev) {
+		BT_ERR("Frame for unknown HCI device");
+		return -ENODEV;
+	}
+
+	if (!test_bit(HCI_RUNNING, &hdev->flags))
+		return -EBUSY;
+
+	data = hdev->driver_data;
+
+	/* Prepend skb with frame type */
+	memcpy(skb_push(skb, 1), &(skb->pkt_type), 1);
+
+	switch (skb->pkt_type) {
+	case HCI_COMMAND_PKT:
+		hdev->stat.cmd_tx++;
+		skb_queue_tail(&data->cmd_queue, skb);
+		break;
+
+	case HCI_ACLDATA_PKT:
+		hdev->stat.acl_tx++;
+		skb_queue_tail(&data->tx_queue, skb);
+		break;
+
+	case HCI_SCODATA_PKT:
+		hdev->stat.sco_tx++;
+		skb_queue_tail(&data->tx_queue, skb);
+		break;
+	};
+
+	read_lock(&data->lock);
+
+	bpa10x_wakeup(data);
+
+	read_unlock(&data->lock);
+
+	return 0;
+}
+
+static void bpa10x_destruct(struct hci_dev *hdev)
+{
+	struct bpa10x_data *data = hdev->driver_data;
+
+	BT_DBG("hdev %p data %p", hdev, data);
+
+	kfree(data);
+}
+
+static int bpa10x_probe(struct usb_interface *intf, const struct usb_device_id *id)
+{
+	struct usb_device *udev = interface_to_usbdev(intf);
+	struct hci_dev *hdev;
+	struct bpa10x_data *data;
+	int err;
+
+	BT_DBG("intf %p id %p", intf, id);
+
+	if (ignore)
+		return -ENODEV;
+
+	data = kmalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		BT_ERR("Can't allocate data structure");
+		return -ENOMEM;
+	}
+
+	memset(data, 0, sizeof(*data));
+
+	data->udev = udev;
+
+	rwlock_init(&data->lock);
+
+	skb_queue_head_init(&data->cmd_queue);
+	skb_queue_head_init(&data->tx_queue);
+
+	hdev = hci_alloc_dev();
+	if (!hdev) {
+		BT_ERR("Can't allocate HCI device");
+		kfree(data);
+		return -ENOMEM;
+	}
+
+	data->hdev = hdev;
+
+	hdev->type = HCI_USB;
+	hdev->driver_data = data;
+	SET_HCIDEV_DEV(hdev, &intf->dev);
+
+	hdev->open	= bpa10x_open;
+	hdev->close	= bpa10x_close;
+	hdev->flush	= bpa10x_flush;
+	hdev->send	= bpa10x_send_frame;
+	hdev->destruct	= bpa10x_destruct;
+
+	hdev->owner = THIS_MODULE;
+
+	err = hci_register_dev(hdev);
+	if (err < 0) {
+		BT_ERR("Can't register HCI device");
+		kfree(data);
+		hci_free_dev(hdev);
+		return err;
+	}
+
+	usb_set_intfdata(intf, data);
+
+	return 0;
+}
+
+static void bpa10x_disconnect(struct usb_interface *intf)
+{
+	struct bpa10x_data *data = usb_get_intfdata(intf);
+	struct hci_dev *hdev = data->hdev;
+
+	BT_DBG("intf %p", intf);
+
+	if (!hdev)
+		return;
+
+	usb_set_intfdata(intf, NULL);
+
+	if (hci_unregister_dev(hdev) < 0)
+		BT_ERR("Can't unregister HCI device %s", hdev->name);
+
+	hci_free_dev(hdev);
+}
+
+static struct usb_driver bpa10x_driver = {
+	.owner		= THIS_MODULE,
+	.name		= "bpa10x",
+	.probe		= bpa10x_probe,
+	.disconnect	= bpa10x_disconnect,
+	.id_table	= bpa10x_table,
+};
+
+static int __init bpa10x_init(void)
+{
+	int err;
+
+	BT_INFO("Digianswer Bluetooth USB driver ver %s", VERSION);
+
+	err = usb_register(&bpa10x_driver);
+	if (err < 0)
+		BT_ERR("Failed to register USB driver");
+
+	return err;
+}
+
+static void __exit bpa10x_exit(void)
+{
+	usb_deregister(&bpa10x_driver);
+}
+
+module_init(bpa10x_init);
+module_exit(bpa10x_exit);
+
+module_param(ignore, bool, 0644);
+MODULE_PARM_DESC(ignore, "Ignore devices from the matching table");
+
+MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+MODULE_DESCRIPTION("Digianswer Bluetooth USB driver ver " VERSION);
+MODULE_VERSION(VERSION);
+MODULE_LICENSE("GPL");
diff -Nru a/drivers/bluetooth/hci_usb.c b/drivers/bluetooth/hci_usb.c
--- a/drivers/bluetooth/hci_usb.c	2005-01-28 18:32:51 -08:00
+++ b/drivers/bluetooth/hci_usb.c	2005-02-04 16:53:59 -08:00
@@ -73,7 +73,7 @@
 static int isoc = 2;
 #endif
 
-#define VERSION "2.7"
+#define VERSION "2.8"
 
 static struct usb_driver hci_usb_driver; 
 
@@ -104,11 +104,11 @@
 	{ USB_DEVICE(0x0a5c, 0x2033), .driver_info = HCI_IGNORE },
 
 	/* Broadcom BCM2035 */
-	{ USB_DEVICE(0x0a5c, 0x2009), .driver_info = HCI_RESET | HCI_BROKEN_ISOC },
 	{ USB_DEVICE(0x0a5c, 0x200a), .driver_info = HCI_RESET | HCI_BROKEN_ISOC },
+	{ USB_DEVICE(0x0a5c, 0x2009), .driver_info = HCI_BCM92035 },
 
 	/* Microsoft Wireless Transceiver for Bluetooth 2.0 */
-	{ USB_DEVICE(0x045e, 0x009c), .driver_info = HCI_RESET | HCI_BROKEN_ISOC },
+	{ USB_DEVICE(0x045e, 0x009c), .driver_info = HCI_BCM92035 },
 
 	/* ISSC Bluetooth Adapter v3.1 */
 	{ USB_DEVICE(0x1131, 0x1001), .driver_info = HCI_RESET },
@@ -975,6 +975,17 @@
 	if (id->driver_info & HCI_SNIFFER) {
 		if (le16_to_cpu(udev->descriptor.bcdDevice) > 0x997)
 			set_bit(HCI_QUIRK_RAW_DEVICE, &hdev->quirks);
+	}
+
+	if (id->driver_info & HCI_BCM92035) {
+		unsigned char cmd[] = { 0x3b, 0xfc, 0x01, 0x00 };
+		struct sk_buff *skb;
+
+		skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
+		if (skb) {
+			memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd));
+			skb_queue_tail(&hdev->driver_init, skb);
+		}
 	}
 
 	if (hci_register_dev(hdev) < 0) {
diff -Nru a/drivers/bluetooth/hci_usb.h b/drivers/bluetooth/hci_usb.h
--- a/drivers/bluetooth/hci_usb.h	2005-01-28 18:32:12 -08:00
+++ b/drivers/bluetooth/hci_usb.h	2005-02-04 16:53:58 -08:00
@@ -33,6 +33,7 @@
 #define HCI_DIGIANSWER		0x04
 #define HCI_SNIFFER		0x08
 #define HCI_BROKEN_ISOC		0x10
+#define HCI_BCM92035		0x20
 
 #define HCI_MAX_IFACE_NUM	3
 
diff -Nru a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
--- a/drivers/char/agp/intel-agp.c	2005-01-20 18:59:37 -08:00
+++ b/drivers/char/agp/intel-agp.c	2005-02-07 18:25:10 -08:00
@@ -1748,12 +1748,16 @@
 
 	if (bridge->driver == &intel_generic_driver)
 		intel_configure();
+	else if (bridge->driver == &intel_850_driver)
+		intel_850_configure();
 	else if (bridge->driver == &intel_845_driver)
 		intel_845_configure();
 	else if (bridge->driver == &intel_830mp_driver)
 		intel_830mp_configure();
 	else if (bridge->driver == &intel_915_driver)
 		intel_i915_configure();
+	else if (bridge->driver == &intel_830_driver)
+		intel_i830_configure();
 
 	return 0;
 }
diff -Nru a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
--- a/drivers/char/drm/drm_drv.c	2005-01-16 00:14:18 -08:00
+++ b/drivers/char/drm/drm_drv.c	2005-02-08 00:26:15 -08:00
@@ -516,7 +516,7 @@
 	
 	if (nr < DRIVER_IOCTL_COUNT)
 		ioctl = &drm_ioctls[nr];
-	else if ((nr >= DRM_COMMAND_BASE) || (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
+	else if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
 		ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
 	else
 		goto err_i1;
diff -Nru a/drivers/char/drm/drm_os_linux.h b/drivers/char/drm/drm_os_linux.h
--- a/drivers/char/drm/drm_os_linux.h	2004-10-23 23:44:47 -07:00
+++ b/drivers/char/drm/drm_os_linux.h	2005-02-08 01:57:35 -08:00
@@ -96,9 +96,6 @@
 	__copy_to_user(arg1, arg2, arg3)
 #define DRM_GET_USER_UNCHECKED(val, uaddr)		\
 	__get_user(val, uaddr)
-#define DRM_PUT_USER_UNCHECKED(uaddr, val)		\
-	__put_user(val, uaddr)
-
 
 #define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data
 
diff -Nru a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
--- a/drivers/char/drm/radeon_drv.h	2005-01-27 00:51:20 -08:00
+++ b/drivers/char/drm/radeon_drv.h	2005-02-08 01:57:35 -08:00
@@ -1027,25 +1027,27 @@
 } while (0)
 
 
-#define OUT_RING_USER_TABLE( tab, sz ) do {			\
+#define OUT_RING_TABLE( tab, sz ) do {					\
 	int _size = (sz);					\
-	int __user *_tab = (tab);					\
+	int *_tab = (int *)(tab);				\
 								\
 	if (write + _size > mask) {				\
-		int i = (mask+1) - write;			\
-		if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write),	\
-				      _tab, i*4 ))		\
-			return DRM_ERR(EFAULT);		\
+		int _i = (mask+1) - write;			\
+		_size -= _i;					\
+		while (_i > 0 ) {				\
+			*(int *)(ring + write) = *_tab++;	\
+			write++;				\
+			_i--;					\
+		}						\
 		write = 0;					\
-		_size -= i;					\
-		_tab += i;					\
+		_tab += _i;					\
 	}							\
 								\
-	if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write),	\
-			               _tab, _size*4 ))		\
-		return DRM_ERR(EFAULT);			\
-								\
-	write += _size;						\
+	while (_size > 0) {					\
+		*(ring + write) = *_tab++;			\
+		write++;					\
+		_size--;					\
+	}							\
 	write &= mask;						\
 } while (0)
 
diff -Nru a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
--- a/drivers/char/drm/radeon_state.c	2005-01-27 00:51:20 -08:00
+++ b/drivers/char/drm/radeon_state.c	2005-02-08 01:57:35 -08:00
@@ -93,21 +93,6 @@
 	return 0;
 }
 
-static __inline__ int radeon_check_and_fixup_offset_user( drm_radeon_private_t *dev_priv,
-							  drm_file_t *filp_priv,
-							  u32 __user *offset ) {
-	u32 off;
-
-	DRM_GET_USER_UNCHECKED( off, offset );
-
-	if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &off ) )
-		return DRM_ERR( EINVAL );
-
-	DRM_PUT_USER_UNCHECKED( offset, off );
-
-	return 0;
-}
-
 static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv,
 						      drm_file_t *filp_priv,
 						      int id,
@@ -115,18 +100,18 @@
 	switch ( id ) {
 
 	case RADEON_EMIT_PP_MISC:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_RB3D_DEPTHOFFSET
-								 - RADEON_PP_MISC ) / 4] ) ) {
+		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
+						    &data[( RADEON_RB3D_DEPTHOFFSET
+							    - RADEON_PP_MISC ) / 4] ) ) {
 			DRM_ERROR( "Invalid depth buffer offset\n" );
 			return DRM_ERR( EINVAL );
 		}
 		break;
 
 	case RADEON_EMIT_PP_CNTL:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_RB3D_COLOROFFSET
-								 - RADEON_PP_CNTL ) / 4] ) ) {
+		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
+						    &data[( RADEON_RB3D_COLOROFFSET
+							    - RADEON_PP_CNTL ) / 4] ) ) {
 			DRM_ERROR( "Invalid colour buffer offset\n" );
 			return DRM_ERR( EINVAL );
 		}
@@ -138,8 +123,8 @@
 	case R200_EMIT_PP_TXOFFSET_3:
 	case R200_EMIT_PP_TXOFFSET_4:
 	case R200_EMIT_PP_TXOFFSET_5:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[0] ) ) {
+		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
+						    &data[0] ) ) {
 			DRM_ERROR( "Invalid R200 texture offset\n" );
 			return DRM_ERR( EINVAL );
 		}
@@ -148,9 +133,9 @@
 	case RADEON_EMIT_PP_TXFILTER_0:
 	case RADEON_EMIT_PP_TXFILTER_1:
 	case RADEON_EMIT_PP_TXFILTER_2:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_PP_TXOFFSET_0
-								 - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
+		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
+						    &data[( RADEON_PP_TXOFFSET_0
+							    - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
 			DRM_ERROR( "Invalid R100 texture offset\n" );
 			return DRM_ERR( EINVAL );
 		}
@@ -164,9 +149,8 @@
 	case R200_EMIT_PP_CUBIC_OFFSETS_5: {
 		int i;
 		for ( i = 0; i < 5; i++ ) {
-			if ( radeon_check_and_fixup_offset_user( dev_priv,
-								 filp_priv,
-								 &data[i] ) ) {
+			if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
+							    &data[i] ) ) {
 				DRM_ERROR( "Invalid R200 cubic texture offset\n" );
 				return DRM_ERR( EINVAL );
 			}
@@ -250,17 +234,11 @@
 						      drm_file_t *filp_priv,
 						      drm_radeon_cmd_buffer_t *cmdbuf,
 						      unsigned int *cmdsz ) {
-	u32 tmp[4];
-	u32 __user *cmd = (u32 __user *)cmdbuf->buf;
-
-	if ( DRM_COPY_FROM_USER_UNCHECKED( tmp, cmd, sizeof( tmp ) ) ) {
-		DRM_ERROR( "Failed to copy data from user space\n" );
-		return DRM_ERR( EFAULT );
-	}
+	u32 *cmd = (u32 *) cmdbuf->buf;
 
-	*cmdsz = 2 + ( ( tmp[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
+	*cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
 
-	if ( ( tmp[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
+	if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
 		DRM_ERROR( "Not a type 3 packet\n" );
 		return DRM_ERR( EINVAL );
 	}
@@ -271,32 +249,27 @@
 	}
 
 	/* Check client state and fix it up if necessary */
-	if ( tmp[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
+	if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
 		u32 offset;
 
-		if ( tmp[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
+		if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
 			      | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
-			offset = tmp[2] << 10;
+			offset = cmd[2] << 10;
 			if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
 				DRM_ERROR( "Invalid first packet offset\n" );
 				return DRM_ERR( EINVAL );
 			}
-			tmp[2] = ( tmp[2] & 0xffc00000 ) | offset >> 10;
+			cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10;
 		}
 
-		if ( ( tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
-		     ( tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
-			offset = tmp[3] << 10;
+		if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
+		     ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
+			offset = cmd[3] << 10;
 			if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
 				DRM_ERROR( "Invalid second packet offset\n" );
 				return DRM_ERR( EINVAL );
 			}
-			tmp[3] = ( tmp[3] & 0xffc00000 ) | offset >> 10;
-		}
-
-		if ( DRM_COPY_TO_USER_UNCHECKED( cmd, tmp, sizeof( tmp ) ) ) {
-			DRM_ERROR( "Failed to copy data to user space\n" );
-			return DRM_ERR( EFAULT );
+			cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10;
 		}
 	}
 
@@ -2473,7 +2446,7 @@
 {
 	int id = (int)header.packet.packet_id;
 	int sz, reg;
-	int __user *data = (int __user *)cmdbuf->buf;
+	int *data = (int *)cmdbuf->buf;
 	RING_LOCALS;
    
 	if (id >= RADEON_MAX_STATE_PACKETS)
@@ -2494,7 +2467,7 @@
 
 	BEGIN_RING(sz+1);
 	OUT_RING( CP_PACKET0( reg, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
+	OUT_RING_TABLE( data, sz );
 	ADVANCE_RING();
 
 	cmdbuf->buf += sz * sizeof(int);
@@ -2508,7 +2481,6 @@
 	drm_radeon_cmd_buffer_t *cmdbuf )
 {
 	int sz = header.scalars.count;
-	int __user *data = (int __user *)cmdbuf->buf;
 	int start = header.scalars.offset;
 	int stride = header.scalars.stride;
 	RING_LOCALS;
@@ -2517,7 +2489,7 @@
 	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
 	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
 	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
+	OUT_RING_TABLE( cmdbuf->buf, sz );
 	ADVANCE_RING();
 	cmdbuf->buf += sz * sizeof(int);
 	cmdbuf->bufsz -= sz * sizeof(int);
@@ -2532,7 +2504,6 @@
 	drm_radeon_cmd_buffer_t *cmdbuf )
 {
 	int sz = header.scalars.count;
-	int __user *data = (int __user *)cmdbuf->buf;
 	int start = ((unsigned int)header.scalars.offset) + 0x100;
 	int stride = header.scalars.stride;
 	RING_LOCALS;
@@ -2541,7 +2512,7 @@
 	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
 	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
 	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
+	OUT_RING_TABLE( cmdbuf->buf, sz );
 	ADVANCE_RING();
 	cmdbuf->buf += sz * sizeof(int);
 	cmdbuf->bufsz -= sz * sizeof(int);
@@ -2554,7 +2525,6 @@
 	drm_radeon_cmd_buffer_t *cmdbuf )
 {
 	int sz = header.vectors.count;
-	int __user *data = (int __user *)cmdbuf->buf;
 	int start = header.vectors.offset;
 	int stride = header.vectors.stride;
 	RING_LOCALS;
@@ -2563,7 +2533,7 @@
 	OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
 	OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
 	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
+	OUT_RING_TABLE( cmdbuf->buf, sz );
 	ADVANCE_RING();
 
 	cmdbuf->buf += sz * sizeof(int);
@@ -2578,7 +2548,6 @@
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	unsigned int cmdsz;
-	int __user *cmd = (int __user *)cmdbuf->buf;
 	int ret;
 	RING_LOCALS;
 
@@ -2591,7 +2560,7 @@
 	}
 
 	BEGIN_RING( cmdsz );
-	OUT_RING_USER_TABLE( cmd, cmdsz );
+	OUT_RING_TABLE( cmdbuf->buf, cmdsz );
 	ADVANCE_RING();
 
 	cmdbuf->buf += cmdsz * 4;
@@ -2608,7 +2577,6 @@
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_clip_rect_t box;
 	unsigned int cmdsz;
-	int __user *cmd = (int __user *)cmdbuf->buf;
 	int ret;
 	drm_clip_rect_t __user *boxes = cmdbuf->boxes;
 	int i = 0;
@@ -2627,7 +2595,7 @@
 
 	do {
 		if ( i < cmdbuf->nbox ) {
-			if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
+			if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) ))
 				return DRM_ERR(EFAULT);
 			/* FIXME The second and subsequent times round
 			 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -2650,7 +2618,7 @@
 		}
 		
 		BEGIN_RING( cmdsz );
-		OUT_RING_USER_TABLE( cmd, cmdsz );
+		OUT_RING_TABLE( cmdbuf->buf, cmdsz );
 		ADVANCE_RING();
 
 	} while ( ++i < cmdbuf->nbox );
@@ -2703,7 +2671,8 @@
 	int idx;
 	drm_radeon_cmd_buffer_t cmdbuf;
 	drm_radeon_cmd_header_t header;
-	int orig_nbox;
+	int orig_nbox, orig_bufsz;
+	char *kbuf=NULL;
 
 	LOCK_TEST_WITH_RETURN( dev, filp );
 
@@ -2720,24 +2689,29 @@
 	RING_SPACE_TEST_WITH_RETURN( dev_priv );
 	VB_AGE_TEST_WITH_RETURN( dev_priv );
 
+	if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) {
+		return DRM_ERR(EINVAL);
+	}
 
-	if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
-		return DRM_ERR(EFAULT);
-
-	if (cmdbuf.nbox &&
-	    DRM_VERIFYAREA_READ(cmdbuf.boxes, 
-			 cmdbuf.nbox * sizeof(drm_clip_rect_t)))
-		return DRM_ERR(EFAULT);
+	/* Allocate an in-kernel area and copy in the cmdbuf.  Do this to avoid
+	 * races between checking values and using those values in other code,
+	 * and simply to avoid a lot of function calls to copy in data.
+	 */
+	orig_bufsz = cmdbuf.bufsz;
+	if (orig_bufsz != 0) {
+		kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER);
+		if (kbuf == NULL)
+			return DRM_ERR(ENOMEM);
+		if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz))
+			return DRM_ERR(EFAULT);
+		cmdbuf.buf = kbuf;
+	}
 
 	orig_nbox = cmdbuf.nbox;
 
 	while ( cmdbuf.bufsz >= sizeof(header) ) {
-		
-		if (DRM_GET_USER_UNCHECKED( header.i, (int __user *)cmdbuf.buf )) {
-			DRM_ERROR("__get_user %p\n", cmdbuf.buf);
-			return DRM_ERR(EFAULT);
-		}
 
+		header.i = *(int *)cmdbuf.buf;
 		cmdbuf.buf += sizeof(header);
 		cmdbuf.bufsz -= sizeof(header);
 
@@ -2746,7 +2720,7 @@
 			DRM_DEBUG("RADEON_CMD_PACKET\n");
 			if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) {
 				DRM_ERROR("radeon_emit_packets failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2754,7 +2728,7 @@
 			DRM_DEBUG("RADEON_CMD_SCALARS\n");
 			if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
 				DRM_ERROR("radeon_emit_scalars failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2762,7 +2736,7 @@
 			DRM_DEBUG("RADEON_CMD_VECTORS\n");
 			if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
 				DRM_ERROR("radeon_emit_vectors failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2772,14 +2746,14 @@
 			if ( idx < 0 || idx >= dma->buf_count ) {
 				DRM_ERROR( "buffer index %d (of %d max)\n",
 					   idx, dma->buf_count - 1 );
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 
 			buf = dma->buflist[idx];
 			if ( buf->filp != filp || buf->pending ) {
 				DRM_ERROR( "bad buffer %p %p %d\n",
 					   buf->filp, filp, buf->pending);
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 
 			radeon_cp_discard_buffer( dev, buf );
@@ -2789,7 +2763,7 @@
 			DRM_DEBUG("RADEON_CMD_PACKET3\n");
 			if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) {
 				DRM_ERROR("radeon_emit_packet3 failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2797,7 +2771,7 @@
 			DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
 			if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) {
 				DRM_ERROR("radeon_emit_packet3_clip failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2805,7 +2779,7 @@
 			DRM_DEBUG("RADEON_CMD_SCALARS2\n");
 			if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
 				DRM_ERROR("radeon_emit_scalars2 failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 
@@ -2813,21 +2787,28 @@
 			DRM_DEBUG("RADEON_CMD_WAIT\n");
 			if (radeon_emit_wait( dev, header.wait.flags )) {
 				DRM_ERROR("radeon_emit_wait failed\n");
-				return DRM_ERR(EINVAL);
+				goto err;
 			}
 			break;
 		default:
 			DRM_ERROR("bad cmd_type %d at %p\n", 
 				  header.header.cmd_type,
 				  cmdbuf.buf - sizeof(header));
-			return DRM_ERR(EINVAL);
+			goto err;
 		}
 	}
 
+	if (orig_bufsz != 0)
+		drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
 
 	DRM_DEBUG("DONE\n");
 	COMMIT_RING();
 	return 0;
+
+err:
+	if (orig_bufsz != 0)
+		drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
+	return DRM_ERR(EINVAL);
 }
 
 
diff -Nru a/drivers/char/hvcs.c b/drivers/char/hvcs.c
--- a/drivers/char/hvcs.c	2005-01-07 21:44:12 -08:00
+++ b/drivers/char/hvcs.c	2005-02-04 17:23:03 -08:00
@@ -1363,6 +1363,7 @@
 
 	hvcs_tty_driver->driver_name = hvcs_driver_name;
 	hvcs_tty_driver->name = hvcs_device_node;
+	hvcs_tty_driver->devfs_name = hvcs_device_node;
 
 	/*
 	 * We'll let the system assign us a major number, indicated by leaving
diff -Nru a/drivers/char/mmtimer.c b/drivers/char/mmtimer.c
--- a/drivers/char/mmtimer.c	2004-11-18 23:03:12 -08:00
+++ b/drivers/char/mmtimer.c	2005-01-28 15:38:57 -08:00
@@ -36,9 +36,7 @@
 #include <asm/sn/intr.h>
 #include <asm/sn/shub_mmr.h>
 #include <asm/sn/nodepda.h>
-
-/* This is ugly and jbarnes has promised me to fix this later */
-#include "../../arch/ia64/sn/include/shubio.h"
+#include <asm/sn/shubio.h>
 
 MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>");
 MODULE_DESCRIPTION("SGI Altix RTC Timer");
diff -Nru a/drivers/char/mxser.c b/drivers/char/mxser.c
--- a/drivers/char/mxser.c	2004-12-26 22:04:22 -08:00
+++ b/drivers/char/mxser.c	2005-02-03 07:13:11 -08:00
@@ -556,7 +556,7 @@
 	info = &mxvar_table[n];
 	/*if (verbose) */  {
 		printk(KERN_DEBUG "        ttyM%d - ttyM%d ", n, n + hwconf->ports - 1);
-		printk(KERN_DEBUG " max. baud rate = %d bps.\n", hwconf->MaxCanSetBaudRate[0]);
+		printk(" max. baud rate = %d bps.\n", hwconf->MaxCanSetBaudRate[0]);
 	}
 
 	for (i = 0; i < hwconf->ports; i++, n++, info++) {
@@ -609,18 +609,12 @@
 	n = board * MXSER_PORTS_PER_BOARD;
 	info = &mxvar_table[n];
 
-	spin_lock_irqsave(&info->slock, flags);
 	retval = request_irq(hwconf->irq, mxser_interrupt, IRQ_T(info), "mxser", info);
 	if (retval) {
-		spin_unlock_irqrestore(&info->slock, flags);
 		printk(KERN_ERR "Board %d: %s", board, mxser_brdname[hwconf->board_type - 1]);
 		printk("  Request irq fail,IRQ (%d) may be conflit with another device.\n", info->irq);
 		return retval;
 	}
-
-	spin_unlock_irqrestore(&info->slock, flags);
-
-
 	return 0;
 }
 
@@ -2144,10 +2138,9 @@
 	mxvar_log.rxcnt[info->port] += cnt;
 	info->mon_data.rxcnt += cnt;
 	info->mon_data.up_rxcnt += cnt;
-
-	tty->ldisc.receive_buf(tty, tty->flip.char_buf, tty->flip.flag_buf, count);
 	spin_unlock_irqrestore(&info->slock, flags);
-
+	
+	tty_flip_buffer_push(tty);
 }
 
 static void mxser_transmit_chars(struct mxser_struct *info)
diff -Nru a/drivers/char/tty_io.c b/drivers/char/tty_io.c
--- a/drivers/char/tty_io.c	2005-01-30 22:33:45 -08:00
+++ b/drivers/char/tty_io.c	2005-02-07 08:37:06 -08:00
@@ -1156,8 +1156,8 @@
 	int i = index + driver->name_base;
 	/* ->name is initialized to "ttyp", but "tty" is expected */
 	sprintf(p, "%s%c%x",
-		driver->subtype == PTY_TYPE_SLAVE ? "pty" : driver->name,
-		ptychar[i >> 4 & 0xf], i & 0xf);
+			driver->subtype == PTY_TYPE_SLAVE ? "tty" : driver->name,
+			ptychar[i >> 4 & 0xf], i & 0xf);
 }
 
 static inline void tty_line_name(struct tty_driver *driver, int index, char *p)
diff -Nru a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
--- a/drivers/cpufreq/cpufreq.c	2005-01-20 21:02:15 -08:00
+++ b/drivers/cpufreq/cpufreq.c	2005-02-03 06:42:40 -08:00
@@ -900,9 +900,12 @@
 
 	if (cpufreq_driver->resume) {
 		ret = cpufreq_driver->resume(cpu_policy);
-		printk(KERN_ERR "cpufreq: resume failed in ->resume step on CPU %u\n", cpu_policy->cpu);
-		cpufreq_cpu_put(cpu_policy);
-		return (ret);
+		if (ret) {
+			printk(KERN_ERR "cpufreq: resume failed in ->resume "
+					"step on CPU %u\n", cpu_policy->cpu);
+			cpufreq_cpu_put(cpu_policy);
+			return ret;
+		}
 	}
 
 	if (!(cpufreq_driver->flags & CPUFREQ_CONST_LOOPS)) {
diff -Nru a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c
--- a/drivers/i2c/busses/i2c-sis5595.c	2004-10-19 16:46:13 -07:00
+++ b/drivers/i2c/busses/i2c-sis5595.c	2005-02-02 22:34:13 -08:00
@@ -181,9 +181,11 @@
 
 	if (force_addr) {
 		dev_info(&SIS5595_dev->dev, "forcing ISA address 0x%04X\n", sis5595_base);
-		if (!pci_write_config_word(SIS5595_dev, ACPI_BASE, sis5595_base))
+		if (pci_write_config_word(SIS5595_dev, ACPI_BASE, sis5595_base)
+		    != PCIBIOS_SUCCESSFUL)
 			goto error;
-		if (!pci_read_config_word(SIS5595_dev, ACPI_BASE, &a))
+		if (pci_read_config_word(SIS5595_dev, ACPI_BASE, &a)
+		    != PCIBIOS_SUCCESSFUL)
 			goto error;
 		if ((a & ~(SIS5595_EXTENT - 1)) != sis5595_base) {
 			/* doesn't work for some chips! */
@@ -192,13 +194,16 @@
 		}
 	}
 
-	if (!pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val))
+	if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val)
+	    != PCIBIOS_SUCCESSFUL)
 		goto error;
 	if ((val & 0x80) == 0) {
 		dev_info(&SIS5595_dev->dev, "enabling ACPI\n");
-		if (!pci_write_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, val | 0x80))
+		if (pci_write_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, val | 0x80)
+		    != PCIBIOS_SUCCESSFUL)
 			goto error;
-		if (!pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val))
+		if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val)
+		    != PCIBIOS_SUCCESSFUL)
 			goto error;
 		if ((val & 0x80) == 0) {
 			/* doesn't work for some chips? */
diff -Nru a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c
--- a/drivers/i2c/busses/i2c-viapro.c	2004-12-18 09:34:28 -08:00
+++ b/drivers/i2c/busses/i2c-viapro.c	2005-02-02 22:33:16 -08:00
@@ -45,6 +45,8 @@
 #include <linux/init.h>
 #include <asm/io.h>
 
+static struct pci_dev *vt596_pdev;
+
 #define SMBBA1	   	 0x90
 #define SMBBA2     	 0x80
 #define SMBBA3     	 0xD0
@@ -231,8 +233,8 @@
 			len = data->block[0];
 			if (len < 0)
 				len = 0;
-			if (len > 32)
-				len = 32;
+			if (len > I2C_SMBUS_BLOCK_MAX)
+				len = I2C_SMBUS_BLOCK_MAX;
 			outb_p(len, SMBHSTDAT0);
 			i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
 			for (i = 1; i <= len; i++)
@@ -266,6 +268,8 @@
 		break;
 	case VT596_BLOCK_DATA:
 		data->block[0] = inb_p(SMBHSTDAT0);
+		if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
+			data->block[0] = I2C_SMBUS_BLOCK_MAX;
 		i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
 		for (i = 1; i <= data->block[0]; i++)
 			data->block[i] = inb_p(SMBBLKDAT);
@@ -381,19 +385,23 @@
 	snprintf(vt596_adapter.name, I2C_NAME_SIZE,
 			"SMBus Via Pro adapter at %04x", vt596_smba);
 	
-	return i2c_add_adapter(&vt596_adapter);
+	vt596_pdev = pci_dev_get(pdev);
+	if (i2c_add_adapter(&vt596_adapter)) {
+		pci_dev_put(vt596_pdev);
+		vt596_pdev = NULL;
+	}
+
+	/* Always return failure here.  This is to allow other drivers to bind
+	 * to this pci device.  We don't really want to have control over the
+	 * pci device, we only wanted to read as few register values from it.
+	 */
+	return -ENODEV;
 
  release_region:
 	release_region(vt596_smba, 8);
 	return error;
 }
 
-static void __devexit vt596_remove(struct pci_dev *pdev)
-{
-	i2c_del_adapter(&vt596_adapter);
-	release_region(vt596_smba, 8);
-}
-
 static struct pci_device_id vt596_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596_3),
 	  .driver_data = SMBBA1 },
@@ -420,7 +428,6 @@
 	.name		= "vt596_smbus",
 	.id_table	= vt596_ids,
 	.probe		= vt596_probe,
-	.remove		= __devexit_p(vt596_remove),
 };
 
 static int __init i2c_vt596_init(void)
@@ -432,6 +439,12 @@
 static void __exit i2c_vt596_exit(void)
 {
 	pci_unregister_driver(&vt596_driver);
+	if (vt596_pdev != NULL) {
+		i2c_del_adapter(&vt596_adapter);
+		release_region(vt596_smba, 8);
+		pci_dev_put(vt596_pdev);
+		vt596_pdev = NULL;
+	}
 }
 
 MODULE_AUTHOR(
diff -Nru a/drivers/i2c/chips/ds1621.c b/drivers/i2c/chips/ds1621.c
--- a/drivers/i2c/chips/ds1621.c	2004-11-08 16:37:27 -08:00
+++ b/drivers/i2c/chips/ds1621.c	2005-02-02 22:35:48 -08:00
@@ -42,9 +42,8 @@
 /* Many DS1621 constants specified below */
 /* Config register used for detection         */
 /*  7    6    5    4    3    2    1    0      */
-/* |Done|THF |TLF |NVB | 1  | 0  |POL |1SHOT| */
-#define DS1621_REG_CONFIG_MASK		0x0C
-#define DS1621_REG_CONFIG_VAL		0x08
+/* |Done|THF |TLF |NVB | X  | X  |POL |1SHOT| */
+#define DS1621_REG_CONFIG_NVB		0x10
 #define DS1621_REG_CONFIG_POLARITY	0x02
 #define DS1621_REG_CONFIG_1SHOT		0x01
 #define DS1621_REG_CONFIG_DONE		0x80
@@ -55,6 +54,7 @@
 #define DS1621_REG_TEMP_MAX		0xA2 /* word, RW */
 #define DS1621_REG_CONF			0xAC /* byte, RW */
 #define DS1621_COM_START		0xEE /* no data */
+#define DS1621_COM_STOP			0x22 /* no data */
 
 /* The DS1621 configuration register */
 #define DS1621_ALARM_TEMP_HIGH		0x40
@@ -212,9 +212,13 @@
 
 	/* Now, we do the remaining detection. It is lousy. */
 	if (kind < 0) {
+		/* The NVB bit should be low if no EEPROM write has been 
+		   requested during the latest 10ms, which is highly 
+		   improbable in our case. */
 		conf = ds1621_read_value(new_client, DS1621_REG_CONF);
-		if ((conf & DS1621_REG_CONFIG_MASK) != DS1621_REG_CONFIG_VAL)
+		if (conf & DS1621_REG_CONFIG_NVB)
 			goto exit_free;
+		/* The 7 lowest bits of a temperature should always be 0. */
 		temp = ds1621_read_value(new_client, DS1621_REG_TEMP);
 		if (temp & 0x007f)
 			goto exit_free;
diff -Nru a/drivers/i2c/chips/it87.c b/drivers/i2c/chips/it87.c
--- a/drivers/i2c/chips/it87.c	2005-01-14 14:17:28 -08:00
+++ b/drivers/i2c/chips/it87.c	2005-02-02 22:34:21 -08:00
@@ -2,8 +2,8 @@
     it87.c - Part of lm_sensors, Linux kernel modules for hardware
              monitoring.
 
-    Supports: IT8705F  Super I/O chip w/LPC interface
-              IT8712F  Super I/O chip w/LPC interface & SMbus
+    Supports: IT8705F  Super I/O chip w/LPC interface & SMBus
+              IT8712F  Super I/O chip w/LPC interface & SMBus
               Sis950   A clone of the IT8705F
 
     Copyright (C) 2001 Chris Gauthron <chrisg@0-in.com> 
@@ -42,10 +42,8 @@
 
 
 /* Addresses to scan */
-static unsigned short normal_i2c[] = { 0x20, 0x21, 0x22, 0x23, 0x24,
-					0x25, 0x26, 0x27, 0x28, 0x29,
-					0x2a, 0x2b, 0x2c, 0x2d, 0x2e,
-					0x2f, I2C_CLIENT_END };
+static unsigned short normal_i2c[] = { 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d,
+					0x2e, 0x2f, I2C_CLIENT_END };
 static unsigned int normal_isa[] = { 0x0290, I2C_CLIENT_ISA_END };
 
 /* Insmod parameters */
diff -Nru a/drivers/i2c/chips/pc87360.c b/drivers/i2c/chips/pc87360.c
--- a/drivers/i2c/chips/pc87360.c	2004-12-10 10:39:34 -08:00
+++ b/drivers/i2c/chips/pc87360.c	2005-02-02 22:34:00 -08:00
@@ -795,8 +795,10 @@
 
 	/* Fan clock dividers may be needed before any data is read */
 	for (i = 0; i < data->fannr; i++) {
-		data->fan_status[i] = pc87360_read_value(data, LD_FAN,
-				      NO_BANK, PC87360_REG_FAN_STATUS(i));
+		if (FAN_CONFIG_MONITOR(data->fan_conf, i))
+			data->fan_status[i] = pc87360_read_value(data,
+					      LD_FAN, NO_BANK,
+					      PC87360_REG_FAN_STATUS(i));
 	}
 
 	if (init > 0) {
@@ -898,14 +900,27 @@
 	}
 
 	if (data->fannr) {
-		device_create_file(&new_client->dev, &dev_attr_fan1_input);
-		device_create_file(&new_client->dev, &dev_attr_fan2_input);
-		device_create_file(&new_client->dev, &dev_attr_fan1_min);
-		device_create_file(&new_client->dev, &dev_attr_fan2_min);
-		device_create_file(&new_client->dev, &dev_attr_fan1_div);
-		device_create_file(&new_client->dev, &dev_attr_fan2_div);
-		device_create_file(&new_client->dev, &dev_attr_fan1_status);
-		device_create_file(&new_client->dev, &dev_attr_fan2_status);
+		if (FAN_CONFIG_MONITOR(data->fan_conf, 0)) {
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan1_input);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan1_min);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan1_div);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan1_status);
+		}
+
+		if (FAN_CONFIG_MONITOR(data->fan_conf, 1)) {
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan2_input);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan2_min);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan2_div);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan2_status);
+		}
 
 		if (FAN_CONFIG_CONTROL(data->fan_conf, 0))
 			device_create_file(&new_client->dev, &dev_attr_pwm1);
@@ -913,10 +928,16 @@
 			device_create_file(&new_client->dev, &dev_attr_pwm2);
 	}
 	if (data->fannr == 3) {
-		device_create_file(&new_client->dev, &dev_attr_fan3_input);
-		device_create_file(&new_client->dev, &dev_attr_fan3_min);
-		device_create_file(&new_client->dev, &dev_attr_fan3_div);
-		device_create_file(&new_client->dev, &dev_attr_fan3_status);
+		if (FAN_CONFIG_MONITOR(data->fan_conf, 2)) {
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan3_input);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan3_min);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan3_div);
+			device_create_file(&new_client->dev,
+					   &dev_attr_fan3_status);
+		}
 
 		if (FAN_CONFIG_CONTROL(data->fan_conf, 2))
 			device_create_file(&new_client->dev, &dev_attr_pwm3);
diff -Nru a/drivers/i2c/chips/via686a.c b/drivers/i2c/chips/via686a.c
--- a/drivers/i2c/chips/via686a.c	2005-01-14 14:18:19 -08:00
+++ b/drivers/i2c/chips/via686a.c	2005-02-02 22:34:47 -08:00
@@ -815,20 +815,24 @@
                return -ENODEV;
        }
        normal_isa[0] = addr;
-       s_bridge = dev;
-       return i2c_add_driver(&via686a_driver);
-}
 
-static void __devexit via686a_pci_remove(struct pci_dev *dev)
-{
-       i2c_del_driver(&via686a_driver);
+	s_bridge = pci_dev_get(dev);
+	if (i2c_add_driver(&via686a_driver)) {
+		pci_dev_put(s_bridge);
+		s_bridge = NULL;
+	}
+
+	/* Always return failure here.  This is to allow other drivers to bind
+	 * to this pci device.  We don't really want to have control over the
+	 * pci device, we only wanted to read as few register values from it.
+	 */
+	return -ENODEV;
 }
 
 static struct pci_driver via686a_pci_driver = {
        .name		= "via686a",
        .id_table	= via686a_pci_ids,
        .probe		= via686a_pci_probe,
-       .remove		= __devexit_p(via686a_pci_remove),
 };
 
 static int __init sm_via686a_init(void)
@@ -838,7 +842,12 @@
 
 static void __exit sm_via686a_exit(void)
 {
-       pci_unregister_driver(&via686a_pci_driver);
+	pci_unregister_driver(&via686a_pci_driver);
+	if (s_bridge != NULL) {
+		i2c_del_driver(&via686a_driver);
+		pci_dev_put(s_bridge);
+		s_bridge = NULL;
+	}
 }
 
 MODULE_AUTHOR("Kyösti Mälkki <kmalkki@cc.hut.fi>, "
diff -Nru a/drivers/i2c/chips/w83781d.c b/drivers/i2c/chips/w83781d.c
--- a/drivers/i2c/chips/w83781d.c	2004-12-10 10:38:41 -08:00
+++ b/drivers/i2c/chips/w83781d.c	2005-02-02 22:34:25 -08:00
@@ -175,11 +175,6 @@
 						: (val)) / 1000, 0, 0xff))
 #define TEMP_FROM_REG(val)		(((val) & 0x80 ? (val)-0x100 : (val)) * 1000)
 
-#define AS99127_TEMP_ADD_TO_REG(val)	(SENSORS_LIMIT((((val) < 0 ? (val)+0x10000*250 \
-						: (val)) / 250) << 7, 0, 0xffff))
-#define AS99127_TEMP_ADD_FROM_REG(val)	((((val) & 0x8000 ? (val)-0x10000 : (val)) \
-						>> 7) * 250)
-
 #define ALARMS_FROM_REG(val)		(val)
 #define PWM_FROM_REG(val)		(val)
 #define PWM_TO_REG(val)			(SENSORS_LIMIT((val),0,255))
@@ -417,13 +412,8 @@
 { \
 	struct w83781d_data *data = w83781d_update_device(dev); \
 	if (nr >= 2) {	/* TEMP2 and TEMP3 */ \
-		if (data->type == as99127f) { \
-			return sprintf(buf,"%ld\n", \
-				(long)AS99127_TEMP_ADD_FROM_REG(data->reg##_add[nr-2])); \
-		} else { \
-			return sprintf(buf,"%d\n", \
-				LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
-		} \
+		return sprintf(buf,"%d\n", \
+			LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
 	} else {	/* TEMP1 */ \
 		return sprintf(buf,"%ld\n", (long)TEMP_FROM_REG(data->reg)); \
 	} \
@@ -442,11 +432,7 @@
 	val = simple_strtol(buf, NULL, 10); \
 	 \
 	if (nr >= 2) {	/* TEMP2 and TEMP3 */ \
-		if (data->type == as99127f) \
-			data->temp_##reg##_add[nr-2] = AS99127_TEMP_ADD_TO_REG(val); \
-		else \
-			data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
-		 \
+		data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
 		w83781d_write_value(client, W83781D_REG_TEMP_##REG(nr), \
 				data->temp_##reg##_add[nr-2]); \
 	} else {	/* TEMP1 */ \
diff -Nru a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c
--- a/drivers/ide/ide-disk.c	2005-01-04 09:39:25 -08:00
+++ b/drivers/ide/ide-disk.c	2005-02-02 16:38:38 -08:00
@@ -132,7 +132,7 @@
 	nsectors.all		= (u16) rq->nr_sectors;
 
 	if (hwif->no_lba48_dma && lba48 && dma) {
-		if (rq->sector + rq->nr_sectors > 1ULL << 28)
+		if (block + rq->nr_sectors > 1ULL << 28)
 			dma = 0;
 	}
 
@@ -253,8 +253,7 @@
 		/* FIXME: ->OUTBSYNC ? */
 		hwif->OUTB(command, IDE_COMMAND_REG);
 
-		pre_task_out_intr(drive, rq);
-		return ide_started;
+		return pre_task_out_intr(drive, rq);
 	}
 }
 EXPORT_SYMBOL_GPL(__ide_do_rw_disk);
diff -Nru a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
--- a/drivers/ide/ide-dma.c	2005-01-09 12:06:39 -08:00
+++ b/drivers/ide/ide-dma.c	2005-02-03 07:58:51 -08:00
@@ -227,7 +227,9 @@
  *	the PRD table that the IDE layer wants to be fed. The code
  *	knows about the 64K wrap bug in the CS5530.
  *
- *	Returns 0 if all went okay, returns 1 otherwise.
+ *	Returns the number of built PRD entries if all went okay,
+ *	returns 0 otherwise.
+ *
  *	May also be invoked from trm290.c
  */
  
@@ -631,7 +633,7 @@
 EXPORT_SYMBOL(__ide_dma_end);
 
 /* returns 1 if dma irq issued, 0 otherwise */
-int __ide_dma_test_irq (ide_drive_t *drive)
+static int __ide_dma_test_irq(ide_drive_t *drive)
 {
 	ide_hwif_t *hwif	= HWIF(drive);
 	u8 dma_stat		= hwif->INB(hwif->dma_status);
@@ -650,8 +652,6 @@
 			drive->name, __FUNCTION__);
 	return 0;
 }
-
-EXPORT_SYMBOL(__ide_dma_test_irq);
 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
 
 int __ide_dma_bad_drive (ide_drive_t *drive)
@@ -784,7 +784,7 @@
 /*
  * Needed for allowing full modular support of ide-driver
  */
-int ide_release_dma_engine (ide_hwif_t *hwif)
+static int ide_release_dma_engine(ide_hwif_t *hwif)
 {
 	if (hwif->dmatable_cpu) {
 		pci_free_consistent(hwif->pci_dev,
@@ -796,7 +796,7 @@
 	return 1;
 }
 
-int ide_release_iomio_dma (ide_hwif_t *hwif)
+static int ide_release_iomio_dma(ide_hwif_t *hwif)
 {
 	if ((hwif->dma_extra) && (hwif->channel == 0))
 		release_region((hwif->dma_base + 16), hwif->dma_extra);
@@ -820,7 +820,7 @@
 	return ide_release_iomio_dma(hwif);
 }
 
-int ide_allocate_dma_engine (ide_hwif_t *hwif)
+static int ide_allocate_dma_engine(ide_hwif_t *hwif)
 {
 	hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
 						  PRD_ENTRIES * PRD_BYTES,
@@ -830,14 +830,13 @@
 		return 0;
 
 	printk(KERN_ERR "%s: -- Error, unable to allocate%s DMA table(s).\n",
-		(hwif->dmatable_cpu == NULL) ? " CPU" : "",
-		hwif->cds->name);
+			hwif->cds->name, !hwif->dmatable_cpu ? " CPU" : "");
 
 	ide_release_dma_engine(hwif);
 	return 1;
 }
 
-int ide_mapped_mmio_dma (ide_hwif_t *hwif, unsigned long base, unsigned int ports)
+static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
 {
 	printk(KERN_INFO "    %s: MMIO-DMA ", hwif->name);
 
@@ -852,7 +851,7 @@
 	return 0;
 }
 
-int ide_iomio_dma (ide_hwif_t *hwif, unsigned long base, unsigned int ports)
+static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
 {
 	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx",
 		hwif->name, base, base + ports - 1);
@@ -881,10 +880,7 @@
 	return 0;
 }
 
-/*
- * 
- */
-int ide_dma_iobase (ide_hwif_t *hwif, unsigned long base, unsigned int ports)
+static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
 {
 	if (hwif->mmio == 2)
 		return ide_mapped_mmio_dma(hwif, base,ports);
diff -Nru a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
--- a/drivers/ide/ide-floppy.c	2005-01-04 09:39:25 -08:00
+++ b/drivers/ide/ide-floppy.c	2005-02-02 15:21:22 -08:00
@@ -585,7 +585,7 @@
 			count = min(bvec->bv_len, bcount);
 
 			data = bvec_kmap_irq(bvec, &flags);
-			atapi_input_bytes(drive, data, count);
+			drive->hwif->atapi_input_bytes(drive, data, count);
 			bvec_kunmap_irq(data, &flags);
 
 			bcount -= count;
@@ -619,7 +619,7 @@
 			count = min(bvec->bv_len, bcount);
 
 			data = bvec_kmap_irq(bvec, &flags);
-			atapi_output_bytes(drive, data, count);
+			drive->hwif->atapi_output_bytes(drive, data, count);
 			bvec_kunmap_irq(data, &flags);
 
 			bcount -= count;
diff -Nru a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c
--- a/drivers/ide/ide-io.c	2005-01-09 11:54:36 -08:00
+++ b/drivers/ide/ide-io.c	2005-02-03 06:19:43 -08:00
@@ -555,7 +555,7 @@
 
 	err = ide_dump_status(drive, msg, stat);
 
-	if (drive == NULL || (rq = HWGROUP(drive)->rq) == NULL)
+	if ((rq = HWGROUP(drive)->rq) == NULL)
 		return ide_stopped;
 
 	/* retry only "normal" I/O: */
@@ -933,6 +933,7 @@
 	if (timeout > WAIT_WORSTCASE)
 		timeout = WAIT_WORSTCASE;
 	drive->sleep = timeout + jiffies;
+	drive->sleeping = 1;
 }
 
 EXPORT_SYMBOL(ide_stall_queue);
@@ -972,18 +973,18 @@
 	}
 
 	do {
-		if ((!drive->sleep || time_after_eq(jiffies, drive->sleep))
+		if ((!drive->sleeping || time_after_eq(jiffies, drive->sleep))
 		    && !elv_queue_empty(drive->queue)) {
 			if (!best
-			 || (drive->sleep && (!best->sleep || 0 < (signed long)(best->sleep - drive->sleep)))
-			 || (!best->sleep && 0 < (signed long)(WAKEUP(best) - WAKEUP(drive))))
+			 || (drive->sleeping && (!best->sleeping || time_before(drive->sleep, best->sleep)))
+			 || (!best->sleeping && time_before(WAKEUP(drive), WAKEUP(best))))
 			{
 				if (!blk_queue_plugged(drive->queue))
 					best = drive;
 			}
 		}
 	} while ((drive = drive->next) != hwgroup->drive);
-	if (best && best->nice1 && !best->sleep && best != hwgroup->drive && best->service_time > WAIT_MIN_SLEEP) {
+	if (best && best->nice1 && !best->sleeping && best != hwgroup->drive && best->service_time > WAIT_MIN_SLEEP) {
 		long t = (signed long)(WAKEUP(best) - jiffies);
 		if (t >= WAIT_MIN_SLEEP) {
 		/*
@@ -992,10 +993,9 @@
 		 */
 			drive = best->next;
 			do {
-				if (!drive->sleep
-				/* FIXME: use time_before */
-				 && 0 < (signed long)(WAKEUP(drive) - (jiffies - best->service_time))
-				 && 0 < (signed long)((jiffies + t) - WAKEUP(drive)))
+				if (!drive->sleeping
+				 && time_before(jiffies - best->service_time, WAKEUP(drive))
+				 && time_before(WAKEUP(drive), jiffies + t))
 				{
 					ide_stall_queue(best, min_t(long, t, 10 * WAIT_MIN_SLEEP));
 					goto repeat;
@@ -1058,14 +1058,17 @@
 		hwgroup->busy = 1;
 		drive = choose_drive(hwgroup);
 		if (drive == NULL) {
-			unsigned long sleep = 0;
+			int sleeping = 0;
+			unsigned long sleep = 0; /* shut up, gcc */
 			hwgroup->rq = NULL;
 			drive = hwgroup->drive;
 			do {
-				if (drive->sleep && (!sleep || 0 < (signed long)(sleep - drive->sleep)))
+				if (drive->sleeping && (!sleeping || time_before(drive->sleep, sleep))) {
+					sleeping = 1;
 					sleep = drive->sleep;
+				}
 			} while ((drive = drive->next) != hwgroup->drive);
-			if (sleep) {
+			if (sleeping) {
 		/*
 		 * Take a short snooze, and then wake up this hwgroup again.
 		 * This gives other hwgroups on the same a chance to
@@ -1105,7 +1108,7 @@
 		}
 		hwgroup->hwif = hwif;
 		hwgroup->drive = drive;
-		drive->sleep = 0;
+		drive->sleeping = 0;
 		drive->service_start = jiffies;
 
 		if (blk_queue_plugged(drive->queue)) {
@@ -1311,7 +1314,7 @@
 			/* local CPU only,
 			 * as if we were handling an interrupt */
 			local_irq_disable();
-			if (hwgroup->poll_timeout != 0) {
+			if (hwgroup->polling) {
 				startstop = handler(drive);
 			} else if (drive_is_ready(drive)) {
 				if (drive->waiting_for_dma)
@@ -1439,8 +1442,7 @@
 		return IRQ_NONE;
 	}
 
-	if ((handler = hwgroup->handler) == NULL ||
-	    hwgroup->poll_timeout != 0) {
+	if ((handler = hwgroup->handler) == NULL || hwgroup->polling) {
 		/*
 		 * Not expecting an interrupt from this drive.
 		 * That means this could be:
diff -Nru a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c
--- a/drivers/ide/ide-iops.c	2005-01-06 19:03:04 -08:00
+++ b/drivers/ide/ide-iops.c	2005-02-03 06:19:43 -08:00
@@ -184,16 +184,6 @@
 
 EXPORT_SYMBOL(default_hwif_mmiops);
 
-void default_hwif_transport (ide_hwif_t *hwif)
-{
-	hwif->ata_input_data		= ata_input_data;
-	hwif->ata_output_data		= ata_output_data;
-	hwif->atapi_input_bytes		= atapi_input_bytes;
-	hwif->atapi_output_bytes	= atapi_output_bytes;
-}
-
-EXPORT_SYMBOL(default_hwif_transport);
-
 u32 ide_read_24 (ide_drive_t *drive)
 {
 	u8 hcyl = HWIF(drive)->INB(IDE_HCYL_REG);
@@ -202,8 +192,6 @@
 	return (hcyl<<16)|(lcyl<<8)|sect;
 }
 
-EXPORT_SYMBOL(ide_read_24);
-
 void SELECT_DRIVE (ide_drive_t *drive)
 {
 	if (HWIF(drive)->selectproc)
@@ -240,7 +228,7 @@
  * of the sector count register location, with interrupts disabled
  * to ensure that the reads all happen together.
  */
-void ata_vlb_sync (ide_drive_t *drive, unsigned long port)
+static void ata_vlb_sync(ide_drive_t *drive, unsigned long port)
 {
 	(void) HWIF(drive)->INB(port);
 	(void) HWIF(drive)->INB(port);
@@ -250,7 +238,7 @@
 /*
  * This is used for most PIO data transfers *from* the IDE interface
  */
-void ata_input_data (ide_drive_t *drive, void *buffer, u32 wcount)
+static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount)
 {
 	ide_hwif_t *hwif	= HWIF(drive);
 	u8 io_32bit		= drive->io_32bit;
@@ -272,7 +260,7 @@
 /*
  * This is used for most PIO data transfers *to* the IDE interface
  */
-void ata_output_data (ide_drive_t *drive, void *buffer, u32 wcount)
+static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount)
 {
 	ide_hwif_t *hwif	= HWIF(drive);
 	u8 io_32bit		= drive->io_32bit;
@@ -299,7 +287,7 @@
  * extra byte allocated for the buffer.
  */
 
-void atapi_input_bytes (ide_drive_t *drive, void *buffer, u32 bytecount)
+static void atapi_input_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
 {
 	ide_hwif_t *hwif = HWIF(drive);
 
@@ -316,9 +304,7 @@
 		hwif->INSW(IDE_DATA_REG, ((u8 *)buffer)+(bytecount & ~0x03), 1);
 }
 
-EXPORT_SYMBOL(atapi_input_bytes);
-
-void atapi_output_bytes (ide_drive_t *drive, void *buffer, u32 bytecount)
+static void atapi_output_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
 {
 	ide_hwif_t *hwif = HWIF(drive);
 
@@ -335,7 +321,15 @@
 		hwif->OUTSW(IDE_DATA_REG, ((u8*)buffer)+(bytecount & ~0x03), 1);
 }
 
-EXPORT_SYMBOL(atapi_output_bytes);
+void default_hwif_transport(ide_hwif_t *hwif)
+{
+	hwif->ata_input_data		= ata_input_data;
+	hwif->ata_output_data		= ata_output_data;
+	hwif->atapi_input_bytes		= atapi_input_bytes;
+	hwif->atapi_output_bytes	= atapi_output_bytes;
+}
+
+EXPORT_SYMBOL(default_hwif_transport);
 
 /*
  * Beginning of Taskfile OPCODE Library and feature sets.
@@ -437,6 +431,7 @@
 #endif
 }
 
+/* FIXME: exported for use by the USB storage (isd200.c) code only */
 EXPORT_SYMBOL(ide_fix_driveid);
 
 void ide_fixstring (u8 *s, const int bytecount, const int byteswap)
@@ -1028,14 +1023,14 @@
 			return ide_started;
 		}
 		/* end of polling */
-		hwgroup->poll_timeout = 0;
+		hwgroup->polling = 0;
 		printk("%s: ATAPI reset timed-out, status=0x%02x\n",
 				drive->name, stat);
 		/* do it the old fashioned way */
 		return do_reset1(drive, 1);
 	}
 	/* done polling */
-	hwgroup->poll_timeout = 0;
+	hwgroup->polling = 0;
 	return ide_stopped;
 }
 
@@ -1095,7 +1090,7 @@
 			printk("\n");
 		}
 	}
-	hwgroup->poll_timeout = 0;	/* done polling */
+	hwgroup->polling = 0;	/* done polling */
 	return ide_stopped;
 }
 
@@ -1112,7 +1107,7 @@
 #endif
 }
 
-void pre_reset (ide_drive_t *drive)
+static void pre_reset(ide_drive_t *drive)
 {
 	DRIVER(drive)->pre_reset(drive);
 
@@ -1170,6 +1165,7 @@
 		udelay (20);
 		hwif->OUTB(WIN_SRST, IDE_COMMAND_REG);
 		hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
+		hwgroup->polling = 1;
 		__ide_set_handler(drive, &atapi_reset_pollfunc, HZ/20, NULL);
 		spin_unlock_irqrestore(&ide_lock, flags);
 		return ide_started;
@@ -1210,6 +1206,7 @@
 	/* more than enough time */
 	udelay(10);
 	hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
+	hwgroup->polling = 1;
 	__ide_set_handler(drive, &reset_pollfunc, HZ/20, NULL);
 
 	/*
diff -Nru a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c
--- a/drivers/ide/ide-lib.c	2005-01-08 16:04:36 -08:00
+++ b/drivers/ide/ide-lib.c	2005-02-05 15:44:14 -08:00
@@ -570,6 +570,7 @@
 	atapi_error_t error;
 
 	status.all = stat;
+	error.all = 0;
 	local_irq_set(flags);
 	printk("%s: %s: status=0x%02x { ", drive->name, msg, stat);
 	if (status.b.bsy)
@@ -584,7 +585,7 @@
 		if (status.b.check)	printk("Error ");
 	}
 	printk("}\n");
-	if ((status.all & (status.b.bsy|status.b.check)) == status.b.check) {
+	if (status.b.check && !status.b.bsy) {
 		error.all = HWIF(drive)->INB(IDE_ERROR_REG);
 		printk("%s: %s: error=0x%02x { ", drive->name, msg, error.all);
 		if (error.b.ili)	printk("IllegalLengthIndication ");
diff -Nru a/drivers/ide/ide-pnp.c b/drivers/ide/ide-pnp.c
--- a/drivers/ide/ide-pnp.c	2004-06-15 09:31:45 -07:00
+++ b/drivers/ide/ide-pnp.c	2005-02-03 07:29:37 -08:00
@@ -21,7 +21,7 @@
 #include <linux/ide.h>
 
 /* Add your devices here :)) */
-struct pnp_device_id idepnp_devices[] = {
+static struct pnp_device_id idepnp_devices[] = {
   	/* Generic ESDI/IDE/ATA compatible hard disk controller */
 	{.id = "PNP0600", .driver_data = 0},
 	{.id = ""}
diff -Nru a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
--- a/drivers/ide/ide-probe.c	2005-01-12 06:01:25 -08:00
+++ b/drivers/ide/ide-probe.c	2005-02-05 10:42:46 -08:00
@@ -841,7 +841,11 @@
 	if (fixup)
 		fixup(hwif);
 
-	hwif_init(hwif);
+	if (!hwif_init(hwif)) {
+		printk(KERN_INFO "%s: failed to initialize IDE interface\n",
+				 hwif->name);
+		return -1;
+	}
 
 	if (hwif->present) {
 		u16 unit = 0;
@@ -1244,8 +1248,9 @@
 {
 	int old_irq, unit;
 
+	/* Return success if no device is connected */
 	if (!hwif->present)
-		return 0;
+		return 1;
 
 	if (!hwif->irq) {
 		if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET])))
diff -Nru a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c
--- a/drivers/ide/ide-tape.c	2004-10-20 01:37:15 -07:00
+++ b/drivers/ide/ide-tape.c	2005-02-02 17:09:29 -08:00
@@ -2439,7 +2439,7 @@
 			tape->dsc_polling_start = jiffies;
 			tape->dsc_polling_frequency = tape->best_dsc_rw_frequency;
 			tape->dsc_timeout = jiffies + IDETAPE_DSC_RW_TIMEOUT;
-		} else if ((signed long) (jiffies - tape->dsc_timeout) > 0) {
+		} else if (time_after(jiffies, tape->dsc_timeout)) {
 			printk(KERN_ERR "ide-tape: %s: DSC timeout\n",
 				tape->name);
 			if (rq->cmd[0] & REQ_IDETAPE_PC2) {
diff -Nru a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c
--- a/drivers/ide/ide-taskfile.c	2005-01-06 19:03:04 -08:00
+++ b/drivers/ide/ide-taskfile.c	2005-02-02 17:19:08 -08:00
@@ -851,8 +851,8 @@
 		hwif->OUTB(taskfile->high_cylinder, IDE_HCYL_REG);
 
         /*
-	 * (ks) In the flagged taskfile approch, we will used all specified
-	 * registers and the register value will not be changed. Except the
+	 * (ks) In the flagged taskfile approch, we will use all specified
+	 * registers and the register value will not be changed, except the
 	 * select bit (master/slave) in the drive_head register. We must make
 	 * sure that the desired drive is selected.
 	 */
diff -Nru a/drivers/ide/ide.c b/drivers/ide/ide.c
--- a/drivers/ide/ide.c	2005-01-20 21:02:09 -08:00
+++ b/drivers/ide/ide.c	2005-02-03 07:29:37 -08:00
@@ -333,7 +333,7 @@
  *	Returns a guessed speed in MHz.
  */
 
-int ide_system_bus_speed (void)
+static int ide_system_bus_speed(void)
 {
 	static struct pci_device_id pci_default[] = {
 		{ PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID) },
@@ -414,7 +414,7 @@
 #ifdef CONFIG_PROC_FS
 struct proc_dir_entry *proc_ide_root;
 
-ide_proc_entry_t generic_subdriver_entries[] = {
+static ide_proc_entry_t generic_subdriver_entries[] = {
 	{ "capacity",	S_IFREG|S_IRUGO,	proc_ide_read_capacity,	NULL },
 	{ NULL, 0, NULL, NULL }
 };
@@ -1675,7 +1675,7 @@
  *
  * Remember to update Documentation/ide.txt if you change something here.
  */
-int __init ide_setup (char *s)
+static int __init ide_setup(char *s)
 {
 	int i, vals[3];
 	ide_hwif_t *hwif;
@@ -2261,7 +2261,7 @@
 /*
  * This is gets invoked once during initialization, to set *everything* up
  */
-int __init ide_init (void)
+static int __init ide_init(void)
 {
 	printk(KERN_INFO "Uniform Multi-Platform E-IDE driver " REVISION "\n");
 	devfs_mk_dir("ide");
@@ -2308,7 +2308,7 @@
 }
 
 #ifdef MODULE
-char *options = NULL;
+static char *options = NULL;
 module_param(options, charp, 0);
 MODULE_LICENSE("GPL");
 
diff -Nru a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
--- a/drivers/ide/legacy/ide-cs.c	2005-01-15 14:31:03 -08:00
+++ b/drivers/ide/legacy/ide-cs.c	2005-02-03 07:29:37 -08:00
@@ -209,7 +209,7 @@
 #define CS_CHECK(fn, ret) \
 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 
-void ide_config(dev_link_t *link)
+static void ide_config(dev_link_t *link)
 {
     client_handle_t handle = link->handle;
     ide_info_t *info = link->priv;
diff -Nru a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
--- a/drivers/ide/pci/Makefile	2004-03-16 12:49:40 -08:00
+++ b/drivers/ide/pci/Makefile	2005-02-02 16:19:50 -08:00
@@ -1,5 +1,4 @@
 
-obj-$(CONFIG_BLK_DEV_ADMA100)		+= adma100.o
 obj-$(CONFIG_BLK_DEV_AEC62XX)		+= aec62xx.o
 obj-$(CONFIG_BLK_DEV_ALI15X3)		+= alim15x3.o
 obj-$(CONFIG_BLK_DEV_AMD74XX)		+= amd74xx.o
diff -Nru a/drivers/ide/pci/adma100.c b/drivers/ide/pci/adma100.c
--- a/drivers/ide/pci/adma100.c	2003-02-18 10:06:19 -08:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,30 +0,0 @@
-/*
- *  linux/drivers/ide/pci/adma100.c -- basic support for Pacific Digital ADMA-100 boards
- *
- *     Created 09 Apr 2002 by Mark Lord
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-#include <linux/mm.h>
-#include <linux/blkdev.h>
-#include <linux/hdreg.h>
-#include <linux/ide.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-
-void __init ide_init_adma100 (ide_hwif_t *hwif)
-{
-	unsigned long  phy_admctl = pci_resource_start(hwif->pci_dev, 4) + 0x80 + (hwif->channel * 0x20);
-	void *v_admctl;
-
-	hwif->autodma = 0;		// not compatible with normal IDE DMA transfers
-	hwif->dma_base = 0;		// disable DMA completely
-	hwif->io_ports[IDE_CONTROL_OFFSET] += 4;	// chip needs offset of 6 instead of 2
-	v_admctl = ioremap_nocache(phy_admctl, 1024);	// map config regs, so we can turn on drive IRQs
-	*((unsigned short *)v_admctl) &= 3;		// enable aIEN; preserve PIO mode
-	iounmap(v_admctl);				// all done; unmap config regs
-}
diff -Nru a/drivers/ide/pci/adma100.h b/drivers/ide/pci/adma100.h
--- a/drivers/ide/pci/adma100.h	2004-05-20 10:41:38 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,28 +0,0 @@
-#ifndef ADMA_100_H
-#define ADMA_100_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-extern void init_setup_pdcadma(struct pci_dev *, ide_pci_device_t *);
-extern unsigned int init_chipset_pdcadma(struct pci_dev *, const char *);
-extern void init_hwif_pdcadma(ide_hwif_t *);
-extern void init_dma_pdcadma(ide_hwif_t *, unsigned long);
-
-static ide_pci_device_t pdcadma_chipsets[] __devinitdata = {
-	{
-		.vendor		= PCI_VENDOR_ID_PDC,
-		.device		= PCI_DEVICE_ID_PDC_1841,
-		.name		= "ADMA100",
-		.init_setup	= init_setup_pdcadma,
-		.init_chipset	= init_chipset_pdcadma,
-		.init_hwif	= init_hwif_pdcadma,
-		.init_dma	= init_dma_pdcadma,
-		.channels	= 2,
-		.autodma	= NODMA,
-		.bootable	= OFF_BOARD,
-	}
-}
-
-#endif /* ADMA_100_H */
diff -Nru a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
--- a/drivers/ide/pci/aec62xx.c	2004-12-29 14:58:32 -08:00
+++ b/drivers/ide/pci/aec62xx.c	2005-02-05 16:13:31 -08:00
@@ -16,7 +16,54 @@
 
 #include <asm/io.h>
 
-#include "aec62xx.h"
+struct chipset_bus_clock_list_entry {
+	u8 xfer_speed;
+	u8 chipset_settings;
+	u8 ultra_settings;
+};
+
+static struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
+	{	XFER_UDMA_6,	0x31,	0x07	},
+	{	XFER_UDMA_5,	0x31,	0x06	},
+	{	XFER_UDMA_4,	0x31,	0x05	},
+	{	XFER_UDMA_3,	0x31,	0x04	},
+	{	XFER_UDMA_2,	0x31,	0x03	},
+	{	XFER_UDMA_1,	0x31,	0x02	},
+	{	XFER_UDMA_0,	0x31,	0x01	},
+
+	{	XFER_MW_DMA_2,	0x31,	0x00	},
+	{	XFER_MW_DMA_1,	0x31,	0x00	},
+	{	XFER_MW_DMA_0,	0x0a,	0x00	},
+	{	XFER_PIO_4,	0x31,	0x00	},
+	{	XFER_PIO_3,	0x33,	0x00	},
+	{	XFER_PIO_2,	0x08,	0x00	},
+	{	XFER_PIO_1,	0x0a,	0x00	},
+	{	XFER_PIO_0,	0x00,	0x00	},
+	{	0,		0x00,	0x00	}
+};
+
+static struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
+	{	XFER_UDMA_6,	0x41,	0x06	},
+	{	XFER_UDMA_5,	0x41,	0x05	},
+	{	XFER_UDMA_4,	0x41,	0x04	},
+	{	XFER_UDMA_3,	0x41,	0x03	},
+	{	XFER_UDMA_2,	0x41,	0x02	},
+	{	XFER_UDMA_1,	0x41,	0x01	},
+	{	XFER_UDMA_0,	0x41,	0x01	},
+
+	{	XFER_MW_DMA_2,	0x41,	0x00	},
+	{	XFER_MW_DMA_1,	0x42,	0x00	},
+	{	XFER_MW_DMA_0,	0x7a,	0x00	},
+	{	XFER_PIO_4,	0x41,	0x00	},
+	{	XFER_PIO_3,	0x43,	0x00	},
+	{	XFER_PIO_2,	0x78,	0x00	},
+	{	XFER_PIO_1,	0x7a,	0x00	},
+	{	XFER_PIO_0,	0x70,	0x00	},
+	{	0,		0x00,	0x00	}
+};
+
+#define BUSCLOCK(D)	\
+	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
 
 #if 0
 		if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
@@ -101,8 +148,7 @@
 	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
-	SPLIT_BYTE(tmp0,tmp1,tmp2);
-	MAKE_WORD(d_conf,tmp1,tmp2);
+	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 
 	tmp1 = 0x00;
@@ -342,6 +388,58 @@
 
 	return ide_setup_pci_device(dev, d);
 }
+
+static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
+	{	/* 0 */
+		.name		= "AEC6210",
+		.init_setup	= init_setup_aec62xx,
+		.init_chipset	= init_chipset_aec62xx,
+		.init_hwif	= init_hwif_aec62xx,
+		.init_dma	= init_dma_aec62xx,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
+		.bootable	= OFF_BOARD,
+	},{	/* 1 */
+		.name		= "AEC6260",
+		.init_setup	= init_setup_aec62xx,
+		.init_chipset	= init_chipset_aec62xx,
+		.init_hwif	= init_hwif_aec62xx,
+		.init_dma	= init_dma_aec62xx,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 2 */
+		.name		= "AEC6260R",
+		.init_setup	= init_setup_aec62xx,
+		.init_chipset	= init_chipset_aec62xx,
+		.init_hwif	= init_hwif_aec62xx,
+		.init_dma	= init_dma_aec62xx,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
+		.bootable	= NEVER_BOARD,
+	},{	/* 3 */
+		.name		= "AEC6X80",
+		.init_setup	= init_setup_aec6x80,
+		.init_chipset	= init_chipset_aec62xx,
+		.init_hwif	= init_hwif_aec62xx,
+		.init_dma	= init_dma_aec62xx,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 4 */
+		.name		= "AEC6X80R",
+		.init_setup	= init_setup_aec6x80,
+		.init_chipset	= init_chipset_aec62xx,
+		.init_hwif	= init_hwif_aec62xx,
+		.init_dma	= init_dma_aec62xx,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
+		.bootable	= OFF_BOARD,
+	}
+};
 
 /**
  *	aec62xx_init_one	-	called when a AEC is found
diff -Nru a/drivers/ide/pci/aec62xx.h b/drivers/ide/pci/aec62xx.h
--- a/drivers/ide/pci/aec62xx.h	2004-12-29 14:58:32 -08:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,122 +0,0 @@
-#ifndef AEC62XX_H
-#define AEC62XX_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-struct chipset_bus_clock_list_entry {
-	byte		xfer_speed;
-	byte		chipset_settings;
-	byte		ultra_settings;
-};
-
-static struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
-	{	XFER_UDMA_6,	0x31,	0x07	},
-	{	XFER_UDMA_5,	0x31,	0x06	},
-	{	XFER_UDMA_4,	0x31,	0x05	},
-	{	XFER_UDMA_3,	0x31,	0x04	},
-	{	XFER_UDMA_2,	0x31,	0x03	},
-	{	XFER_UDMA_1,	0x31,	0x02	},
-	{	XFER_UDMA_0,	0x31,	0x01	},
-
-	{	XFER_MW_DMA_2,	0x31,	0x00	},
-	{	XFER_MW_DMA_1,	0x31,	0x00	},
-	{	XFER_MW_DMA_0,	0x0a,	0x00	},
-	{	XFER_PIO_4,	0x31,	0x00	},
-	{	XFER_PIO_3,	0x33,	0x00	},
-	{	XFER_PIO_2,	0x08,	0x00	},
-	{	XFER_PIO_1,	0x0a,	0x00	},
-	{	XFER_PIO_0,	0x00,	0x00	},
-	{	0,		0x00,	0x00	}
-};
-
-static struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
-	{	XFER_UDMA_6,	0x41,	0x06	},
-	{	XFER_UDMA_5,	0x41,	0x05	},
-	{	XFER_UDMA_4,	0x41,	0x04	},
-	{	XFER_UDMA_3,	0x41,	0x03	},
-	{	XFER_UDMA_2,	0x41,	0x02	},
-	{	XFER_UDMA_1,	0x41,	0x01	},
-	{	XFER_UDMA_0,	0x41,	0x01	},
-
-	{	XFER_MW_DMA_2,	0x41,	0x00	},
-	{	XFER_MW_DMA_1,	0x42,	0x00	},
-	{	XFER_MW_DMA_0,	0x7a,	0x00	},
-	{	XFER_PIO_4,	0x41,	0x00	},
-	{	XFER_PIO_3,	0x43,	0x00	},
-	{	XFER_PIO_2,	0x78,	0x00	},
-	{	XFER_PIO_1,	0x7a,	0x00	},
-	{	XFER_PIO_0,	0x70,	0x00	},
-	{	0,		0x00,	0x00	}
-};
-
-#ifndef SPLIT_BYTE
-#define SPLIT_BYTE(B,H,L)	((H)=(B>>4), (L)=(B-((B>>4)<<4)))
-#endif
-#ifndef MAKE_WORD
-#define MAKE_WORD(W,HB,LB)	((W)=((HB<<8)+LB))
-#endif
-
-#define BUSCLOCK(D)	\
-	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
-
-static int init_setup_aec6x80(struct pci_dev *, ide_pci_device_t *);
-static int init_setup_aec62xx(struct pci_dev *, ide_pci_device_t *);
-static unsigned int init_chipset_aec62xx(struct pci_dev *, const char *);
-static void init_hwif_aec62xx(ide_hwif_t *);
-static void init_dma_aec62xx(ide_hwif_t *, unsigned long);
-
-static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
-	{	/* 0 */
-		.name		= "AEC6210",
-		.init_setup	= init_setup_aec62xx,
-		.init_chipset	= init_chipset_aec62xx,
-		.init_hwif	= init_hwif_aec62xx,
-		.init_dma	= init_dma_aec62xx,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
-		.bootable	= OFF_BOARD,
-	},{	/* 1 */
-		.name		= "AEC6260",
-		.init_setup	= init_setup_aec62xx,
-		.init_chipset	= init_chipset_aec62xx,
-		.init_hwif	= init_hwif_aec62xx,
-		.init_dma	= init_dma_aec62xx,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= OFF_BOARD,
-	},{	/* 2 */
-		.name		= "AEC6260R",
-		.init_setup	= init_setup_aec62xx,
-		.init_chipset	= init_chipset_aec62xx,
-		.init_hwif	= init_hwif_aec62xx,
-		.init_dma	= init_dma_aec62xx,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
-		.bootable	= NEVER_BOARD,
-	},{	/* 3 */
-		.name		= "AEC6X80",
-		.init_setup	= init_setup_aec6x80,
-		.init_chipset	= init_chipset_aec62xx,
-		.init_hwif	= init_hwif_aec62xx,
-		.init_dma	= init_dma_aec62xx,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= OFF_BOARD,
-	},{	/* 4 */
-		.name		= "AEC6X80R",
-		.init_setup	= init_setup_aec6x80,
-		.init_chipset	= init_chipset_aec62xx,
-		.init_hwif	= init_hwif_aec62xx,
-		.init_dma	= init_dma_aec62xx,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
-		.bootable	= OFF_BOARD,
-	}
-};
-
-#endif /* AEC62XX_H */
diff -Nru a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
--- a/drivers/ide/pci/cmd64x.c	2004-12-29 14:58:32 -08:00
+++ b/drivers/ide/pci/cmd64x.c	2005-02-05 16:20:47 -08:00
@@ -25,7 +25,56 @@
 
 #include <asm/io.h>
 
-#include "cmd64x.h"
+#define DISPLAY_CMD64X_TIMINGS
+
+#define CMD_DEBUG 0
+
+#if CMD_DEBUG
+#define cmdprintk(x...)	printk(x)
+#else
+#define cmdprintk(x...)
+#endif
+
+/*
+ * CMD64x specific registers definition.
+ */
+#define CFR		0x50
+#define   CFR_INTR_CH0		0x02
+#define CNTRL		0x51
+#define	  CNTRL_DIS_RA0		0x40
+#define   CNTRL_DIS_RA1		0x80
+#define	  CNTRL_ENA_2ND		0x08
+
+#define	CMDTIM		0x52
+#define	ARTTIM0		0x53
+#define	DRWTIM0		0x54
+#define ARTTIM1 	0x55
+#define DRWTIM1		0x56
+#define ARTTIM23	0x57
+#define   ARTTIM23_DIS_RA2	0x04
+#define   ARTTIM23_DIS_RA3	0x08
+#define   ARTTIM23_INTR_CH1	0x10
+#define ARTTIM2		0x57
+#define ARTTIM3		0x57
+#define DRWTIM23	0x58
+#define DRWTIM2		0x58
+#define BRST		0x59
+#define DRWTIM3		0x5b
+
+#define BMIDECR0	0x70
+#define MRDMODE		0x71
+#define   MRDMODE_INTR_CH0	0x04
+#define   MRDMODE_INTR_CH1	0x08
+#define   MRDMODE_BLK_CH0	0x10
+#define   MRDMODE_BLK_CH1	0x20
+#define BMIDESR0	0x72
+#define UDIDETCR0	0x73
+#define DTPR0		0x74
+#define BMIDECR1	0x78
+#define BMIDECSR	0x79
+#define BMIDESR1	0x7A
+#define UDIDETCR1	0x7B
+#define DTPR1		0x7C
 
 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
 #include <linux/stat.h>
@@ -706,6 +755,39 @@
 	hwif->drives[0].autodma = hwif->autodma;
 	hwif->drives[1].autodma = hwif->autodma;
 }
+
+static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
+	{	/* 0 */
+		.name		= "CMD643",
+		.init_chipset	= init_chipset_cmd64x,
+		.init_hwif	= init_hwif_cmd64x,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 1 */
+		.name		= "CMD646",
+		.init_chipset	= init_chipset_cmd64x,
+		.init_hwif	= init_hwif_cmd64x,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
+		.bootable	= ON_BOARD,
+	},{	/* 2 */
+		.name		= "CMD648",
+		.init_chipset	= init_chipset_cmd64x,
+		.init_hwif	= init_hwif_cmd64x,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 3 */
+		.name		= "CMD649",
+		.init_chipset	= init_chipset_cmd64x,
+		.init_hwif	= init_hwif_cmd64x,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	}
+};
 
 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 {
diff -Nru a/drivers/ide/pci/cmd64x.h b/drivers/ide/pci/cmd64x.h
--- a/drivers/ide/pci/cmd64x.h	2004-10-10 08:44:05 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,95 +0,0 @@
-#ifndef CMD64X_H
-#define CMD64X_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-#define DISPLAY_CMD64X_TIMINGS
-
-#define CMD_DEBUG 0
-
-#if CMD_DEBUG
-#define cmdprintk(x...)	printk(x)
-#else
-#define cmdprintk(x...)
-#endif
-
-/*
- * CMD64x specific registers definition.
- */
-#define CFR		0x50
-#define   CFR_INTR_CH0		0x02
-#define CNTRL		0x51
-#define	  CNTRL_DIS_RA0		0x40
-#define   CNTRL_DIS_RA1		0x80
-#define	  CNTRL_ENA_2ND		0x08
-
-#define	CMDTIM		0x52
-#define	ARTTIM0		0x53
-#define	DRWTIM0		0x54
-#define ARTTIM1 	0x55
-#define DRWTIM1		0x56
-#define ARTTIM23	0x57
-#define   ARTTIM23_DIS_RA2	0x04
-#define   ARTTIM23_DIS_RA3	0x08
-#define   ARTTIM23_INTR_CH1	0x10
-#define ARTTIM2		0x57
-#define ARTTIM3		0x57
-#define DRWTIM23	0x58
-#define DRWTIM2		0x58
-#define BRST		0x59
-#define DRWTIM3		0x5b
-
-#define BMIDECR0	0x70
-#define MRDMODE		0x71
-#define   MRDMODE_INTR_CH0	0x04
-#define   MRDMODE_INTR_CH1	0x08
-#define   MRDMODE_BLK_CH0	0x10
-#define   MRDMODE_BLK_CH1	0x20
-#define BMIDESR0	0x72
-#define UDIDETCR0	0x73
-#define DTPR0		0x74
-#define BMIDECR1	0x78
-#define BMIDECSR	0x79
-#define BMIDESR1	0x7A
-#define UDIDETCR1	0x7B
-#define DTPR1		0x7C
-
-static unsigned int init_chipset_cmd64x(struct pci_dev *, const char *);
-static void init_hwif_cmd64x(ide_hwif_t *);
-
-static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
-	{	/* 0 */
-		.name		= "CMD643",
-		.init_chipset	= init_chipset_cmd64x,
-		.init_hwif	= init_hwif_cmd64x,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 1 */
-		.name		= "CMD646",
-		.init_chipset	= init_chipset_cmd64x,
-		.init_hwif	= init_hwif_cmd64x,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
-		.bootable	= ON_BOARD,
-	},{	/* 2 */
-		.name		= "CMD648",
-		.init_chipset	= init_chipset_cmd64x,
-		.init_hwif	= init_hwif_cmd64x,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	},{
-		.name		= "CMD649",
-		.init_chipset	= init_chipset_cmd64x,
-		.init_hwif	= init_hwif_cmd64x,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	}
-};
-
-#endif /* CMD64X_H */
diff -Nru a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
--- a/drivers/ide/pci/cy82c693.c	2004-12-29 14:58:32 -08:00
+++ b/drivers/ide/pci/cy82c693.c	2005-02-05 16:34:02 -08:00
@@ -54,7 +54,64 @@
 
 #include <asm/io.h>
 
-#include "cy82c693.h"
+/* the current version */
+#define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
+
+/*
+ *	The following are used to debug the driver.
+ */
+#define CY82C693_DEBUG_LOGS	0
+#define CY82C693_DEBUG_INFO	0
+
+/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
+#undef CY82C693_SETDMA_CLOCK
+
+/*
+ *	NOTE: the value for busmaster timeout is tricky and I got it by
+ *	trial and error!  By using a to low value will cause DMA timeouts
+ *	and drop IDE performance, and by using a to high value will cause
+ *	audio playback to scatter.
+ *	If you know a better value or how to calc it, please let me know.
+ */
+
+/* twice the value written in cy82c693ub datasheet */
+#define BUSMASTER_TIMEOUT	0x50
+/*
+ * the value above was tested on my machine and it seems to work okay
+ */
+
+/* here are the offset definitions for the registers */
+#define CY82_IDE_CMDREG		0x04
+#define CY82_IDE_ADDRSETUP	0x48
+#define CY82_IDE_MASTER_IOR	0x4C
+#define CY82_IDE_MASTER_IOW	0x4D
+#define CY82_IDE_SLAVE_IOR	0x4E
+#define CY82_IDE_SLAVE_IOW	0x4F
+#define CY82_IDE_MASTER_8BIT	0x50
+#define CY82_IDE_SLAVE_8BIT	0x51
+
+#define CY82_INDEX_PORT		0x22
+#define CY82_DATA_PORT		0x23
+
+#define CY82_INDEX_CTRLREG1	0x01
+#define CY82_INDEX_CHANNEL0	0x30
+#define CY82_INDEX_CHANNEL1	0x31
+#define CY82_INDEX_TIMEOUT	0x32
+
+/* the max PIO mode - from datasheet */
+#define CY82C693_MAX_PIO	4
+
+/* the min and max PCI bus speed in MHz - from datasheet */
+#define CY82C963_MIN_BUS_SPEED	25
+#define CY82C963_MAX_BUS_SPEED	33
+
+/* the struct for the PIO mode timings */
+typedef struct pio_clocks_s {
+	u8	address_time;	/* Address setup (clocks) */
+	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
+	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
+	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
+} pio_clocks_t;
 
 /*
  * calc clocks using bus_speed
@@ -421,6 +478,18 @@
 		hwif->channel = 1;
 	}
 }
+
+static ide_pci_device_t cy82c693_chipsets[] __devinitdata = {
+	{	/* 0 */
+		.name		= "CY82C693",
+		.init_chipset	= init_chipset_cy82c693,
+		.init_iops	= init_iops_cy82c693,
+		.init_hwif	= init_hwif_cy82c693,
+		.channels	= 1,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	}
+};
 
 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 {
diff -Nru a/drivers/ide/pci/cy82c693.h b/drivers/ide/pci/cy82c693.h
--- a/drivers/ide/pci/cy82c693.h	2004-06-01 12:04:38 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,83 +0,0 @@
-#ifndef CY82C693_H
-#define CY82C693_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-/* the current version */
-#define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
-
-/*
- *	The following are used to debug the driver.
- */
-#define	CY82C693_DEBUG_LOGS	0
-#define	CY82C693_DEBUG_INFO	0
-
-/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
-#undef CY82C693_SETDMA_CLOCK
-
-/*
- *	NOTE: the value for busmaster timeout is tricky and I got it by
- *	 trial and error!  By using a to low value will cause DMA timeouts
- *	 and drop IDE performance, and by using a to high value will cause
- *	 audio playback to scatter.
- *	 If you know a better value or how to calc it, please let me know.
- */
-
-/* twice the value written in cy82c693ub datasheet */
-#define BUSMASTER_TIMEOUT	0x50
-/*
- * the value above was tested on my machine and it seems to work okay
- */
-
-/* here are the offset definitions for the registers */
-#define CY82_IDE_CMDREG		0x04
-#define CY82_IDE_ADDRSETUP	0x48
-#define CY82_IDE_MASTER_IOR	0x4C	
-#define CY82_IDE_MASTER_IOW	0x4D	
-#define CY82_IDE_SLAVE_IOR	0x4E	
-#define CY82_IDE_SLAVE_IOW	0x4F
-#define CY82_IDE_MASTER_8BIT	0x50	
-#define CY82_IDE_SLAVE_8BIT	0x51	
-
-#define CY82_INDEX_PORT		0x22
-#define CY82_DATA_PORT		0x23
-
-#define CY82_INDEX_CTRLREG1	0x01
-#define CY82_INDEX_CHANNEL0	0x30
-#define CY82_INDEX_CHANNEL1	0x31
-#define CY82_INDEX_TIMEOUT	0x32
-
-/* the max PIO mode - from datasheet */
-#define CY82C693_MAX_PIO	4
-
-/* the min and max PCI bus speed in MHz - from datasheet */
-#define CY82C963_MIN_BUS_SPEED	25
-#define CY82C963_MAX_BUS_SPEED	33
-
-/* the struct for the PIO mode timings */
-typedef struct pio_clocks_s {
-        u8	address_time;	/* Address setup (clocks) */
-	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
-	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
-	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
-} pio_clocks_t;
-
-static unsigned int init_chipset_cy82c693(struct pci_dev *, const char *);
-static void init_hwif_cy82c693(ide_hwif_t *);
-static void init_iops_cy82c693(ide_hwif_t *);
-
-static ide_pci_device_t cy82c693_chipsets[] __devinitdata = {
-	{	/* 0 */
-		.name		= "CY82C693",
-		.init_chipset	= init_chipset_cy82c693,
-		.init_iops	= init_iops_cy82c693,
-		.init_hwif	= init_hwif_cy82c693,
-		.channels	= 1,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	}
-};
-
-#endif /* CY82C693_H */
diff -Nru a/drivers/ide/pci/generic.c b/drivers/ide/pci/generic.c
--- a/drivers/ide/pci/generic.c	2004-12-30 11:27:07 -08:00
+++ b/drivers/ide/pci/generic.c	2005-02-05 17:00:20 -08:00
@@ -39,13 +39,6 @@
 
 #include <asm/io.h>
 
-#include "generic.h"
-
-static unsigned int __devinit init_chipset_generic (struct pci_dev *dev, const char *name)
-{
-	return 0;
-}
-
 static void __devinit init_hwif_generic (ide_hwif_t *hwif)
 {
 	switch(hwif->pci_dev->device) {
@@ -82,6 +75,89 @@
 	}
 	return 0;
 #endif	
+
+static ide_pci_device_t generic_chipsets[] __devinitdata = {
+	{	/* 0 */
+		.name		= "NS87410",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.enablebits	= {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
+		.bootable	= ON_BOARD,
+        },{	/* 1 */
+		.name		= "SAMURAI",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 2 */
+		.name		= "HT6565",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 3 */
+		.name		= "UM8673F",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 4 */
+		.name		= "UM8886A",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 5 */
+		.name		= "UM8886BF",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 6 */
+		.name		= "HINT_IDE",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 7 */
+		.name		= "VIA_IDE",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 8 */
+		.name		= "OPTI621V",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 9 */
+		.name		= "VIA8237SATA",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 10 */
+		.name 		= "Piccolo0102",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 11 */
+		.name 		= "Piccolo0103",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 12 */
+		.name 		= "Piccolo0105",
+		.init_hwif	= init_hwif_generic,
+		.channels	= 2,
+		.autodma	= NOAUTODMA,
+		.bootable	= ON_BOARD,
+	}
+};
 
 /**
  *	generic_init_one	-	called when a PIIX is found
diff -Nru a/drivers/ide/pci/generic.h b/drivers/ide/pci/generic.h
--- a/drivers/ide/pci/generic.h	2004-06-01 12:04:38 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,120 +0,0 @@
-#ifndef IDE_GENERIC_H
-#define IDE_GENERIC_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-static unsigned int init_chipset_generic(struct pci_dev *, const char *);
-static void init_hwif_generic(ide_hwif_t *);
-
-static ide_pci_device_t generic_chipsets[] __devinitdata = {
-	{	/* 0 */
-		.name		= "NS87410",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.enablebits	= {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
-		.bootable	= ON_BOARD,
-        },{	/* 1 */
-		.name		= "SAMURAI",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 2 */
-		.name		= "HT6565",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 3 */
-		.name		= "UM8673F",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 4 */
-		.name		= "UM8886A",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 5 */
-		.name		= "UM8886BF",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 6 */
-		.name		= "HINT_IDE",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 7 */
-		.name		= "VIA_IDE",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 8 */
-		.name		= "OPTI621V",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= ON_BOARD,
-	},{	/* 9 */
-		.name		= "VIA8237SATA",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= OFF_BOARD,
-	},{ /* 10 */
-		.name 		= "Piccolo0102",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= ON_BOARD,
-	},{ /* 11 */
-		.name 		= "Piccolo0103",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= ON_BOARD,
-	},{ /* 12 */
-		.name 		= "Piccolo0105",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= NOAUTODMA,
-		.bootable	= ON_BOARD,
-	}
-};
-
-#if 0
-static ide_pci_device_t unknown_chipset[] __devinitdata = {
-	{	/* 0 */
-		.name		= "PCI_IDE",
-		.init_chipset	= init_chipset_generic,
-		.init_hwif	= init_hwif_generic,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= ON_BOARD,
-	}
-};
-#endif
-
-#endif /* IDE_GENERIC_H */
diff -Nru a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
--- a/drivers/ide/pci/hpt366.c	2004-12-29 14:58:32 -08:00
+++ b/drivers/ide/pci/hpt366.c	2005-02-05 17:46:28 -08:00
@@ -70,9 +70,384 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "hpt366.h"
+/* various tuning parameters */
+#define HPT_RESET_STATE_ENGINE
+#undef HPT_DELAY_INTERRUPT
+#undef HPT_SERIALIZE_IO
+
+static const char *quirk_drives[] = {
+	"QUANTUM FIREBALLlct08 08",
+	"QUANTUM FIREBALLP KA6.4",
+	"QUANTUM FIREBALLP LM20.4",
+	"QUANTUM FIREBALLP LM20.5",
+	NULL
+};
+
+static const char *bad_ata100_5[] = {
+	"IBM-DTLA-307075",
+	"IBM-DTLA-307060",
+	"IBM-DTLA-307045",
+	"IBM-DTLA-307030",
+	"IBM-DTLA-307020",
+	"IBM-DTLA-307015",
+	"IBM-DTLA-305040",
+	"IBM-DTLA-305030",
+	"IBM-DTLA-305020",
+	"IC35L010AVER07-0",
+	"IC35L020AVER07-0",
+	"IC35L030AVER07-0",
+	"IC35L040AVER07-0",
+	"IC35L060AVER07-0",
+	"WDC AC310200R",
+	NULL
+};
+
+static const char *bad_ata66_4[] = {
+	"IBM-DTLA-307075",
+	"IBM-DTLA-307060",
+	"IBM-DTLA-307045",
+	"IBM-DTLA-307030",
+	"IBM-DTLA-307020",
+	"IBM-DTLA-307015",
+	"IBM-DTLA-305040",
+	"IBM-DTLA-305030",
+	"IBM-DTLA-305020",
+	"IC35L010AVER07-0",
+	"IC35L020AVER07-0",
+	"IC35L030AVER07-0",
+	"IC35L040AVER07-0",
+	"IC35L060AVER07-0",
+	"WDC AC310200R",
+	NULL
+};
+
+static const char *bad_ata66_3[] = {
+	"WDC AC310200R",
+	NULL
+};
+
+static const char *bad_ata33[] = {
+	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
+	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
+	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
+	"Maxtor 90510D4",
+	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
+	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
+	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
+	NULL
+};
+
+struct chipset_bus_clock_list_entry {
+	u8		xfer_speed;
+	unsigned int	chipset_settings;
+};
+
+/* key for bus clock timings
+ * bit
+ * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
+ *        DMA. cycles = value + 1
+ * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
+ *        DMA. cycles = value + 1
+ * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
+ *        register access.
+ * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
+ *        register access.
+ * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
+ *        during task file register access.
+ * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
+ *        xfer.
+ * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
+ *        register access.
+ * 28     UDMA enable
+ * 29     DMA enable
+ * 30     PIO_MST enable. if set, the chip is in bus master mode during
+ *        PIO.
+ * 31     FIFO enable.
+ */
+static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
+	{	XFER_UDMA_4,	0x900fd943	},
+	{	XFER_UDMA_3,	0x900ad943	},
+	{	XFER_UDMA_2,	0x900bd943	},
+	{	XFER_UDMA_1,	0x9008d943	},
+	{	XFER_UDMA_0,	0x9008d943	},
+
+	{	XFER_MW_DMA_2,	0xa008d943	},
+	{	XFER_MW_DMA_1,	0xa010d955	},
+	{	XFER_MW_DMA_0,	0xa010d9fc	},
+
+	{	XFER_PIO_4,	0xc008d963	},
+	{	XFER_PIO_3,	0xc010d974	},
+	{	XFER_PIO_2,	0xc010d997	},
+	{	XFER_PIO_1,	0xc010d9c7	},
+	{	XFER_PIO_0,	0xc018d9d9	},
+	{	0,		0x0120d9d9	}
+};
+
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
+	{	XFER_UDMA_4,	0x90c9a731	},
+	{	XFER_UDMA_3,	0x90cfa731	},
+	{	XFER_UDMA_2,	0x90caa731	},
+	{	XFER_UDMA_1,	0x90cba731	},
+	{	XFER_UDMA_0,	0x90c8a731	},
+
+	{	XFER_MW_DMA_2,	0xa0c8a731	},
+	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
+	{	XFER_MW_DMA_0,	0xa0c8a797	},
+
+	{	XFER_PIO_4,	0xc0c8a731	},
+	{	XFER_PIO_3,	0xc0c8a742	},
+	{	XFER_PIO_2,	0xc0d0a753	},
+	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
+	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
+	{	0,		0x0120a7a7	}
+};
+
+static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
+	{	XFER_UDMA_4,	0x90c98521	},
+	{	XFER_UDMA_3,	0x90cf8521	},
+	{	XFER_UDMA_2,	0x90cf8521	},
+	{	XFER_UDMA_1,	0x90cb8521	},
+	{	XFER_UDMA_0,	0x90cb8521	},
+
+	{	XFER_MW_DMA_2,	0xa0ca8521	},
+	{	XFER_MW_DMA_1,	0xa0ca8532	},
+	{	XFER_MW_DMA_0,	0xa0ca8575	},
+
+	{	XFER_PIO_4,	0xc0ca8521	},
+	{	XFER_PIO_3,	0xc0ca8532	},
+	{	XFER_PIO_2,	0xc0ca8542	},
+	{	XFER_PIO_1,	0xc0d08572	},
+	{	XFER_PIO_0,	0xc0d08585	},
+	{	0,		0x01208585	}
+};
+
+/* from highpoint documentation. these are old values */
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
+/*	{	XFER_UDMA_5,	0x1A85F442,	0x16454e31	}, */
+	{	XFER_UDMA_5,	0x16454e31	},
+	{	XFER_UDMA_4,	0x16454e31	},
+	{	XFER_UDMA_3,	0x166d4e31	},
+	{	XFER_UDMA_2,	0x16494e31	},
+	{	XFER_UDMA_1,	0x164d4e31	},
+	{	XFER_UDMA_0,	0x16514e31	},
+
+	{	XFER_MW_DMA_2,	0x26514e21	},
+	{	XFER_MW_DMA_1,	0x26514e33	},
+	{	XFER_MW_DMA_0,	0x26514e97	},
+
+	{	XFER_PIO_4,	0x06514e21	},
+	{	XFER_PIO_3,	0x06514e22	},
+	{	XFER_PIO_2,	0x06514e33	},
+	{	XFER_PIO_1,	0x06914e43	},
+	{	XFER_PIO_0,	0x06914e57	},
+	{	0,		0x06514e57	}
+};
+
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
+	{	XFER_UDMA_5,	0x14846231	},
+	{	XFER_UDMA_4,	0x14886231	},
+	{	XFER_UDMA_3,	0x148c6231	},
+	{	XFER_UDMA_2,	0x148c6231	},
+	{	XFER_UDMA_1,	0x14906231	},
+	{	XFER_UDMA_0,	0x14986231	},
+
+	{	XFER_MW_DMA_2,	0x26514e21	},
+	{	XFER_MW_DMA_1,	0x26514e33	},
+	{	XFER_MW_DMA_0,	0x26514e97	},
+
+	{	XFER_PIO_4,	0x06514e21	},
+	{	XFER_PIO_3,	0x06514e22	},
+	{	XFER_PIO_2,	0x06514e33	},
+	{	XFER_PIO_1,	0x06914e43	},
+	{	XFER_PIO_0,	0x06914e57	},
+	{	0,		0x06514e57	}
+};
+
+/* these are the current (4 sep 2001) timings from highpoint */
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
+	{	XFER_UDMA_5,	0x12446231	},
+	{	XFER_UDMA_4,	0x12446231	},
+	{	XFER_UDMA_3,	0x126c6231	},
+	{	XFER_UDMA_2,	0x12486231	},
+	{	XFER_UDMA_1,	0x124c6233	},
+	{	XFER_UDMA_0,	0x12506297	},
+
+	{	XFER_MW_DMA_2,	0x22406c31	},
+	{	XFER_MW_DMA_1,	0x22406c33	},
+	{	XFER_MW_DMA_0,	0x22406c97	},
+
+	{	XFER_PIO_4,	0x06414e31	},
+	{	XFER_PIO_3,	0x06414e42	},
+	{	XFER_PIO_2,	0x06414e53	},
+	{	XFER_PIO_1,	0x06814e93	},
+	{	XFER_PIO_0,	0x06814ea7	},
+	{	0,		0x06814ea7	}
+};
+
+/* 2x 33MHz timings */
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
+	{	XFER_UDMA_5,	0x1488e673	},
+	{	XFER_UDMA_4,	0x1488e673	},
+	{	XFER_UDMA_3,	0x1498e673	},
+	{	XFER_UDMA_2,	0x1490e673	},
+	{	XFER_UDMA_1,	0x1498e677	},
+	{	XFER_UDMA_0,	0x14a0e73f	},
+
+	{	XFER_MW_DMA_2,	0x2480fa73	},
+	{	XFER_MW_DMA_1,	0x2480fa77	}, 
+	{	XFER_MW_DMA_0,	0x2480fb3f	},
+
+	{	XFER_PIO_4,	0x0c82be73	},
+	{	XFER_PIO_3,	0x0c82be95	},
+	{	XFER_PIO_2,	0x0c82beb7	},
+	{	XFER_PIO_1,	0x0d02bf37	},
+	{	XFER_PIO_0,	0x0d02bf5f	},
+	{	0,		0x0d02bf5f	}
+};
+
+static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
+	{	XFER_UDMA_5,	0x12848242	},
+	{	XFER_UDMA_4,	0x12ac8242	},
+	{	XFER_UDMA_3,	0x128c8242	},
+	{	XFER_UDMA_2,	0x120c8242	},
+	{	XFER_UDMA_1,	0x12148254	},
+	{	XFER_UDMA_0,	0x121882ea	},
+
+	{	XFER_MW_DMA_2,	0x22808242	},
+	{	XFER_MW_DMA_1,	0x22808254	},
+	{	XFER_MW_DMA_0,	0x228082ea	},
+
+	{	XFER_PIO_4,	0x0a81f442	},
+	{	XFER_PIO_3,	0x0a81f443	},
+	{	XFER_PIO_2,	0x0a81f454	},
+	{	XFER_PIO_1,	0x0ac1f465	},
+	{	XFER_PIO_0,	0x0ac1f48a	},
+	{	0,		0x0ac1f48a	}
+};
+
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
+	{	XFER_UDMA_6,	0x1c81dc62	},
+	{	XFER_UDMA_5,	0x1c6ddc62	},
+	{	XFER_UDMA_4,	0x1c8ddc62	},
+	{	XFER_UDMA_3,	0x1c8edc62	},	/* checkme */
+	{	XFER_UDMA_2,	0x1c91dc62	},
+	{	XFER_UDMA_1,	0x1c9adc62	},	/* checkme */
+	{	XFER_UDMA_0,	0x1c82dc62	},	/* checkme */
+
+	{	XFER_MW_DMA_2,	0x2c829262	},
+	{	XFER_MW_DMA_1,	0x2c829266	},	/* checkme */
+	{	XFER_MW_DMA_0,	0x2c82922e	},	/* checkme */
+
+	{	XFER_PIO_4,	0x0c829c62	},
+	{	XFER_PIO_3,	0x0c829c84	},
+	{	XFER_PIO_2,	0x0c829ca6	},
+	{	XFER_PIO_1,	0x0d029d26	},
+	{	XFER_PIO_0,	0x0d029d5e	},
+	{	0,		0x0d029d5e	}
+};
+
+static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
+	{	XFER_UDMA_5,	0x12848242	},
+	{	XFER_UDMA_4,	0x12ac8242	},
+	{	XFER_UDMA_3,	0x128c8242	},
+	{	XFER_UDMA_2,	0x120c8242	},
+	{	XFER_UDMA_1,	0x12148254	},
+	{	XFER_UDMA_0,	0x121882ea	},
+
+	{	XFER_MW_DMA_2,	0x22808242	},
+	{	XFER_MW_DMA_1,	0x22808254	},
+	{	XFER_MW_DMA_0,	0x228082ea	},
+
+	{	XFER_PIO_4,	0x0a81f442	},
+	{	XFER_PIO_3,	0x0a81f443	},
+	{	XFER_PIO_2,	0x0a81f454	},
+	{	XFER_PIO_1,	0x0ac1f465	},
+	{	XFER_PIO_0,	0x0ac1f48a	},
+	{	0,		0x0a81f443	}
+};
+
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
+	{	XFER_UDMA_6,	0x1c869c62	},
+	{	XFER_UDMA_5,	0x1cae9c62	},
+	{	XFER_UDMA_4,	0x1c8a9c62	},
+	{	XFER_UDMA_3,	0x1c8e9c62	},
+	{	XFER_UDMA_2,	0x1c929c62	},
+	{	XFER_UDMA_1,	0x1c9a9c62	},
+	{	XFER_UDMA_0,	0x1c829c62	},
+
+	{	XFER_MW_DMA_2,	0x2c829c62	},
+	{	XFER_MW_DMA_1,	0x2c829c66	},
+	{	XFER_MW_DMA_0,	0x2c829d2e	},
+
+	{	XFER_PIO_4,	0x0c829c62	},
+	{	XFER_PIO_3,	0x0c829c84	},
+	{	XFER_PIO_2,	0x0c829ca6	},
+	{	XFER_PIO_1,	0x0d029d26	},
+	{	XFER_PIO_0,	0x0d029d5e	},
+	{	0,		0x0d029d26	}
+};
+
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
+	{	XFER_UDMA_6,	0x12808242	},
+	{	XFER_UDMA_5,	0x12848242	},
+	{	XFER_UDMA_4,	0x12ac8242	},
+	{	XFER_UDMA_3,	0x128c8242	},
+	{	XFER_UDMA_2,	0x120c8242	},
+	{	XFER_UDMA_1,	0x12148254	},
+	{	XFER_UDMA_0,	0x121882ea	},
+
+	{	XFER_MW_DMA_2,	0x22808242	},
+	{	XFER_MW_DMA_1,	0x22808254	},
+	{	XFER_MW_DMA_0,	0x228082ea	},
+
+	{	XFER_PIO_4,	0x0a81f442	},
+	{	XFER_PIO_3,	0x0a81f443	},
+	{	XFER_PIO_2,	0x0a81f454	},
+	{	XFER_PIO_1,	0x0ac1f465	},
+	{	XFER_PIO_0,	0x0ac1f48a	},
+	{	0,		0x06814e93	}
+};
+
+/* FIXME: 50MHz timings for HPT374 */
 
 #if 0
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
+	{	XFER_UDMA_6,	0x12406231	},	/* checkme */
+	{	XFER_UDMA_5,	0x12446231	},	/* 0x14846231 */
+	{	XFER_UDMA_4,	0x16814ea7	},	/* 0x14886231 */
+	{	XFER_UDMA_3,	0x16814ea7	},	/* 0x148c6231 */
+	{	XFER_UDMA_2,	0x16814ea7	},	/* 0x148c6231 */
+	{	XFER_UDMA_1,	0x16814ea7	},	/* 0x14906231 */
+	{	XFER_UDMA_0,	0x16814ea7	},	/* 0x14986231 */
+	{	XFER_MW_DMA_2,	0x16814ea7	},	/* 0x26514e21 */
+	{	XFER_MW_DMA_1,	0x16814ea7	},	/* 0x26514e97 */
+	{	XFER_MW_DMA_0,	0x16814ea7	},	/* 0x26514e97 */
+	{	XFER_PIO_4,	0x06814ea7	},	/* 0x06514e21 */
+	{	XFER_PIO_3,	0x06814ea7	},	/* 0x06514e22 */
+	{	XFER_PIO_2,	0x06814ea7	},	/* 0x06514e33 */
+	{	XFER_PIO_1,	0x06814ea7	},	/* 0x06914e43 */
+	{	XFER_PIO_0,	0x06814ea7	},	/* 0x06914e57 */
+	{	0,		0x06814ea7	}
+};
+#endif
+
+#define HPT366_DEBUG_DRIVE_INFO		0
+#define HPT374_ALLOW_ATA133_6		0
+#define HPT371_ALLOW_ATA133_6		0
+#define HPT302_ALLOW_ATA133_6		0
+#define HPT372_ALLOW_ATA133_6		1
+#define HPT370_ALLOW_ATA100_5		1
+#define HPT366_ALLOW_ATA66_4		1
+#define HPT366_ALLOW_ATA66_3		1
+#define HPT366_MAX_DEVS			8
+
+#define F_LOW_PCI_33	0x23
+#define F_LOW_PCI_40	0x29
+#define F_LOW_PCI_50	0x2d
+#define F_LOW_PCI_66	0x42
+
+/* FIXME: compare with driver's code before removing */
+#if 0
 		if (hpt_minimum_revision(dev, 3)) {
 			u8 cbl;
 			cbl = inb(iobase + 0x7b);
@@ -1273,6 +1648,64 @@
 	return ide_setup_pci_device(dev, d);
 }
 
+static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
+	{	/* 0 */
+		.name		= "HPT366",
+		.init_setup	= init_setup_hpt366,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+		.extra		= 240
+	},{	/* 1 */
+		.name		= "HPT372A",
+		.init_setup	= init_setup_hpt37x,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 2 */
+		.name		= "HPT302",
+		.init_setup	= init_setup_hpt37x,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 3 */
+		.name		= "HPT371",
+		.init_setup	= init_setup_hpt37x,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 4 */
+		.name		= "HPT374",
+		.init_setup	= init_setup_hpt374,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,	/* 4 */
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	},{	/* 5 */
+		.name		= "HPT372N",
+		.init_setup	= init_setup_hpt37x,
+		.init_chipset	= init_chipset_hpt366,
+		.init_hwif	= init_hwif_hpt366,
+		.init_dma	= init_dma_hpt366,
+		.channels	= 2,	/* 4 */
+		.autodma	= AUTODMA,
+		.bootable	= OFF_BOARD,
+	}
+};
 
 /**
  *	hpt366_init_one	-	called when an HPT366 is found
diff -Nru a/drivers/ide/pci/hpt366.h b/drivers/ide/pci/hpt366.h
--- a/drivers/ide/pci/hpt366.h	2004-12-29 14:58:32 -08:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,483 +0,0 @@
-#ifndef HPT366_H
-#define HPT366_H
-
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-/* various tuning parameters */
-#define HPT_RESET_STATE_ENGINE
-#undef HPT_DELAY_INTERRUPT
-#undef HPT_SERIALIZE_IO
-
-static const char *quirk_drives[] = {
-	"QUANTUM FIREBALLlct08 08",
-	"QUANTUM FIREBALLP KA6.4",
-	"QUANTUM FIREBALLP LM20.4",
-	"QUANTUM FIREBALLP LM20.5",
-        NULL
-};
-
-static const char *bad_ata100_5[] = {
-	"IBM-DTLA-307075",
-	"IBM-DTLA-307060",
-	"IBM-DTLA-307045",
-	"IBM-DTLA-307030",
-	"IBM-DTLA-307020",
-	"IBM-DTLA-307015",
-	"IBM-DTLA-305040",
-	"IBM-DTLA-305030",
-	"IBM-DTLA-305020",
-	"IC35L010AVER07-0",
-	"IC35L020AVER07-0",
-	"IC35L030AVER07-0",
-	"IC35L040AVER07-0",
-	"IC35L060AVER07-0",
-	"WDC AC310200R",
-	NULL
-};
-
-static const char *bad_ata66_4[] = {
-	"IBM-DTLA-307075",
-	"IBM-DTLA-307060",
-	"IBM-DTLA-307045",
-	"IBM-DTLA-307030",
-	"IBM-DTLA-307020",
-	"IBM-DTLA-307015",
-	"IBM-DTLA-305040",
-	"IBM-DTLA-305030",
-	"IBM-DTLA-305020",
-	"IC35L010AVER07-0",
-	"IC35L020AVER07-0",
-	"IC35L030AVER07-0",
-	"IC35L040AVER07-0",
-	"IC35L060AVER07-0",
-	"WDC AC310200R",
-	NULL
-};
-
-static const char *bad_ata66_3[] = {
-	"WDC AC310200R",
-	NULL
-};
-
-static const char *bad_ata33[] = {
-	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
-	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
-	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
-	"Maxtor 90510D4",
-	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
-	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
-	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
-	NULL
-};
-
-struct chipset_bus_clock_list_entry {
-	byte		xfer_speed;
-	unsigned int	chipset_settings;
-};
-
-/* key for bus clock timings
- * bit
- * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
- *        DMA. cycles = value + 1
- * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
- *        DMA. cycles = value + 1
- * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
- *        register access.
- * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
- *        register access.
- * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
- *        during task file register access.
- * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
- *        xfer.
- * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
- *        register access.
- * 28     UDMA enable
- * 29     DMA enable
- * 30     PIO_MST enable. if set, the chip is in bus master mode during
- *        PIO.
- * 31     FIFO enable.
- */
-static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
-	{	XFER_UDMA_4,	0x900fd943	},
-	{	XFER_UDMA_3,	0x900ad943	},
-	{	XFER_UDMA_2,	0x900bd943	},
-	{	XFER_UDMA_1,	0x9008d943	},
-	{	XFER_UDMA_0,	0x9008d943	},
-
-	{	XFER_MW_DMA_2,	0xa008d943	},
-	{	XFER_MW_DMA_1,	0xa010d955	},
-	{	XFER_MW_DMA_0,	0xa010d9fc	},
-
-	{	XFER_PIO_4,	0xc008d963	},
-	{	XFER_PIO_3,	0xc010d974	},
-	{	XFER_PIO_2,	0xc010d997	},
-	{	XFER_PIO_1,	0xc010d9c7	},
-	{	XFER_PIO_0,	0xc018d9d9	},
-	{	0,		0x0120d9d9	}
-};
-
-static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
-	{	XFER_UDMA_4,	0x90c9a731	},
-	{	XFER_UDMA_3,	0x90cfa731	},
-	{	XFER_UDMA_2,	0x90caa731	},
-	{	XFER_UDMA_1,	0x90cba731	},
-	{	XFER_UDMA_0,	0x90c8a731	},
-
-	{	XFER_MW_DMA_2,	0xa0c8a731	},
-	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
-	{	XFER_MW_DMA_0,	0xa0c8a797	},
-
-	{	XFER_PIO_4,	0xc0c8a731	},
-	{	XFER_PIO_3,	0xc0c8a742	},
-	{	XFER_PIO_2,	0xc0d0a753	},
-	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
-	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
-	{	0,		0x0120a7a7	}
-};
-
-static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
-
-	{	XFER_UDMA_4,	0x90c98521	},
-	{	XFER_UDMA_3,	0x90cf8521	},
-	{	XFER_UDMA_2,	0x90cf8521	},
-	{	XFER_UDMA_1,	0x90cb8521	},
-	{	XFER_UDMA_0,	0x90cb8521	},
-
-	{	XFER_MW_DMA_2,	0xa0ca8521	},
-	{	XFER_MW_DMA_1,	0xa0ca8532	},
-	{	XFER_MW_DMA_0,	0xa0ca8575	},
-
-	{	XFER_PIO_4,	0xc0ca8521	},
-	{	XFER_PIO_3,	0xc0ca8532	},
-	{	XFER_PIO_2,	0xc0ca8542	},
-	{	XFER_PIO_1,	0xc0d08572	},
-	{	XFER_PIO_0,	0xc0d08585	},
-	{	0,		0x01208585	}
-};
-
-/* from highpoint documentation. these are old values */
-static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
-/*	{	XFER_UDMA_5,	0x1A85F442,	0x16454e31	}, */
-	{	XFER_UDMA_5,	0x16454e31	},
-	{	XFER_UDMA_4,	0x16454e31	},
-	{	XFER_UDMA_3,	0x166d4e31	},
-	{	XFER_UDMA_2,	0x16494e31	},
-	{	XFER_UDMA_1,	0x164d4e31	},
-	{	XFER_UDMA_0,	0x16514e31	},
-
-	{	XFER_MW_DMA_2,	0x26514e21	},
-	{	XFER_MW_DMA_1,	0x26514e33	},
-	{	XFER_MW_DMA_0,	0x26514e97	},
-
-	{	XFER_PIO_4,	0x06514e21	},
-	{	XFER_PIO_3,	0x06514e22	},
-	{	XFER_PIO_2,	0x06514e33	},
-	{	XFER_PIO_1,	0x06914e43	},
-	{	XFER_PIO_0,	0x06914e57	},
-	{	0,		0x06514e57	}
-};
-
-static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
-	{       XFER_UDMA_5,    0x14846231      },
-	{       XFER_UDMA_4,    0x14886231      },
-	{       XFER_UDMA_3,    0x148c6231      },
-	{       XFER_UDMA_2,    0x148c6231      },
-	{       XFER_UDMA_1,    0x14906231      },
-	{       XFER_UDMA_0,    0x14986231      },
-	
-	{       XFER_MW_DMA_2,  0x26514e21      },
-	{       XFER_MW_DMA_1,  0x26514e33      },
-	{       XFER_MW_DMA_0,  0x26514e97      },
-	
-	{       XFER_PIO_4,     0x06514e21      },
-	{       XFER_PIO_3,     0x06514e22      },
-	{       XFER_PIO_2,     0x06514e33      },
-	{       XFER_PIO_1,     0x06914e43      },
-	{       XFER_PIO_0,     0x06914e57      },
-	{       0,              0x06514e57      }
-};
-
-/* these are the current (4 sep 2001) timings from highpoint */
-static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
-        {       XFER_UDMA_5,    0x12446231      },
-        {       XFER_UDMA_4,    0x12446231      },
-        {       XFER_UDMA_3,    0x126c6231      },
-        {       XFER_UDMA_2,    0x12486231      },
-        {       XFER_UDMA_1,    0x124c6233      },
-        {       XFER_UDMA_0,    0x12506297      },
-
-        {       XFER_MW_DMA_2,  0x22406c31      },
-        {       XFER_MW_DMA_1,  0x22406c33      },
-        {       XFER_MW_DMA_0,  0x22406c97      },
-
-        {       XFER_PIO_4,     0x06414e31      },
-        {       XFER_PIO_3,     0x06414e42      },
-        {       XFER_PIO_2,     0x06414e53      },
-        {       XFER_PIO_1,     0x06814e93      },
-        {       XFER_PIO_0,     0x06814ea7      },
-        {       0,              0x06814ea7      }
-};
-
-/* 2x 33MHz timings */
-static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
-	{       XFER_UDMA_5,    0x1488e673       },
-	{       XFER_UDMA_4,    0x1488e673       },
-	{       XFER_UDMA_3,    0x1498e673       },
-	{       XFER_UDMA_2,    0x1490e673       },
-	{       XFER_UDMA_1,    0x1498e677       },
-	{       XFER_UDMA_0,    0x14a0e73f       },
-
-	{       XFER_MW_DMA_2,  0x2480fa73       },
-	{       XFER_MW_DMA_1,  0x2480fa77       }, 
-	{       XFER_MW_DMA_0,  0x2480fb3f       },
-
-	{       XFER_PIO_4,     0x0c82be73       },
-	{       XFER_PIO_3,     0x0c82be95       },
-	{       XFER_PIO_2,     0x0c82beb7       },
-	{       XFER_PIO_1,     0x0d02bf37       },
-	{       XFER_PIO_0,     0x0d02bf5f       },
-	{       0,              0x0d02bf5f       }
-};
-
-static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
-	{       XFER_UDMA_5,    0x12848242      },
-	{       XFER_UDMA_4,    0x12ac8242      },
-	{       XFER_UDMA_3,    0x128c8242      },
-	{       XFER_UDMA_2,    0x120c8242      },
-	{       XFER_UDMA_1,    0x12148254      },
-	{       XFER_UDMA_0,    0x121882ea      },
-
-	{       XFER_MW_DMA_2,  0x22808242      },
-	{       XFER_MW_DMA_1,  0x22808254      },
-	{       XFER_MW_DMA_0,  0x228082ea      },
-
-	{       XFER_PIO_4,     0x0a81f442      },
-	{       XFER_PIO_3,     0x0a81f443      },
-	{       XFER_PIO_2,     0x0a81f454      },
-	{       XFER_PIO_1,     0x0ac1f465      },
-	{       XFER_PIO_0,     0x0ac1f48a      },
-	{       0,              0x0ac1f48a      }
-};
-
-static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
-	{	XFER_UDMA_6,	0x1c81dc62	},
-	{	XFER_UDMA_5,	0x1c6ddc62	},
-	{	XFER_UDMA_4,	0x1c8ddc62	},
-	{	XFER_UDMA_3,	0x1c8edc62	},	/* checkme */
-	{	XFER_UDMA_2,	0x1c91dc62	},
-	{	XFER_UDMA_1,	0x1c9adc62	},	/* checkme */
-	{	XFER_UDMA_0,	0x1c82dc62	},	/* checkme */
-
-	{	XFER_MW_DMA_2,	0x2c829262	},
-	{	XFER_MW_DMA_1,	0x2c829266	},	/* checkme */
-	{	XFER_MW_DMA_0,	0x2c82922e	},	/* checkme */
-
-	{	XFER_PIO_4,	0x0c829c62	},
-	{	XFER_PIO_3,	0x0c829c84	},
-	{	XFER_PIO_2,	0x0c829ca6	},
-	{	XFER_PIO_1,	0x0d029d26	},
-	{	XFER_PIO_0,	0x0d029d5e	},
-	{	0,		0x0d029d5e	}
-};
-
-static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
-	{	XFER_UDMA_5,	0x12848242	},
-	{	XFER_UDMA_4,	0x12ac8242	},
-	{	XFER_UDMA_3,	0x128c8242	},
-	{	XFER_UDMA_2,	0x120c8242	},
-	{	XFER_UDMA_1,	0x12148254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-	{	XFER_MW_DMA_1,	0x22808254	},
-	{	XFER_MW_DMA_0,	0x228082ea	},
-
-	{	XFER_PIO_4,	0x0a81f442	},
-	{	XFER_PIO_3,	0x0a81f443	},
-	{	XFER_PIO_2,	0x0a81f454	},
-	{	XFER_PIO_1,	0x0ac1f465	},
-	{	XFER_PIO_0,	0x0ac1f48a	},
-	{	0,		0x0a81f443	}
-};
-
-static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
-	{	XFER_UDMA_6,	0x1c869c62	},
-	{	XFER_UDMA_5,	0x1cae9c62	},
-	{	XFER_UDMA_4,	0x1c8a9c62	},
-	{	XFER_UDMA_3,	0x1c8e9c62	},
-	{	XFER_UDMA_2,	0x1c929c62	},
-	{	XFER_UDMA_1,	0x1c9a9c62	},
-	{	XFER_UDMA_0,	0x1c829c62	},
-
-	{	XFER_MW_DMA_2,	0x2c829c62	},
-	{	XFER_MW_DMA_1,	0x2c829c66	},
-	{	XFER_MW_DMA_0,	0x2c829d2e	},
-
-	{	XFER_PIO_4,	0x0c829c62	},
-	{	XFER_PIO_3,	0x0c829c84	},
-	{	XFER_PIO_2,	0x0c829ca6	},
-	{	XFER_PIO_1,	0x0d029d26	},
-	{	XFER_PIO_0,	0x0d029d5e	},
-	{	0,		0x0d029d26	}
-};
-
-static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
-	{	XFER_UDMA_6,	0x12808242	},
-	{	XFER_UDMA_5,	0x12848242	},
-	{	XFER_UDMA_4,	0x12ac8242	},
-	{	XFER_UDMA_3,	0x128c8242	},
-	{	XFER_UDMA_2,	0x120c8242	},
-	{	XFER_UDMA_1,	0x12148254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-	{	XFER_MW_DMA_1,	0x22808254	},
-	{	XFER_MW_DMA_0,	0x228082ea	},
-
-	{	XFER_PIO_4,	0x0a81f442	},
-	{	XFER_PIO_3,	0x0a81f443	},
-	{	XFER_PIO_2,	0x0a81f454	},
-	{	XFER_PIO_1,	0x0ac1f465	},
-	{	XFER_PIO_0,	0x0ac1f48a	},
-	{	0,		0x06814e93	}
-};
-
-#if 0
-static struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
-	{	XFER_UDMA_6,	},
-	{	XFER_UDMA_5,	},
-	{	XFER_UDMA_4,	},
-	{	XFER_UDMA_3,	},
-	{	XFER_UDMA_2,	},
-	{	XFER_UDMA_1,	},
-	{	XFER_UDMA_0,	},
-	{	XFER_MW_DMA_2,	},
-	{	XFER_MW_DMA_1,	},
-	{	XFER_MW_DMA_0,	},
-	{	XFER_PIO_4,	},
-	{	XFER_PIO_3,	},
-	{	XFER_PIO_2,	},
-	{	XFER_PIO_1,	},
-	{	XFER_PIO_0,	},
-	{	0,	}
-};
-#endif
-#if 0
-static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
-	{	XFER_UDMA_6,	0x12406231	},	/* checkme */
-	{	XFER_UDMA_5,	0x12446231	},
-				0x14846231
-	{	XFER_UDMA_4,		0x16814ea7	},
-				0x14886231
-	{	XFER_UDMA_3,		0x16814ea7	},
-				0x148c6231
-	{	XFER_UDMA_2,		0x16814ea7	},
-				0x148c6231
-	{	XFER_UDMA_1,		0x16814ea7	},
-				0x14906231
-	{	XFER_UDMA_0,		0x16814ea7	},
-				0x14986231
-	{	XFER_MW_DMA_2,		0x16814ea7	},
-				0x26514e21
-	{	XFER_MW_DMA_1,		0x16814ea7	},
-				0x26514e97
-	{	XFER_MW_DMA_0,		0x16814ea7	},
-				0x26514e97
-	{	XFER_PIO_4,		0x06814ea7	},
-				0x06514e21
-	{	XFER_PIO_3,		0x06814ea7	},
-				0x06514e22
-	{	XFER_PIO_2,		0x06814ea7	},
-				0x06514e33
-	{	XFER_PIO_1,		0x06814ea7	},
-				0x06914e43
-	{	XFER_PIO_0,		0x06814ea7	},
-				0x06914e57
-	{	0,		0x06814ea7	}
-};
-#endif
-
-#define HPT366_DEBUG_DRIVE_INFO		0
-#define HPT374_ALLOW_ATA133_6		0
-#define HPT371_ALLOW_ATA133_6		0
-#define HPT302_ALLOW_ATA133_6		0
-#define HPT372_ALLOW_ATA133_6		1
-#define HPT370_ALLOW_ATA100_5		1
-#define HPT366_ALLOW_ATA66_4		1
-#define HPT366_ALLOW_ATA66_3		1
-#define HPT366_MAX_DEVS			8
-
-#define F_LOW_PCI_33      0x23
-#define F_LOW_PCI_40      0x29
-#define F_LOW_PCI_50      0x2d
-#define F_LOW_PCI_66      0x42
-
-static int init_setup_hpt366(struct pci_dev *, ide_pci_device_t *);
-static int init_setup_hpt37x(struct pci_dev *, ide_pci_device_t *);
-static int init_setup_hpt374(struct pci_dev *, ide_pci_device_t *);
-static unsigned int init_chipset_hpt366(struct pci_dev *, const char *);
-static void init_hwif_hpt366(ide_hwif_t *);
-static void init_dma_hpt366(ide_hwif_t *, unsigned long);
-
-static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
-	{	/* 0 */
-		.name		= "HPT366",
-		.init_setup	= init_setup_hpt366,
-		.init_chipset	= init_chipset_hpt366,
-		.init_hwif	= init_hwif_hpt366,
-		.init_dma	= init_dma_hpt366,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.extra		= 240
- Nea7	uble	= OFF_BOARD,
-		.exRD,
-	2Nea7	ubhree_bas7FF_BOFER_UDMA_0,    0x1498623OARD,
-DTLAM *);	= 2,
-		.a-7AM *);	=_0,xRD,
_AM *);1   0x29)NmQ26:2 2,	0xA_0,		0x2eckme */MA_1,ide_pci_device7wif_hp		.e		= "HPT374",
+		.init_setup	= init_setup_hpt374,
+		.init_chipset	= init_(_PIO_3c	,e HPT374_ALLOW_A0(*);	=_0,xRD,
_AM *);1   0x29)NmQ26:2 2,	0xA_0,		0x2eckme */MA_1,ide_pci_device7wif_hp		.e		(w,
-2c829262	},
-	{	XFER_MW_DMA_1,	0x2c829266	},	/* checkme */
-	{	XFER_MW_DMA_0,	0x2c82922e	},	/* checkme */
-
-	{	0x2c82922e	},	/*2,	0x0l5-n	.init
-	{	XFER_MW8)73+N    el  check(n2922e	},S NOAUTI +0,0 @@
-#ifndef HPT3e	}
-};
-a9d.init_e_pci_device_t *);
-static ineFextra	Fextra	Fextra	Fextra	Fextra	Fextra	Fextra	Fextra	Fextra	Fextra	Fee_t hpt366_chipsets[] _829c62     0_22e	t[] = {
-	{	XFER_UDMA_6,	0x1extra	Fextrx0aCXFE1e	= 2AUTODMA,
-		.enaf0aCXFE1e	-		.efr ineFer 906804	},igned int inaer 9068extra36\*ODMA,
ll1488eSeY"s1488eSeY"s:bntation. these p:3td88e,
-				.bootu20 nNlM82ea   ock_lBXFE1e	-		.efr ineFer 906804	},igned int inaer 9068extra36\*ODMA,
ll1488eSeY"s1488eSeY"s:bntation. these p:3td88e,
-				.bootu20 nNlM82ea  27_+_hpt36		.bo,rx0aCC,4,		.bo,rx0aCC,4,		.bo,rx0aCC,4,		.bo,r5_2pMaxtor 9151u 		.bo,c6231
-	{	XFER_UDMA_1,		0x168_or 9151u 		.bo,c6231
-	{	XFER_UDMA_1,		0x168_orma	= {	XFE151u 		.bo,c6231
-	{	XFEe 20XFER_M1	XFER_UDMA_3,	0x1c8e9c62	},vODMA,
+		.bootable	= ON_BOARD,
+	},{	/* 11 */
+		.name 		 ,1	0x1c9adc62	},	/* chi 		 ,		/0uTI/* chi 		 ,		/0uTI/* )ON_B UDMA_2,    0x1490e673       },   0x	{	XFER_cM *);1   0x29)Nms7	},	/*xa0ch8e,
a0ch8e,
a0ch8e	},
-ch8
-	{	XFEe 20x29)Nmsx42
_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-		.extra		= 240
- Nea7	24e21	P0_generic,
+		.channelsODMA,udma_c	-		.2  { s9Ee { s50   lTI/* chi 		 ,		/0uTI/* )ON_B UDMA_2,    0x1490e673       },   0x	{	XFER_cM *);1   0x29)Nms7	},	/*xa0ch8e,
a0ch8e,
a0ch8e	},
-ch8
-	{	XFEe 20x29)Nmsx42
_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-		.extra		= 240
- Nea7	24e21	P0_generic,
+		.channelsODMA,udma_c	-		.2  { 	XFER_UDs29)Nmsx42;a.channels	=up_hpt37x(struct pci_dev -p_ct pci_0define F_LOsiH	  V2wifx1498ch8
-	{	WDC AC310200R",
-	NU_1,	0ahh)Nms7	e0aCC,h)SF_L	0ahhPIO_1,		0x06814ea7	},
-				0x06914e43
-	{	XFER_PIO_0,		0x06814esctive tim.7
-	{	0,		0x+	74e21_FEe 2or 9s	{	XFER_UDMA_pset	chipsetso,rx0aCF_LOs eadc62	},	/* (Vtd02bf5f a	0x06814esctive tim.7
-	{	0,		0x+	74e21_FEe 2or 9s	{	XFER_UDMA_pset	chipsetso,r4ea},
-	{	XnDD,
_A,r4ea},
-	sInDD0d0a7aa	},	/* 0R_PI},
-	si_device_t hpt366_chip0x1c8e9c62	eea},
-	sInDD0d0a7aa	},	/* 0R_PI};set	= ie22	s_bus_clock_list_entry sixty_six_u ie22	s_   XFER_PIO_UDMA_3,	1c8edc62	},	/*aER_},
-	 0x1nK},
-	sInDDc62	},	/*},
,	1c8edc-de_pci_device7wif_hp		.e		= ",
-
-nm{	0,		0x0120d9d9	}+ci_de0,	0xa0c8a7 0120d y4,		.bo,r5_2pMevice_t *);
-static 6	}2&:},
-	x06814ea7	},
-_uct chip,	0x121882ea	},
-
-	{	XFE		.extra	gvic	}
-};
-
-sXFER_-static 6	}2&:},
-	x06e		= EFER_UDMA_4,	0x12ac8242	},
-	{	XFER_UDMA_3,	0x128c1t;
-
-sac8242	},
-	{	128c1t;
-:iste
+		.mue
+	;
-Aaic	}
-0x121490e-c 6	}2&:},
-	x06e		= EFER_U8		0x168_or 9151u 		.bo,c623268_e*4nd MW
 =de/pci/hrl_U8	,evice_t *);
-stati7Raist_entry forty___UDMA+x2ea,
_A,r4ea},
-	sInDD0d0a7aa	},	/* 0R_PI},
-	si_dC	/* 0R_Pe,
-	sInDD0d0a7aa	},	/* 0R_PI};seW
 =dei_device7wif_h8_UDMA_d int -882ea	},
-
-	{	XFE		.extrsac8ba},
-	{_149ty_six_u ie22	s_   XFERn49ty_six_u ie 0120d  F0x06814esc2i_dC	/0e-c 6	}2&:},
-	x06e		= EFER_U8		0x168_or 9151u 		.bo,c623268_e*4nd MWit_e_pci_device_t *);
-static ineFextra	Fis2188r6edc62	}c4,	0xtu20 nN+evice_t *);
-0I	9c62	},
-	{	XFER.bootable	= OFF_BOARD,
+	},{	/* 2 */
+		.naA_1,		ic ineF%A	/* 2 68_e*4nd MWit_h"TA6_edc6214esc2i_ck_list_"},
-	E0(PI},
-	si_dC- Nea7e22	s_   XFERn49ty_six_R_U8		0x168_or 9151u0(PI},
-	sia	Ftd8[] = 7i0681Eix_R_81EW
 =d7i06N81EW
 s2188rr 90680D4"30p-	{sy_sct chtwe3MWit_h"TA6__51so,r4ea3		ice_ nN+eI7,
+	_0ix_R_81+eI7,
td8[] = 7i068exthanne:sS75t chtwe3MWit_h"TA6__51so,r4ea3		ice_ nN+eI7,
+	_0ix_R_81+eI7,
td8[] = 7i068exthanne:sS75t chtwe3MWit_h"TA    na},
-tra	Fextra	Fextra	Fextra	Fee_t hpt366_chipsets[] _829c62     0_22e	t[] = {
-	{	XFER_UDMA_6,	0x1extra	Fextrx0aCXFE1e	= 2AUTODMA,
-		.ena	Fextraefine A,
-		.ena	Fextraefine A,
-		
-		
t8e,)xthanne:sS75  },
-	{    ne A,U8		0hi 		 ,		/0uTI/* ,M0x124cS40xa0hptAwoSaf_h )	/* ,
+		.channelsODMeI7,
+	_0ixe3MWit,
+	_0ix_R_814,	0x1c8a9c62	},
+	{	XFER_UDMA_3,	0x1c8e9c62	},
+	{	XFER_UDMA_2,	0x1c929c62	},
+	{	XFER_UDMA_1,	0x1c9a9c62	},
+	{	XFER_UDMA_0,	0x1c829c62	},
+
+	{	XFER_MW_DMA_2,	0x2c829c62	},
+	{	XFER_MW_DMA_1,	0x2c829c66	},
+	{	XFER_MW_DMA_0,	0x2c829d2e	},
+
+	{	XFER_PIO_4IO_4IO6O;01,   b242	},
SC },
- AwoSaf_h ID,
-cha	F8u},
SC 2- AwoSaf_h ID,
-cht_h"TA6S};seMA_3,	0x1c8eE
SC e_9c62	},
-	{	UDM1c8+	|0x06>+sDMA																								-        x06>+sDMA																								-        x06>+sDMA											      <E										dNGS,
+	_0ix_R_8 SS)WDC AC310200R",
-	NULL
-};dc62	},	/* various tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};
lUDs298R_UDMA_init_setup_hpt366,
-		.i0:)		.mue
+	;
-Aaic1twe3MG_DMA_1:)	9)Nm4s tu{	848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m" 
+	{	sLA-307060",
-	"IBM-DTLA-30704504,	0x12ac8242	},
-	{	XFER_UD5{	XFER4mue
+	sp&	3=307045L  intllTODMA,
+bULL
-};dc62	},	/* vahpt37_%L
-};d4	},
       },
-	{       XFu8;d4	},
       },
-	{       -IO_4-	{	XFER_UDMA_2,	0x1A+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m04,	0Sr1c829  x0m04,	0S2	},
+	{	XFER_U	848-  +	{	XFER_x0m,M_(*);			0x}
-};
lUDs2985le	= ht_h"TA6S};seMA_3,	0x1c8;2680D4"uA6S};=_0_9UDMA_u3td88e_0,	0x1c829  x0m04,	0Sr1c,	0Sr1_ L buF= Oh},
-	{  6EHs2985      {       XFER_PIO_3,     0x06414e42      },
-        {       XFER_PIO_2,  1+	{	XFER_PIOhS75t chtwe3MWit_h"TA6___ALL7MA											      <E										dNGlUDs2985le	= ht_h"TA6S};seMA_3,	0x1c8;2680D4"uA6S};=_062	},
+
+8;2680D4"uA6S};=_062	},
+
+8;2680D-)0x1c829  x0m04,	0try {
-i 		 ,		ID,
0eO+		.name		= "HPT3  1+	{	XFER		0x0dl1
-	{	XFER_P_u ie 0120829 }
-};DMA_1ctatic strucs0tr4_BOARD,
-0	-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m04,	0Sr1c829 "IBivers/il1
-	CLs+
+8;2680D-/mLV/(2f=,
-6,3 */
b0     }
-};
-
-/},
+	{	XFE+8;268	5			dN/
b0     }
-};
-
-/},
+	{	XFE+8;T3	{	T3	dN/
b0     1+R_81E.init_hwif	},
1E.inDMA_1,	0A81E.init_hwif	},
1E.inDMA_1,	0A81E.init_hwipous.vR_UDMd 0120827ic struct chianI8_5	.bootu20 nNlM82ea  27_+_hpt36		.bo,rx0aCC,4,		.bo,rx0aCC,4,		.bo,rx0aCC,4,		.bo,r5_2pMaxtor 9151u 		.bo,c6231
-	{	XFER_UDMA_1,		0x168_or 91,<eMH,		.bo,   },
   }
--	{	XFE		.ex_UDMA_1,	r 90680D4", "MarN/
b0     1+R_eu}
-}= h2 _0,	0x1c829 -
mcd  _0,	0x1c829 -
mcd  _ime of DMW_DMA_0,	0xa0    },
-t0,	cV,	/*x+I71-msx42
LCLs+
+8;2680D-/mg2680D-/mg26spt366(ide_hwhii	0,		0x0d029d29 "IBivers/il1
-	CLs+
+8;2680D-/mLV/(2f=,
-6,3 */
b0     }
-};
_7r 90S5,	0x1cae9c 0x1A_1ctw5,	0x1cae XFER"ti},
_0U3", "Maxtor 90845U3", "Maxto0x1c8,4,		.244627r 90Sa3	}8>	0x1cae X									dNGlUDs297)o	{	XFE	XFER_PIO_4,	0x06414e31{	/* Ds297)e2	MST e672i_ck_list_"},
-	E0(PI},
-	si_dC- Ne)Nms7	},	/*xa0ch8e,
a0ch8R_U8		0x168-504,	0x12ac8242	},
-	{	XFER_UD5{	XF-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-1	/*xa0ch8e,
a0ch8R_U8		09168-504,	0x12ac8242	},
-	{	XFER_UD5{	XF-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-2	/*xa0ch8e,
a0ch8R_U8		70168-504,	0x12ac8242	},
-	{	XFER_UD		
-		
-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	{	XFER_UDMA_6,	0x1280824829c62	},
+-504,	0x12ac8242	},
-	{	XFER_UD5{	XF-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-4UDMA_6,	0x1280824829c62	5,
+-504,	0x12ac8242	},
-	{	XFER_UD5{	XF-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x22808242	},
-5UDMA_6,	0x1280824829c62	6168-504,	0x12ac8242	},
-	{	XFER_UD		
-6	
-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	{	XFER6UDMA_6,	0x1280824829c62	7,
+-504,	0x12ac8242	},
-	{	XFER_UD5{	XF-R4mue
+	sp&	3=307045L  intllTODMA,
+bUL-
-};dc62	},	/* vahpt37_%L
-};d4	},
 48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA_2,	0x2280824F_LOs eadc62	},	/*42      },5f a	0x06814esctive tim.7
-	{	0,		0x+	74eoldFEe 2or 9s	{	XFER_UDMA_pset	choldFE= ht_h"TA6S};seMA_3,	0x1c8;2680DoldFE0d0a7aa	},	/* 0R_PI},
-	si_device_t hpt366_chip0x1c8e9c62	eoldFE0d0anDD0d0a7aa	36:5_hp		.e		(w,
46,9 +46,60FER_UDMA_6,	0x12406231	},	/* checkme */
-rqc829266	},	/* chec8e9c62	eoldFh"y_six_u ie0x1nK},
-	sInDDc62	8a	},
+	{	0,42      }heckme */
-	{	XFE09266	_},
-	 0x1nK},
-	sInDDc62	},++#define F_LOW_PCI_device7wif_hp		.e		= ",
-
-nm{	0,		0x0120d9d9	}+ci_de0,	0xa0c8a7 0120d y4,		.bo,r5_2pMevice_t *);
-static 6	}2&:},
-	x06814ea7	},
-_uct chip,	0x121882ea	},
-
-	{	XFE		.extra	gvic	}
-};
-
-sXFER_-static 6	}2&:},
-	x06e		= EFER_UDMA_4,	0x12ac8242	},
-	{	XFER_UDMA_3,	0x128c1t;
	/*A RAUTODMA,DMA_0_},
-		SYNC_ERRDY_EN	0xC09ty_six_u i	SYNC_IN8ddc80_UDMAontrol/* 2	5	0x0es.
- * 4 t_chipsvs. 	},
-*2,	0xs,DMA_0_},
-		ERRDY_EN	0x40_UDMAontrol/* 2	5	0x0es.
- * 4 t_chipsvs. 	},
-*2,	0xs,DMA_0_},
-		IORDY_EN	0x20_UDMPIO: IOREADY,DMA_0_},
-		PREFETCH_EN	0x10_UDMPIO: PREFETCH}
+};
+0_},
-		PA38ddc68_UDMPIO"A"_hpt366,DMA_0_},
-		PA28ddc64_UDMPIO"A"_hpt366,DMA_0_},
-		PA18ddc62_UDMPIO"A"_hpt366,DMA_0_},
-		PA0C AC31_UDMPIO"A"_hpt366,DMA_;
	/*B RAUTODMA,DMA_A_0_},
-		MB28ddc80_UDM	},"B"_hpt366,DMA_0_},
-		MB18ddc40_UDM	},"B"_hpt366,DMA_0_},
-		MB0C AC20_UDM	},"B"_hpt366,DMA_A_0_},
-		PB4		0x10_UDMPIO8242f_ 1:0,DMA_A_0_},
-		PB38ddc68_UDMPIO"B"_hpt366,DM_UDMPIO flow Control/et	= DMA_0_},
-		PB28ddc64_UDMPIO"B"_hpt366,DM_UDMPIO 4 DMA_0_},
-		PB18ddc62_UDMPIO"B"_hpt366,DM_UDMPIO 3 half DMA_0_},
-		PB0C AC31_UDMPIO"B"_hpt366,DM_UDMPIO 3 othMA,half DMA_;
	/*C RAUTODMA,DMA_0_},
-		IORDYp_NO_SPEEDddc4Fy_six_u i	SPEED_DIS AC3FA_A_0_},
-			},RQp8ddc80A_0_},
-		IORDYp8ddc40A_0_},
-			},R_EN	 AC20A_0_},
-			},W_EN	 AC109ty_six_u i	MC38ddc68_UDM	},"C"_hpt366,DMA_0_},
-		MC28ddc64_UDM	},"C"_hpt366,DMA_0_},
-		MC18ddc62_UDM	},"C"_hpt366,DMA_0_},
-		MC0C AC31_UDM	},"C"_hpt366,DMA+	{	XFER_0x16814ea7	},
-	bibma 	= 97)eresourT e+#drteF%A	/4	0x2c8269x265120,	0x0681	((sc1c &{	XF2)ER_U	XF2)E? "8" :681	((sc1c &{	XF1)ER_U	XF1)E? "6" :681	((sc1c &{	XF0)ER_U	XF0)E? "4" : "??"ER_MWSPLIT_BYTE(sc1e, hi,	},		0x1hi	= sc1e >> 4	0x1lo	= sc1e &{	Xf		0xp += spr"Maf(p, "S#deus Poll366,Period                : %d\n", hi)		0xp += spr"Maf(p, "InDMArupt C_2,  S#deus Poll366,Delay : %d\n", },		02	s_   X2c8272	},
+7-6	7	0x1488623{	/* 2 */
+		.naA_1,		ic ineF%A	/* 2 68_e*4nd MWit_h"TA6_edc6214esc2i_9c62	eist_"},
-	E0(PI},
-	si_dC- Nea7e22	s_   XFERn49ty_six_R_U8		4 tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};i_d4XFER4mue
+	sp&	3=307045L  intllTODMA,9c62	ULL
-};dc62	},	/* vahpt37_%L
-};d42	ULL
-};dc62	{	XFER_UDMA_2,
-};d42	ULL
-}848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m	XFER_UDMA_16 chtwe3MWit_h"TA6__51so,r4ea3		ice_ 2tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};i_d4XFER4mue
+	sp&	3=307045L  intllTODMA,9c62	ULL
-};dc62	},	/* vahpt37_%L
-};d42	ULL
-};dc62	{	XFER_UDMA_2,
-};d42	ULL
-}848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m	XFER_UDMA_48 x0m	X06514DMA_IDE0x0dFLAG8242f_4s ttrx0aCXFE1e	= 2AUTODMA,
-		.ena	Fex63tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};i_d4XFER4mue
+	sp&	3=307045L  intllTODMA,9c62	ULL
-};dc62	},	/* vahpt37_%L
-};d42	ULL
-};dc62	{	XFER_UDMA_2,
-};d42	ULL
-}848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m	XFER_UDMA_48 x0m	},
+	{	XFER_UDMA_0,	0x1c829c6265tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};65XFER4mue
+	sp&	3=307045L  intllTODMA,9c62	ULL
-};dc62	},	/* vahpt37_%L
-};d42	ULL
-};dc62	{	XFER_UDMA_2,
-};d42	ULL
-}848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m	XFER_UDMA_48 x0m	X06514DMA_IDE0x0dFLAG8242f_4s ttrx0aCXFE1e
-cht_h"TA6S};seMA_3,	0x67tu{	XFER_UDMA_2,	0h;,M_(*);			0x}
-};xxXFER4mue
+	sp&	3=307045L  intllTODMA,9c62	ULL
-};dc62	},	/* vahpt37_%L
-};d42	ULL
-};dc62	{	XFER_UDMA_2,
-};d42	ULL
-}848242f_he time of Ly5SC MHz timi 	=_0,e,
-		.)	9)Nm4s tu{	848242f_4mue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-{
-	{	XFER/}9UDMA_0,	0x1c829  x0m	XFER_UDMA_48 x0m	,	0x1A+x29)Nmsx42
B9eD2	e
-	{	XFER/}9UDMA_0,	0x1c8s tu{	m04,	0Sr1c829  x0m04,	0S2	},
+	{	XFER_U	848-  +	{oldFhce_t hpt366_chip0x1c8e9c62	eoldFh= ht_h"TA6S};seMA_3,	0x1c8;2680DoldF6S};=_0_9UDMA_u3td88e_0,	0x1c829  x0m04,	0Sr1c,	0Sr1_ L buF= Oh},
-	{  6EHs2944      {       XFER_PIO_3,     0x06414e42      },
-        {       XFER_PIO_2,  1+	{	XFER_PIOhS75t chtwe3MWit_h"TA6___ALL7MA						    XFERSPLIT_BYTE  0x06414eSPLIT_BYTE(B,H,L)	((H)=(B>>4), (L)=(B-((B>>4)<<4)))_UDMA_3,	0x1c8edc62	42      }heckme */
-	{	XFE che+
+#define F_LOW_PCI_				dNGlUDs2985le	= ht_h"TA6S};seMA_3,	0x1c8;2680D4"uA6S};=_062	},
+
+8;2680D4"uA6S};=_062	},
+
+8;2680D-)0x1c829  x0m04,	0try {
-i 		 ,		ID,
0eO+		.name		= "HPT3  1+	{	XFER		0x0dl1
-	{	XFER_P_u ie 0120829 }
-};DMA_1ctatic strucs0tr4_BOARD,
-0	-{
-	{	XFER/}9UDMA_0,	0x1c829  	/*A RAUTODMA,DMA-0_},
-		SYNC_ERRDY_EN	0xC09-A-0_},
-		SYNC_IN8ddc80_UDMAontrol/* 2	5	0x0es.
- * 4 t_chipsvs. 	},
-*2,	0xs,DMA-0_},
-		ERRDY_EN	0x40_UDMAontrol/* 2	5	0x0es.
- * 4 t_chipsvs. 	},
-*2,	0xs,DMA-0_},
-		IORDY_EN	0x20_UDMPIO: IOREADY,DMA-0_},
-		PREFETCH_EN	0x10_UDMPIO: PREFETCH}
+}-A-0_},
-		PA38ddc68_UDMPIO"A"_hpt366,DMA-0_},
-		PA28ddc64_UDMPIO"A"_hpt366,DMA-0_},
-		PA18ddc62_UDMPIO"A"_hpt366,DMA-0_},
-		PA0C AC31_UDMPIO"A"_hpt366,DMA9  	/*B RAUTODMA,DMA-A-0_},
-		MB28ddc80_UDM	},"B"_hpt366,DMA-0_},
-		MB18ddc40_UDM	},"B"_hpt366,DMA-0_},
-		MB0C AC20_UDM	},"B"_hpt366,DMA-A-0_},
-		PB4		0x10_UDMPIO8242f_ 1:0,DMA-A-0_},
-		PB38ddc68_UDMPIO"B"_hpt366,DM_UDMPIO flow Control/et	= DMA-0_},
-		PB28ddc64_UDMPIO"B"_hpt366,DM_UDMPIO 4 DMA-0_},
-		PB18ddc62_UDMPIO"B"_hpt366,DM_UDMPIO 3 half DMA-0_},
-		PB0C AC31_UDMPIO"B"_hpt366,DM_UDMPIO 3 othMA,half DMA9  	/*C RAUTODMA,DMA-0_},
-		IORDYp_NO_SPEEDddc4Fy-six_u i	SPEED_DIS AC3FA-A-0_},
-			},RQp8ddc80A-0_},
-		IORDYp8ddc40A-0_},
-			},R_EN	 AC20A-0_},
-			},W_EN	 AC109-A-0_},
-		MC38ddc68_UDM	},"C"_hpt366,DMA-0_},
-		MC28ddc64_UDM	},"C"_hpt366,DMA-0_},
-		MC18ddc62_UDM	},"C"_hpt366,DMA-0_},
-		MC0C AC31_UDM	},"C"_hpt366,DMA-2680D-/mLV/(2f=,
-6,3 */
b0   i_d4}
-};
_7r 90S5,	0x1cae9c 0x1A_1ctw5,	0x1cae XFER"ti}V/(2f=,
-6,3 */
b0   65	0,		0x0d029d29 "IBivers/il1
-	CLs+
+8;2680D-/mLV/(2f=,
-6,3 */
b0   xxnit_dma_hpt366,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= OF
b0   xxnit_dma_hpt366,
-		 90Sa3	}8>	0x1cae X									dNGlUDs297)o	{	Xxxn-	{	XFER_MW_DMA_1,	0x22808254	},
-	{	)o	{	Xxxn-	{	XFER_MW_8082ea	},
-
-	{	XFER_PIO_4,	0x0a81f442	},
-	{2i_9c62	eist_"},
-	E0(PI},
-	si_dC- Ne)Nms7	},	/*xa0ch8e,
a0ch8R_U8		46168-504,	0x12ac8242	},
-	{	XFER_UD		
i_d4XF-R4mue
+	sp&	3=307045L  intllTODMA,9c62	UL-
-};dc62	},	/* vahpt37_%L
-};d42	UL-
-};dc62	{	XFER_UDMA_2,
-};d42	UL48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	XFER_UDMA_16 c8242	},
-1	/*xa0ch8e,
a0ch8R_U8		02168-504,	0x12ac8242	},
-	{	XFER_UD		
i_d4XF-R4mue
+	sp&	3=307045L  intllTODMA,9c62	UL-
-};dc62	},	/* vahpt37_%L
-};d42	UL-
-};dc62	{	XFER_UDMA_2,
-};d42	UL48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	XFER_UDMA_48 x-m	X06514DMA_IDE0x0dFLAG8242f_4s ttr8242	},
-2	/*xa0ch8e,
a0ch8R_U8		63168-504,	0x12ac8242	},
-	{	XFER_UD		
i_d4XF-R4mue
+	sp&	3=307045L  intllTODMA,9c62	UL-
-};dc62	},	/* vahpt37_%L
-};d42	UL-
-};dc62	{	XFER_UDMA_2,
-};d42	UL48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	XFER_UDMA_48 x-m	{	XFER_UDMA_6,	0x1280824829c6265168-504,	0x12ac8242	},
-	{	XFER_UD		
65XF-R4mue
+	sp&	3=307045L  intllTODMA,9c62	UL-
-};dc62	},	/* vahpt37_%L
-};d42	UL-
-};dc62	{	XFER_UDMA_2,
-};d42	UL48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	XFER_UDMA_48 x-m	X06514DMA_IDE0x0dFLAG8242f_4s ttr8242	},
-4UDMA_6,	0x1280824829c6267168-504,	0x12ac8242	},
-	{	XFER_UD		
xxXF-R4mue
+	sp&	3=307045L  intllTODMA,9c62	UL-
-};dc62	},	/* vahpt37_%L
-};d42	UL-
-};dc62	{	XFER_UDMA_2,
-};d42	UL48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
,e,
-		.)	9)Nm4s tu{	848242f_4-ue
+	sp&	=_0,e	c828242f	_0,	,FER__UDMA+x29)Nmsx42
B9eDwif	= iniy_three_base_hpt374[] = {
-	XFER_UDMA_48 x-m	F_LOs eadc62	},	/*42      },5f a	0x06814esctive tim.7
-	{	0,	iixFEe 2or 9s	{	XFER_UDMAiixFE= ht_h"TA6S};seMA_3,	0x1iixFE0d0anDD1-14xty_49:03,
-	si_device_t hpt366_chip0x1ciixFE0d0anDD2-06 05:02:40hp		.e		(w,
-238292623},
-	{	XFER_MW_DMA_1,	0x2c829266	},	/* checiixF,	/*aE80D-/mLV/(2no_ciix_t *);
+x29)N14ea730,19 +528,510x06814ea7	},
-				0x06514e33
-	{	XFER_PIO_1,		0-stat29)N- *	},
-	{	XFER_iix	R/}9UDMbaodma 4 IDEpt366,
+		.N- *	@PI}: PIIX 0x0 42	},
N- *	@P: IDEpp0xpt3foN- *N- *	E	sp&	er acxp fixup/* 4 * acPIIX AontrollMA,
nd * an per* 4mN- *	aE80Dndard	0x0 0x0 {	XFE_hpt366atic ineFextra	366_ALLOW,
-	{	XFER_iixtra	Fextra	Fextra	Fextra	Fextra	Fextra	Fee_t hpt366_chipsets[] _829c62     0_22e	t[] = {
c8edc62	DECLAR_4sIIXtup	(0x12_ra	) \ea7e2 6	}2&:},
	0x1280820x12_ra	,}2&:},
	ue
+	sp&	3=307045L  intllTODMiix,2&:},
	ue
+		},	/* vahpt37_%L
iix,2&:},
	_UDMA_1,	},
-	}2&:},
	_0,	0x121882ea	},
}2&:},
	6814esctive tim.7
1	{	0,		08+	74e21_3	{	0,		08+		74\9151u 		.bo,c6231
-	{	XFE
-stati_e*4nd MWit_h"TA6_edc6214esc2iix_A6_et3fo-	E0(PI},
-	si_dC- Nea7	/*},	/*	DECLAR_4sIIXtup	("sIIXa"),ea7	/*}1	/*	DECLAR_4sIIXtup	("sIIXb"),eaea7e22	s	= 2AUTODMA,
-		.eMsIIX488eSeY"s:bntation. these p:3
iix,LL
-}848242f_he time of Ly5SC MHzNbo,rx0aCC,4,		.bo,rx0aCC,4,6D	{	0,		08+	74e216F	{	0,		08+		7Fer 906804	},igned int inaer 9eaea7	/*}3	/*	DECLAR_4sIIXtup	("sIIX3"),ea7	/*}4	/*	DECLAR_4sIIXtup	("sIIX4"),ea7	/*}5	/*	DECLAR_4sIIXtup	("ICH0"),ea7	/*}6	/*	DECLAR_4sIIXtup	("sIIX4"),ea7	/*}7	/*	DECLAR_4sIIXtup	("ICH"),ea7	/*}8	/*	DECLAR_4sIIXtup	("sIIX4"),ea7	/*}9	/*	DECLAR_4sIIXtup	("sIIX4"),ea7	/*10	/*	DECLAR_4sIIXtup	("ICH2"),ea7	/*11	/*	DECLAR_4sIIXtup	("ICH2M"),ea7	/*12	/*	DECLAR_4sIIXtup	("ICH3M"),ea7	/*13	/*	DECLAR_4sIIXtup	("ICH3"),ea7	/*14	/*	DECLAR_4sIIXtup	("ICH4"),ea7	/*15	/*	DECLAR_4sIIXtup	("ICH5"),ea7	/*16	/*	DECLAR_4sIIXtup	("C-ICH"),ea7	/*17	/*	DECLAR_4sIIXtup	("ICH4"),ea7	/*18	/*	DECLAR_4sIIXtup	("ICH5-SATA"),ea7	/*19	/*	DECLAR_4sIIXtup	("ICH5"),ea7	/*20	/*	DECLAR_4sIIXtup	("ICH6"),ea7	/*21	/*	DECLAR_4sIIXtup	("ICH7"),ea7	/*22	/*	DECLAR_4sIIXtup	("ICH4"),ea0x1A+x29)Nmsx42iix_
-	{	XFER/}9UDMA_0,	0x1c8sIIX ,	0Sr1c8214ea757},
-	87		0x14886231
-	extra	Fextra	FeC- &2iix_A6_et3fo-id	},
-		r_si_d]x1A+pt366_chid	}W,
-	{	XFE0_22e	t[] +3{	/* 2 */
+		.naA_1,		ic ineF%A	/* 2 68_A+x29)N	0x06814esctive tim.7
-	{	0,	iixFhce_t hpt366_chip0x1ciixFh= ht_h"TA6S};seMA_3,	0x1iixFh0d0anDD1-14xty_49:03,
-	si_devic x0m04,	0Sr1c,	0Sr1_ L buF= Oh},
-	{  6EHs265      {       XFER_IIXt   0x06414e4IIXt   ch8e,
a0ch8e,
a0ch8e	},
-ch8
-	{	XFEe 20x29)Nmsx42
_0,	,FER__UDMA+x29)Nmsx42
B9eD,
-		.extra		= 240
-_iixtra	Fextra	Fextra		.channels	= 2,
-		.autodma	= AUTODMA,
-		.a	366_ALLOW,
-	intllTODMiixnit_dma_hpt366,
-		 90Sa3	}8>	0x1cae X									dNGlUDs297)iixnFER_PIO_4,	0x06414c8edc62	DECLAR_4sIIXtup	(0x12_ra	) \e-	x0aCC,4,		.b	0x1280820x12_ra	,}2&:-504,	0x12ac8242	},
-	{	XFER_iix,2&:-,
	ue
+	sp&	3=307045L  intllTODMiix,2&:-,
	ue
+		},	/* vahpt37_%L
iix,2&:-,
	_UDMA_1,	},
-	}2&:-,
	_0,	0x121882ea	},
}2&:-,
	6814esctive tim.7
1	{	0,		08+	74e21_3	{	0,		08+		74\9-51u 		.bo,c6231
-	{	XFE
-st-m	F_at29N- *	Tsp&	eof * acvarious PIIX Aapability b				sN- *N- *366 R_PIO_4,	0x0a81f442	},
-	{2iix_A6_et3fo-	E0(PI},
-	si_dC- Ne-7	/*},	/*	DECLAR_4sIIXtup	("sIIXa"),e-7	/*}1	/*	DECLAR_4sIIXtup	("sIIXb"),e-e)Nms7	}2	/*xa0ch8e,
a0ch8MsIIX488-504,	0x12ac8242	},
-	{	XFER_iix,:-,
	ue
+		},	/* vahpt37_%L
iix,L48254	},
-	{	XFER_UDMA_0,	0x1218NIO_0,		0x06814esctive tim.76D	{	0,		08+	74e216F	{	0,		08+		7Fup_hpt37x(struct pci_dev -p_ce-e)N	/*}3	/*	DECLAR_4sIIXtup	("sIIX3"),e-7	/*}4	/*	DECLAR_4sIIXtup	("sIIX4"),e-7	/*}5	/*	DECLAR_4sIIXtup	("ICH0"),e-7	/*}6	/*	DECLAR_4sIIXtup	("sIIX4"),e-7	/*}7	/*	DECLAR_4sIIXtup	("ICH"),e-7	/*}8	/*	DECLAR_4sIIXtup	("sIIX4"),e-7	/*}9	/*	DECLAR_4sIIXtup	("sIIX4"),e-7	/*10	/*	DECLAR_4sIIXtup	("ICH2"),e-7	/*11	/*	DECLAR_4sIIXtup	("ICH2M"),e-7	/*12	/*	DECLAR_4sIIXtup	("ICH3M"),e-7	/*13	/*	DECLAR_4sIIXtup	("ICH3"),e-7	/*14	/*	DECLAR_4sIIXtup	("ICH4"),e-7	/*15	/*	DECLAR_4sIIXtup	("ICH5"),e-7	/*16	/*	DECLAR_4sIIXtup	("C-ICH"),e-7	/*17	/*	DECLAR_4sIIXtup	("ICH4"),e-7	/*18	/*	DECLAR_4sIIXtup	("ICH5-SATA"),e-7	/*19	/*	DECLAR_4sIIXtup	("ICH5"),e-7	/*20	/*	DECLAR_4sIIXtup	("ICH6"),e-7	/*21	/*	DECLAR_4sIIXtup	("ICH7"),e-7	/*22	/*	DECLAR_4sIIXtup	("ICH4"),e_LOs eadc62	},	/*4IIXt 5f a	0x06814esctive tim.7
-	{	0,ser tiworksFEe 2or 9s	{	XFER_UDMser tiworksFE= ht_h"TA6S};seMA_3,	0xser tiworksFE0d0a7aa	},	/* 0R_PI},
-	si_device_t hpt366_chip0x1ser tiworksFE0d0anDD2-06 05:15:30hp		.e		(w,
39x26539x		0x068XFER_MW_DMA_1,	0x2c829266	},	/* cheser tiworksFh"y_six_u ieSVWKS_CSB5_REVISIt pNEW	0x92,	/*min 0x0_REVISIt pID/* 4     5 (A2.0),DMA_0_},
-	eSVWKS_CSB6_REVISIt 	0xa0,	/*min 0x0_REVISIt pID/* 4     4 (A1.0),DMA_;
	/*Seagate Barracuda ATA IV Family*2,	0xs,in     /et	= 5
+ * Aan heckrun * air FIFOs0,	0x1usA_0,ith * acCSB5,DMA_+#define F_LOW_PCI_svwks_bad82ea100e		= ",
-
ST3d0a11AMA_4,	ST340a16AMA_4,	ST360021AMA_4,	ST380021AMA_4,,	0x128c1{	XFER_PIO_3,svwks_rI},sion	= 0;	XFER_PIOit_dma_hpt366,
-isa,		0x114ea78{	XF+593,440x0681{	/* 2 */
+		.naA_1,		ic ineF%A	/* 2 68_A+4nd MWit_h"TA6_edc6214escser tiworkseist_"},
-	E0(PI},
-	si_dC- Nea7e22	s_   XFERn49ty_six_SvrWks OSB4tu{	XFER_UDMA_2,	0h;,M_(*);			0svwksXFER4mue
+	sp&	3=307045L  intllTODsvwksXFER4mue
+		},	/* vahpt37_%LsvwksXFER4m  },
-	{       XFu8;d4	},
       },
-	{       -IO_4-	d int inaer 9068extra36\*ODMA,
ll148SvrWks CSB5tu{	XFER_UDMA_2,	0h;,M_(*);			0svwksXFER4mue
+	sp&	3=307045L  intllTODsvwksXFER4mue
+		},	/* vahpt37_%LsvwksXFER4m;dc62	{	XFER_UDMA_2,svwksXFER4m  },
-	{       XFu8;d4	},
       },
-	{       -IO_4-	d int inaer 9068ex2ra36\*ODMA,
ll148SvrWks CSB tu{	XFER_UDMA_2,	0h;,M_(*);			0csb6XFER4mue
+	sp&	3=307045L  intllTODsvwksXFER4mue
+		},	/* vahpt37_%LsvwksXFER4m;dc62	{	XFER_UDMA_2,svwksXFER4m  },
-	{       XFu8;d4	},
       },
-	{       -IO_4-	d int inaer 9068ex3ra36\*ODMA,
ll148SvrWks CSB tu{	XFER_UDMA_2,	0h;,M_(*);			0csb6XFER4mue
+	sp&	3=307045L  intllTODsvwksXFER4mue
+		},	/* vahpt37_%LsvwksXFER4m;dc62	{	XFER_UDMA_2,svwksXFER4m  },
-	{   1,68ex2ra36\*OD8;d4	},
       },
-	{       -IO_4-	d int inaer ea0x1A+x29)Nmsx4svwks_
-	{	XFER/}9UDMA_0,	0x1c8OSB/CSB4,	0Sr1c829  x0m04,	0S2	},
+	{	XFER_U	ser tiworksFhce_t hpt366_chip0x1ser tiworksFh= ht_h"TA6S};seMA_3,	0xser tiworksF6S};=_0_9UDMA_u3td88e_0,	0x1c829  x0m04,	0Sr1c,	0Sr1_ L buF= Oh},
-	{  6EHs269      {   		    XFERSERVERWORKS_   0x06414eSERVERWORKS_           {       XFER_PIO_2,  1+	{	XFER_PIOhS75t chtwe3MWit_h"TA6___ALL7MA						 u XFERSVWKS_heckme */
-	{	XF6414c8edc62	SVWKS_CSB5_REVISIt pNEW	0x92,	/*min 0x0_REVISIt pID/* 4     5 (A2.0),DMA-0_},
-	eSVWKS_CSB6_REVISIt 	0xa0,	/*min 0x0_REVISIt pID/* 4     4 (A1.0),DMA9  	/*Seagate Barracuda ATA IV Family*2,	0xs,in     /et	= 5
- * Aan heckrun * air FIFOs0,	0x1usA_0,ith * acCSB5,DMA-+#define F_LOW_PCI_svwks_bad82ea100e		= ",--
ST3d0a11AMA_-,	ST340a16AMA_-,	ST360021AMA_-,	ST380021AMA_A_0,	0x1c829  eD,
-		.extra		= 240
-svwks	0,		0x0d029d29 "IBivers/il1
-	CLs+
+8;2680D-/mLV/(2f=,
-6,3 */csb6nit_dma_hpt366,
-		.channels	= 2,
-		.autodma	= AUTODMA,
-		.bootable	= OFsvwks	0,		0x0d029d29 "IB 90Sa3	}8>	0x1cae X									dNGlUDs297svwks	-	{	XFER_MW_DMA_1,	0x22808254	},
-	{	svwks	-	{	XFER_MW_8082ea	},
-
-	{	XFER_PIO_4,	0x0a81f442	},
-	{ser tiworkseist_"},
-	E0(PI},
-	si_dC- Ne)Nms7	},	/*xa0ch8e,
a0ch8SvrWks OSB4tu{-XFER_UDMA_2,	0h;,M_(*);			0svwksXF-R4mue
+	sp&	3=307045L  intllTODsvwksXF-R4mue
+		},	/* vahpt37_%LsvwksXF48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA pci_dev -p_ct pci_0define F_LOsiH	 SvrWks CSB5tu{-XFER_UDMA_2,	0h;,M_(*);			0svwksXF-R4mue
+	sp&	3=307045L  intllTODsvwksXF-R4mue
+		},	/* vahpt37_%LsvwksXF4825;dc62	{	XFER_UDMA_2,svwksXF48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA pci_dev -p_ct pci20define F_LOsiH	 SvrWks CSB6168-504,	0x12ac8242	},
-	{	XFERcsb6XF-R4mue
+	sp&	3=307045L  intllTODsvwksXF-R4mue
+		},	/* vahpt37_%LsvwksXF4825;dc62	{	XFER_UDMA_2,svwksXF48254	},
-	{	XFER_UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA pci_dev -p_ct pci30define F_LOsiH	 SvrWks CSB6168-504,	0x12ac8242	},
-	{	XFERcsb6XF-R4mue
+	sp&	3=307045L  intllTODsvwksXF-R4mue
+		},	/* vahpt37_%LsvwksXF4825;dc62	{	XFER_UDMA_2,svwksXF48254	},
-	{	XF1,68ex2ra36UDMA_0,	0x121882ea	},
-
-	{	XFER_MW_DMA pci_dev -p_e_LOs eadc62	},	/*SERVERWORKS_ 5f a	0x06814esctive tim.7
-	{	0,sgiioc4FEe 2or 9s	{	XFER_UDMsgiioc4FE= ht_h"TA6S};seMA_3,	0xsgiioc4FE0d0anDD1-06 17:35:35,
-	si_device_t hpt366_chip0x1sgiioc4FE0d0anDD2-03 063td821hp		.e		(w,
669x265669x	0x0681	pr"Mak(KERN	{	XF "%s: %s Bus-M_chips   /disa_MWd\n",681	       {	XFERF_LO,id	}F_LO)x1A+ptprob{	XFER_R_UD148c6		0x16f (prob{	XFER_R_UD148c6	-	{	1{	/* 2 -EIOx1A+x68exCreate /proc6_ch   },ixs,DMA 	create_proc_0x0ainDMAfaces(); a	0x06814esctive tim.7
-	{	0,siimageFEe 2or 9s	{	XFER_UDMsiimageFE= ht_h"TA6S};seMA_3,	0xsiimageFE0d0a7aa	},	/* 0R_PI},
-	si_device_t hpt366_chip0x1siimageFE0d0anDD2-03 06319:4base_hpt374[]590},
-	90},
x0681	6f (148c623INL(SATA_STATUS_REG) &{	XF3) !={	XF3) 86231	pr"Mak(KERN	WARNING "%s: relTO phy*2ead,XFER_us=0x%08x\n",681	
+	{	XFEF_LO,i48c623INL(SATA_STATUS_REG)ER_MW		HWGROUP6814ea7->poll14eaeout	= 0;	+W		HWGROUP6814ea7->poll366,= 0;	X		1{	/* 2 */
+	#drted;	X		+	},1{	/* 2 0;		0x06814esctive tim.7
-	{	0,via82cxxxFEe 2or 9s	{	XFER_UDMvia82cxxxFE= ht_h"TA6S};seMA_3,	0xvia82cxxxFE0d0anDD1-30 22:22:t ini	si_device_t hpt366_chip0x1via82cxxxFE0d0anDD2-02 23:24:,	/se_hpt374[]589},
-	89},
x068148c623e		= procC- &via	{	XDs2985x1A+xPT366",
-		.initPPC_MULTIPLATFORM_0,e, _},
-	d(		.initPPC_MULTIPLATFORM) && _},
-	d(		.initPPC32)6231f(_maint-	e== _MACH inrp &&  inrp_A_4,e== _CHRP_Pegasos) 8623148c623irq
-	{	XFER4	},
-	 ?*15	:/* ;D,
+		0x06814esctive tim.7_PIniband/hw/mthca/mthca_cqFEe 2or 9s	{	X_PIniband/hw/mthca/mthca_cqFE= ht_h"TA6S};seM_PIniband/hw/mthca/mthca_cqFE0d0anDD1-15/* 001:49ini	si_device_t hpt366__PIniband/hw/mthca/mthca_cqFE0d0anDD2-03 06342:t9ase_hpt374[] == {
-	{{	XFER_U1	
+*fr	= ,= 0;	X		1+	},1	XFER_PIO_4,(&(*cur_qp7->O_4,ER_MW		6f (atomic(PIc_and_test(&(*cur_qp7->refcr1ct))_U1	
+wake_up(&(*cur_qp7->wait);	X		+	}	X		XFER_O_4,(&PI}->qp_Aa_MW.O_4,ER_	0x06814esctive tim.7_PIniband/hw/mthca/mthca_qpFEe 2or 9s	{	X_PIniband/hw/mthca/mthca_qpFE= ht_h"TA6S};seM_PIniband/hw/mthca/mthca_qpFE0d0anDD1-15/* 001:50ini	si_device_t hpt366__PIniband/hw/mthca/mthca_qpFE0d0anDD2-03 06342:t9ase_hpt374[]1323},
+1323}8FER_U1	
+break;	X		1+	}	+W		break;	+	X		case   :681		((s,		0x0mthca_ud	{	gW_D wqa7->lkey =_U1	
+cpu_to_be32(to_mah(wr->wr.ud.ah7->keyER_	0x06814esctive tim.7_put/mousA_evFEe 2or 9s	{	X_put/mousA_evFE= ht_h"TA6S};seM_put/mousA_evFE0d0a7aa	},7 01:21:1},
-	si_device_t hpt366__put/mousA_evFE0d0anDD1-,	/*	si6:49ini	si_d(w,
46 ie22	46 ie22
-	{	XFER_M6f (!p->dx && !p->dy && !p->dz) Ne)NM6f (list->tail !={list->head)_U1	
list->tail = (list->tail + 1) % PACKET_QUEUE_LEN;681	6f (list->tail =={list->head)_ 1	
list->ready = 0;	+W	-	{e	+W		list->tail = (list->tail + 1) % PACKET_QUEUE_LEN;681XFER_MXFER_PIO_4,		0x06814ea7	list->pack	XD				0x06514e21	0x06814esctive tim.7sdn/hisax/avm_a1pFEe 2or 9s	{	Xsdn/hisax/avm_a1pFE= ht_h"TA6S};seMsdn/hisax/avm_a1pFE 0x42
-2-18 19:42:1},
-	si_device_t hpt366_sdn/hisax/avm_a1pFE 0x4nDD2-03 06342:40hp		.e		(w,
231},
-231},

-	{	cs23irq
-	card->para[0]x1A+xPT	outb(cs23hw.avm.cfg_reg+ASL1_OFFSET, ASL1_W_ENDc62_S0		0x1byteout(cs23hw.avm.cfg_reg+ASL1_OFFSET, ASL1_W_ENDc62_S0		0 1byteout(cs23hw.avm.cfg_reg+ASL0_OFFSET,	XF0)	0 1HZDELAY(HZ / 5 + 1)	0 1byteout(cs23hw.avm.cfg_reg+ASL0_OFFSET,ASL0_W_RESETe21	0x06814esctive tim.7sdn/hisax/7sdnhdlcFEe 2or 9s	{	Xsdn/hisax/7sdnhdlcFE= ht_h"TA6S};seMsdn/hisax/7sdnhdlcFE 0x42
-7-11 01:5 0R1init_setup_hb"TA6S};seMsdn/hisax/7sdnhdlcFE 0x4nDD2-03 063t0si6hp		.e		(w,
308x265308x26ER_U1	
+hdlcER4rcC- 4rc_ccitt_byte(hdlcER4rc,i4dlcERshift_N/
b0	}	X				// good bytel  ce6S}d_U1	
+6f (dsize--) Nea7	
+6f (4dlcERdstpos < dsize) 86231			dst[4dlcERdstpos++		= 4dlcERshift_N/
;	X		1	} -	{e 86231			// fr_LO too-
-	{1	0x06814esctive tim.md/dm-cryptFEe 2or 9s	{	md/dm-cryptFE= ht_h"TA6S};semd/dm-cryptFE0d0a7aa1-15/*9:,	:25,
-	si_device_t hpt366md/dm-cryptFE0d0anDD2-03 07:L bu4hp		.e		(w,
329x265329},
x0688888888888888888888s,		0x0bio *base_bio, AUTODMA,
-		.*bio_vec_0xx9c62	},s,		0x0bio *bioR_MWAUTODMA,
-		.nr_iovecs	= dm_div_up(size, PAG2_SIZE		0x1AUTODMA,
-		.nr_iovecs	= (size + PAG2_SIZE - 1) >> PAG2_SHIFT;	X	-		.gfp_tu20 = GFP_NOIO | __GFP_HIGHMEM		0x16814ea7	},
-				0xC- 4urs.
-->			0x14986UTODMA,
-		.b;1	0x06814esctive tim.md/dm-logFEe 2or 9s	{	md/dm-logFE= ht_h"TA6S};semd/dm-logFE0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dm-logFE0d0anDD2-03 07:L bu4hp		.e		(w,
129x265129},
x068s,		0x0log_c62	},s,		0x0dm_#drgTO *ti;	X	-		.touched;	-	sec14e_tl  gion_size	0x1A-		32_tl  gion_size	0986UTODMA,
-		.  gion_cr1ct;681{	gion_t sync_cr1ct;68	(w,
214e21+214e21
-	{	enum sync sync = DEFAULTSYNC0	}	X	s,		0x0log_c6*lc;	-	sec14e_tl  gion_size	0x1A-		32_tl  gion_size	0986UTODMA,
-		.  gion_cr1ct;681size_x0bitlTODsize	09	(w,
313,1},+313,1},ER_U1	}681XFER-+6f (sscanf(drgv[0], SECTOR8242MAT, &  gion_size) !={1) Nea76f (sscanf(drgv[0], "%u", &  gion_size) !={1) NeU1	DMWARN("invalid.  gion size s,	366");	X		{	/* 2 -EINVAL;681XFER-+  gion_cr1ct	= dm_div_up(ti->len,l  gion_size[] +3{	gion_cr1ct	= dm_sec14e_div_up(ti->len,l  gion_size[] }	X	lc = kmal			(sizeof(*lc), GFP_KERNEL);	X	6f (!lc) Ne74[]508x265508x26ER_U1{	/* 2 A_1,		header(lc));
-static ineFsec14e_tlc4ea_gTO_  gion_size(s,		0x0dirtyD		gW_		g)+4nd MWitA-		32_tlc4ea_gTO_  gion_size(s,		0x0dirtyD		gW_		g)+62	},s,		0x0log_c6*lc	= (s,		0x0log_c6*)0logER4ontext;681{	/* 2 lcER  gion_size	0(w,
616x265616x26ER_U1	break;	X	{	case STATUSTYPE_TDc62:_U1	DMEMIT("%s %u " SECTOR8242MAT " ", },gERA_4,FEF_LO,ea7	DMEMIT("%s %u %u ", },gERA_4,FEF_LO,e81	       lcERsync == DEFAULTSYNC ?*1 : 2, lcER  gion_size);	X		DMEMIT_SYNC0	}1XF(w,
637},
-637},
x068XF	case STATUSTYPE_TDc62:_X		* 4mat(PI}_t(bux0es, lcERlog_PI}->bPI}->bP_PI}ER_MW	DMEMIT("%s %u %s " SECTOR8242MAT " ", },gERA_4,FEF_LO,ea7	DMEMIT("%s %u %s %u ", },gERA_4,FEF_LO,e81	       lcERsync == DEFAULTSYNC ?*2 : 3, bux0es,e81	       lcER  gion_size);	X		DMEMIT_SYNC0		0x06814esctive tim.md/dm-logFhce_t hpt366md/dm-logFh= ht_h"TA6S};semd/dm-logF6S};=_009-22/*333 0R7init_setup_hb"TA6S};semd/dm-logF6S};=nDD2-03 07:L bu4hp		.e		(w,
39x26539x26ER_U1 * Re},ix0xs,* acsmal	e		  ize of.  gion that,* ac		gWcan_U1 * deal0,ith._U1 */	-	sec14e_tl(*gTO_  gion_size)(s,		0x0dirtyD		gW_		g)	0x1A-		32_tl(*gTO_  gion_size)(s,		0x0dirtyD		gW_		g)	0 6888888888/*_U1 * A predicate to say0,	0thMA,a.  gion is clean hr-	{	.		0x06814esctive tim.md/dm-raid1FEe 2or 9s	{	md/dm-raid1FE= ht_h"TA6S};semd/dm-raid1FE0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dm-raid1FE0d0anDD2-03 07:L bu4hp		.e		(w,
67},
-67},
x068s,		0x0mirr4e_lTO;68s,		0x0  gion_hash62	},s,		0x0mirr4e_lTO *ms;	-	sec14e_tl  gion_size	0x1A-		32_tl  gion_size	0986UTODMA,
  gion_shiftx1A+x68exholds persTODM		.  gionXFER_= DMA74[]135x265135x26ER_UD_},
-	eMIN_REGIONS 64_UD_},
-	eMAX_RECOVERY 1aE80D-/mLV/(2rh_R_UD1s,		0x0  gion_hash6*rh, s,		0x0mirr4e_lTO *ms
-
-	888s,		0x0dirtyD		gW_		g, sec14e_tl  gion_size,ea7	888s,		0x0dirtyD		gW_		g, A-		32_tl  gion_size,e81	   {	gion_t nr_{	gions9c62	},
UTODMA,
-		.nr_buck	Xs, max_buck	Xs	0(w,
871},
-871},
x0688* TdrgTO functions688*---------------------------------------------------------------DMA FER_PIOit_dma_mirr4e_lTO *al			_4ontext(
UTODMA,
-		.nr_mirr4es
-
-	,1	Xec14e_tl  gion_size,ea7				A-		32_tl  gion_size,e81	,1	X,		0x0dm_#drgTO *ti,e81	,1	X,		0x0dirtyD		gW_dl9c62	(w,
894},
-894},
x068XF	ms23ti	= ti;	X	ms23nr_mirr4es	= nr_mirr4es;	-	ms23nr_{	gions	= dm_div_up(ti->len,l  gion_size[] +3ms23nr_{	gions	= dm_sec14e_div_up(ti->len,l  gion_size[] }3ms23in_sync = 0;FER_M6f (rh_R_UD1&ms23rh, ms
 dl,l  gion_size, ms23nr_{	gions)) Ne74[]916x265916x26ER_U1kfr	=(ms));
-static ineFinl
-	e-		.ac_2, _  gion_size(s,		0x0dm_#drgTO *ti, sec14e_tlsize[+4nd MWit_nl
-	e-		.ac_2, _  gion_size(s,		0x0dm_#drgTO *ti, A-		32_tlsize[+88623{	/* 2 !(size % (PAG2_SIZE >> 9) || (size & (size - 1)) ||e81	 size > ti->len)0		0x06814esctive tim.md/dm-s,	3peFEe 2or 9s	{	md/dm-s,	3peFE= ht_h"TA6S};semd/dm-s,	3peFE0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dm-s,	3peFE0d0anDD2-03 06342:t9ase_hpt374[]21},
-21},

-	{	A-		32_tls,	3pesx1A+x68exT acsize of.this #drgTO / num.ls,	3pes */	-	A-		32_tls,	3pe_width] +3sec14e_tls,	3pe_width] A+x68exs,	3pe chunkcsize DMA 	A-		32_tlchunk_shiftx1	0x06814esctive tim.md/dm-Aa_MW.Ee 2or 9s	{	md/dm-Aa_MW.E= ht_h"TA6S};semd/dm-Aa_MW.E0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dm-Aa_MW.E0d0anDD2-03 07:L bu4hp		.e		(w,
58x26558x26ER_U/)Nmsx Similar to ceil366(log_size(n))Nmsx/utodma	= AUTODMA,
-		.boXD		g(16814ea7	},
-	n8082ea	},
-
-	{ base)+4nd MWitAUTODMA,
-		.boXD		g(16814ea7	-		.n, AUTODMA,
-		.base)+886231		.  sult = 0;FER	0x06814esctive tim.md/dm.Ee 2or 9s	{	md/dm.E= ht_h"TA6S};semd/dm.E0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dmFE0d0anDD2-03 07:L bu4hp		.e		(w,
331 {
-331 {
ER_U1 */R_M6f (ti->split_io) NeU1	sec14e_tlbr1c8aryR_MW	br1c8ary	= dm_rr1c8_up(offlTO + 1, ti->split_io) - offlTOOs e+W	br1c8ary	= ((offlTO + ti->split_io) & ~(ti->split_io - 1))ea7		   - offlTOOs81	6f (len > br1c8ary)_ 1	
len	= br1c8aryR_,
+		0x06814esctive tim.md/dmFhce_t hpt366md/dmFh= ht_h"TA6S};semd/dmFh0d0anDD1-,5/*33t0s21hp		.e		evice_t hpt366md/dmF6S};=nDD2-03 07:L bu4hp		.e		(w,
143,21h+143,2},ER_U8_A+x29
- * Aeil366(n / size) * size
+ * Ceil366(n / sz)Nmsx/utodma	= _nl
-	e82ea	},
-
-	{ dm_rr1c8_up(16814ea7	},
-	n8082ea	},
-
-	{ size[+t hpt82ea	},
-
-	{ r	= n % size	0pt366_chin + (r ?*(size - r) : 0[] = {
c8edc62	dm_div_up(n80sz) (((n) + (sz) - 1) / (sz)49ty_six_u iedm_sec14e_div_up(n80sz) (4\91{4\915sec14e_tl_r	= ((n) + (sz) - 1);4\915sec14e_div(_s, (sz)4;4\915_r;4\91}4\91)_A+x29
- * Ceil366(n / size)
+ * Aeil366(n / size) * size
msx/utodma	= _nl
-	e82ea	},
-
-	{ dm_div_up(16814ea7	},
-	n8082ea	},
-
-	{ size[+t hpt366_chidm_rr1c8_up(n80size) / size	0p {
c8edc62	dm_rr1c8_up(n80sz) (dm_div_up((n), (sz)4 * (sz)49 aE80D-/mLV/lMA_1,	c14e_tlto_sec14e(16814ea7	},
-	n)+886	0x06814esctive tim.md/md.Ee 2or 9s	{	md/md.E= ht_h"TA6S};semd/mdFE0d0anDD1-19 04:23:30hp		.e		evice_t hpt366md/mdFE0d0anDD0d08 02:35:23hp		.e		(w,
336 {
-336	XFER_U1s,		0x0completion x0xct;6811		.  tx1A+ptbio_gTO(bio	XFER23{w |= (1 << BIO_RW_SYNC[] }	X	bio->bi_bPI}	= b		0x114ea937 {
-935x8
x068XF	max_PI}	= 0;	X	ITERATE_Rup	(mdF%A	rF%A2,tmp)e)NM6f (rF%A2->desc_nr > max_PI})_U1	
max_PI}	= rF%A2->desc_nr;	+W	6f (rF%A2->desc_nr+1 > max_PI})_+1	
max_PI}	= rF%A2->desc_nr+1;	X	_U1sb->max_PI}	= cpu_to_le32(max_PI});	X	* 4 (i=0; i<max_PI};i+1)_14ea955},
+953},

-	{	XFER_MXbER  checky_offlTO = cpu_to_le64(0[],	/*notlsupported yTO *36\*XbERsb_csum
-	calc_sb_1_csum(sb 2 68_A+x	(w,
1474ie22	1473,13

-	{	XFE	disk->major	= MAJOR(PI});	X	disk->first_minor	= uALLO<< shiftx1-+6f (partitioned)0x16f (partitioned) NeU1	spr"Maf(disk->disk_F_LO,i"md_d%d", uALLER_MW-	{e	+W	spr"Maf(disk->devfs_F_LO,i"md/d%d", uALLER_+	} -	{e 86231spr"Maf(disk->disk_F_LO,i"md%d", uALLER_+		spr"Maf(disk->devfs_F_LO,i"md/%d", uALLER_+	}	X	disk->fops	= &md_fops;	X	disk->pr"vate_si_dC- mdF%A;	X	disk->queueC- mdF%A->queuex114ea244{	XF+2444,90x1488623md _ PI}_t *rF%A;	X0x16f (mdF%A->pers == 0,	0-	{	1{	/* 2 -ENOup	;	+	X	rPI}	= dc6d_ PI}(mdF%A	 PI});	X	6f (!rPI})_ 	1{	/* 2 -ENOup	;	(w,
3364ie22	3369,1},ER_U1R_UDMwaitqueue	head1&mdF%A->  checky_wait);	X	lastac_2,  = 0;FER-+6f (j)0x16f (j>2) NeU1	pr"Mak(KERN	{	XF _ 1	
"md: relut366,  checky of.%s from c_2, po"Ma.\n",681	
mdF_LO(mdF%A)ER_+		mdF%A->4urseresync = jR_+	}	X6811c829 (j < max_sec14es) 862311		.sec14es;	(w,
3449x2653456},
x068XF	6f (!test_bUD1MD_RECOVERY_ERR, &mdF%A->  checky) &&_U1    mdF%A->4urseresync > 2 &&_-1    mdF%A->4urseresync > mdF%A->  checky_cp) Nea7    mdF%A->4urseresync >= mdF%A->  checky_cp) Ne81	6f (test_bUD1MD_RECOVERY_INTR, &mdF%A->  checky)) 86231	pr"Mak(KERN	{	XF _ 1	

"md: c_2, po"Ma366,  checky of.%s.\n",6(w,
3657},
-3664},
x068	* 4 (minor=0; minor	<eMAX_MD_up	S; ++minor)_ 	1devfs_mk_bPI}(MKup	(mdp_tujor, minor<<MdpMinorShift),681	
888888S_IFBLK|S_IRUSR|S_IWUSR
-
-	,888888"md/d%d", minor);ea7		   888"md/mdp%d", minor);e 68XF	rAUTODMAere	XFE_notifier1&md_notifier)0		0x06814esctive tim.md/raid5.Ee 2or 9s	{	md/raid5.E= ht_h"TA6S};semd/raid5.E0d0anDD1-30 22:33:46hp		.e		evice_t hpt366md/raid5.E0d0anDD0d08 02:35:58ini	si_d(w,
49x26549},
x0688* This macro is usA_0to deDMAmMA_1* ac'next'0bio in,* ac	TOD, ghptn,* acsec14e688* of * ac4urs.
-xs,	3pe+42	},
N ,DMA-0_},
-	er5_next_bio(bio, sec1) (4( bio->bi_sec14e + (bio->bi_size>>9)	<esec1 + STRIPE_SECTORS)E? bio->bi_next : 0,	0-	{0_},
-	er5_next_bio(bio, sec1) (4( (bio	->bi_sec14e + ((bio	->bi_size>>9)	<esec1 + STRIPE_SECTORS)E? (bio	->bi_next : 0,	0-	U/)Nmsx T acfollow366,Aan be usA_0to debug * act hpt3N ,DMA(w,
23{	XF+234e21
-	{}9 aE80D-/mL80825unplug_	},
-s(mdF%A_t *mdF%A);+4nd MWit80825raid5_unplug_	ic inerequest_queue	t *q)c1{	XFER_PIOs,		0x0s,	3pe_head *gTO_acthpt_s,	3pe(raid5_ER_P	t *ER_P, sec14e_tlsec14e,e81	,1	  8881		.pd_0xx,LV/(2nob				) 0(w,
612,1165613ie22
-	{_A+x29
- * Copy5			d betwe0x1c8page in,* acs,	3pe cac_2,,
nd one hr-more bion
- * T acpage could al14e0,ith * acmidd&	eof * acbio,  4 * are could be 
- * sx0xral bion, eac_0,ith sx0xral bio_vecs,x1c8c_0check parteof * acpage
- * Multiple bion arac	TnkA_0tog0thMA,on bi_next.  T aracmay be FER_UsN- * at,* acend of.this 	TOD.  We ignore * am.
+ * Copy5			d betwe0x1c8page in,* acs,	3pe cac_2,,
nd a bio.
+ * T aracaracno al14em.
-x 4 size guarantees betwe0x1* acpage  4 * a
+ * bio except that,* aracis some hecklap.
+ * All iovecs	in,* acbio must be  90Sidarad.N ,DMAE80D-/mL80825copy_si_d(V/(2frombio, s,		0x0bio *bio,e81	     0,		0x0dage *dage,6(w,
625,4165625,3{
ER_U1W_PCI_	dC- dage_address(dage);	X	s,		0x0bio_vec *bvl;6811		.i	0x16nx0dage_offlTOOs8-
-* 4 (;bio && bio->bi_sec14e <lsec14e+STRIPE_SECTORS;_-1     0bio =er5_next_bio(bio, sec1or) ) Ne)NM6nx0dage_offlTOOs)NM6f (bio->bi_sec14e >= sec1or)-
-	,dage_offlTO	= (si4ea7)(bio->bi_sec14e - sec1or) * 512Os)NM-	{e -
-	,dage_offlTO	= (si4ea7)(sec14e - bio->bi_sec14e) * -512Os)NMbio_* 4_eac_	{	gm.
-(bvl,cbio, i) Ne)NMM6nx0len	= bio_iovec_0xx(bio,i	->bv_len;e)NMM6nx0clen;e)NMM6nx0b_offlTO	= 0;NMMe-e)N	16f (page_offlTO	< 0) Ne)NMM	b_offlTO	= -dage_offlTOOs)NM	,dage_offlTO	+=0b_offlTOOs)NM	,len	-=0b_offlTOOs)NM	}e-e)N	16f (len > 0 && dage_offlTO	+ len > STRIPE_SIZE	s)NM	,clen	= STRIPE_SIZE - dage_offlTOO	s)NM	-	{e clen	= len;e+M6f (bio->bi_sec14e >= sec1or)-+	,dage_offlTO	= (si4ea7)(bio->bi_sec14e - sec1or) * 512Os+W-	{e	+W	dage_offlTO	= (si4ea7)(sec14e - bio->bi_sec14e) * -512Os+Mbio_* 4_eac_	{	gm.
-(bvl,cbio, i) Ne+MM6nx0len	= bio_iovec_0xx(bio,i	->bv_len;e+MM6nx0clen;e+MM6nx0b_offlTO	= 0;eaea716f (page_offlTO	< 0) Ne+MM	b_offlTO	= -dage_offlTOOs+M	,dage_offlTO	+=0b_offlTOOs+M	,len	-=0b_offlTOOs+	ti_e*4	16f (len > 0 && dage_offlTO	+ len > STRIPE_SIZE	s+M	,clen	= STRIPE_SIZE - dage_offlTOO	+W	-	{e clen	= len;e NMMe-N	16f (clen > 0) Ne)NMM	W_PCI_bdC- __bio_kmap_atomic(bio, i, KM_USER0ER_MW		16f (frombio	s)NM	,	memcpy(pa+dage_offlTO,cba+b_offlTO,cclen)0	)NM	,-	{e	)NM	,	memcpy(ba+b_offlTO,cpa+dage_offlTO,cclen)0	)NM	,__bio_kunmap_atomic(ba, KM_USER0ER_MW		}Me-N	16f (clen < len),	/*hitcend of.dage */e)NMM	break;	-M	,dage_offlTO	+=0 len;e+MM6f (clen > 0) Ne+MM	W_PCI_bdC- __bio_kmap_atomic(bio, i, KM_USER0ER_+		16f (frombio	s+M	,	memcpy(pa+dage_offlTO,cba+b_offlTO,cclen)0	+	W	-	{e	+W			memcpy(ba+b_offlTO,cpa+dage_offlTO,cclen)0	+M	,__bio_kunmap_atomic(ba, KM_USER0ER_U1	}6+	16f (clen < len),	/*hitcend of.dage */e+W		break;	+	,dage_offlTO	+=0 len;e{	XFE}+x	(w,
725},
+722ie22
-	{	M	,dtr[cr1ct++		= dage_address(sh->dev[i].dage);	X	MM	W_osen	= sh->dev[i].toA_1,	;	X	MM	sh->dev[i].toA_1,	 = 0,	0;eaea711	6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	+wake_up(&ER_P->wait_* 4_hecklap);	+	X		1	6f (sh->dev[i].A_1,ten),BUG();	X	MM	sh->dev[i].A_1,ten
-	c_osen;	X	MM	W_2, _xor(	0x2c82737},
+738ie22
-	{	M	6f (i!=pd_0xx && sh->dev[i].toA_1,	) 86231		W_osen	= sh->dev[i].toA_1,	;	X	MM	sh->dev[i].toA_1,	 = 0,	0;eaea711	6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	+wake_up(&ER_P->wait_* 4_hecklap);	+	X		1	6f (sh->dev[i].A_1,ten),BUG();	X	MM	sh->dev[i].A_1,ten
-	c_osen;	X	MMXF(w,
793},
+798},
x0688* 14eaad/toA_1,	 po"Ma0to * acfirst	in,a3	}8in. Nmsx T acbi_next 	}8in must be in hrdar.
msx/utodma	= 80825add_s,	3pe_bio (s,		0x0s,	3pe_head *sh, s,		0x0bio *bi,LV/(2dd_0xx,LV/(2* 4A_1,	)+4nd MWit_nt5add_s,	3pe_bio(s,		0x0s,	3pe_head *sh, s,		0x0bio *bi,LV/(2dd_0xx,LV/(2* 4A_1,	)+62	},s,		0x0bio **bip;681{aid5_ER_P	t *ER_P	= sh->{aid_ER_P	0(w,
810ie22	815,13

-	{	-	{e	U1	bip	= &sh->dev[dd_0xx].toeaad;6811c829 (*bip && (*bip)->bi_sec14e <lbi->bi_sec14e) Ne)NMckmeON((*bip)->bi_sec14e + ((*bip)->bi_size >> 9) >lbi->bi_sec14e);e+MM6f ((*bip)->bi_sec14e + ((*bip)->bi_size >> 9) >lbi->bi_sec14e)s+M	,goto hecklap;	U1	bip	= & (*bip)->bi_next;681}  	/*FIXME do I neA_0to worry about	hecklappi
-	bion */e+W6f (*bip && (*bip)->bi_sec14e <lbi->bi_sec14e + ((bi->bi_size)>>9))s+M	goto hecklap;	+XF	6f (*bip && bi->bi_next && (*bip) !={bi->bi_next)_ 	1BUG();	X	6f (*bip)_14ea828x265836x26ER_U1	(16814ea7	},
-	
-	{	sh->sec14e,2dd_0xx);FER_M6f (* 4A_1,	) Ne)NMUDMA_2,  if.dage is checkra7	*/e+W	UDMA_2,  if.dage is checka7	*/eU1	sec14e_tlsec14e = sh->dev[dd_0xx].sec14e;_X		* 4 (bi=sh->dev[dd_0xx].toA_1,	;	X	M     0ec14e <lsh->dev[dd_0xx].sec14e + STRIPE_SECTORS &&_14ea840},
+848,13

-	{		6f (sec14e >= sh->dev[dd_0xx].sec14e + STRIPE_SECTORS)_ 1	
lTODbUD1R5_OVERWRITE, &sh->dev[dd_0xx].06514e21 	}6+	{	/* 2 1;eaea hecklap:915set_bUD1R5_Oecklap, &sh->dev[dd_0xx].06514e21+MXFER_PIO_4,		0x(&ER_P->42	},
-O_4,ER_+	XFER_PIO_4,(&sh->O_4,ER_+	{	/* 2 0;	68_A+x	(w,
900},
+915}8FER_U1	
XFER_O_4,		0x(&ER_P->42	},
-O_4,ER_X		1{bi	= F%A->toeaad;681	1dev->toeaad = 0,	0;ea11	6f (test_and_clear_bUD1R5_Oecklap, &dev->06514e	s+M	,	wake_up(&ER_P->wait_* 4_hecklap);	},1	XFER_PIO_4,		0x(&ER_P->42	},
-O_4,ER_X		11c829 ({bi	&& rbi->bi_sec14e < F%A->sec14e + STRIPE_SECTORS) 86231		Wopy_si_d(0, rbi, F%A->dage, F%A->sec14e	0x2c82947},
+964,90x148MM	sh->dev[i].toA_1,	 = 0,	0;e{	M	6f (bi) to_A_1,	--;	}	+W		6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	wake_up(&ER_P->wait_* 4_hecklap);	+	X		11c829 (bi	&& bi->bi_sec14e < sh->dev[i].sec14e + STRIPE_SECTORS)86231		s,		0x0bio *nextbi	= r5_next_bio(bi, sh->dev[i].sec14e);	X	MM	Wlear_bUD1BIO_UPTODATE, &bi->bi_06514e212c82975},
+995}8FER_U1	
6f (!test_bUD1R5_Insync, &sh->dev[i].06514e	 86231		bi	= sh->dev[i].toeaad;681	1	sh->dev[i].toeaad = 0,	0;ea11		6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	+wake_up(&ER_P->wait_* 4_hecklap);	X		1	6f (bi) to_eaad--;	}			11c829 (bi	&& bi->bi_sec14e < sh->dev[i].sec14e + STRIPE_SECTORS)86231			s,		0x0bio *nextbi	= r5_next_bio(bi, sh->dev[i].sec14e);	(w,
140{	XF+1424},
x068	6f ( bio_si_d_dir(bi) == WRITE )_ 1	md_A_1,	+	#drt(mdF%A);+8	* 4 (;logical_sec14e < lastasec14e; logical_sec14e += STRIPE_SECTORS) 86a7	DEFINE_WAIT(w);	X			X		new_sec14e = {aid5_ERmpu,	+	ec14e(logical_sec14e,e81	,1	M  {aid_disks
 di_d_disks
 &dd_0xx,L&pd_0xx,LER_P);	(w,
1410ie7h+1433,28FER_U1	
(16814ea7	},
-	
-	{	new_sec14e, _U1	
(16814ea7	},
-	
-	{	logical_sec14e);	}	+W{	/ry:	+	,drepare_to_wait(&ER_P->wait_* 4_hecklap,L&w, TASK_UNINTERRUPTIBLE);	X		sh = gTO_acthpt_s,	3pe(ER_P, new_sec14e, pd_0xx,L(bi->bi_rw&RWA_MASK))Os81	6f (sh) Ne)	-M	,add_s,	3pe_bio(sh,cbi,2dd_0xx,L(bi->bi_rw&RW_MASK))Os-	+W		6f (!add_s,	3pe_bio(sh,cbi,2dd_0xx,L(bi->bi_rw&RW_MASK))) Nea7	
+	/*Add faiMA_0due to hecklap.  Flush x0xrythi
-ea7	
+ * and wait,a31c829ea7	
+ */e+W			raid5_unplug_	ic inemdF%A->queue)0	+M	,W{	least_s,	3pe(sh)0	+M	,Wschedule()0	+M	,Wgoto {	/ry0	+M	,}6+	1	PInish_wait(&ER_P->wait_* 4_hecklap,L&wER_X		1{aid5_plug_	ic ineER_P);	X		1handlt_s,	3pe(sh)0	 	,W{	least_s,	3pe(sh)0	+_U1	} -	{e 86231	/* AannotlgTO s,	3pe * 4 eaad-ahead,Xjust ghpt-up	*/eU1		Wlear_bUD1BIO_UPTODATE, &bi->bi_06514e21+	1	PInish_wait(&ER_P->wait_* 4_hecklap,L&wER_X		1break;	X		+	},1		(w,
1568	XF+1602},
x068XF	XFER_O_4,		nit(&ER_P->42	},
-O_4,ER_X	R_UDMwaitqueue	head1&ER_P->wait_* 4_s,	3pe		0x16_UDMwaitqueue	head1&ER_P->wait_* 4_hecklap);	X	INIT_LIST_HEAD1&ER_P->handlt_	TOD);	X	INIT_LIST_HEAD1&ER_P->delayed_	TOD);	X	INIT_LIST_HEAD1&ER_P->inacthpt_	TOD);		0x06814esctive tim.md/raid6m8in.Ee 2or 9s	{	md/raid6m8in.E= ht_h"TA6S};semd/raid6m8in.E0d0anDD1-30 22:33:46hp		.e		evice_t hpt366md/raid6m8in.E0d0anDD0d08 02:35:58ini	si_d(w,
54},
-54},
x0688* This macro is usA_0to deDMAmMA_1* ac'next'0bio in,* ac	TOD, ghptn,* acsec14e688* of * ac4urs.
-xs,	3pe+42	},
N ,DMA-0_},
-	er5_next_bio(bio, sec1) (4( bio->bi_sec14e + (bio->bi_size>>9)	<esec1 + STRIPE_SECTORS)E? bio->bi_next : 0,	0-	{0_},
-	er5_next_bio(bio, sec1) (4( (bio	->bi_sec14e + ((bio	->bi_size>>9)	<esec1 + STRIPE_SECTORS)E? (bio	->bi_next : 0,	0-	U/)Nmsx T acfollow366,Aan be usA_0to debug * act hpt3N ,DMA(w,
670,4165670,3{
ER_U1W_PCI_	dC- dage_address(dage);	X	s,		0x0bio_vec *bvl;6811		.i	0x16nx0dage_offlTOOs8-
-* 4 (;bio && bio->bi_sec14e <lsec14e+STRIPE_SECTORS;_-1     0bio =er5_next_bio(bio, sec1or) ) Ne)NM6nx0dage_offlTOOs)NM6f (bio->bi_sec14e >= sec1or)-
-	,dage_offlTO	= (si4ea7)(bio->bi_sec14e - sec1or) * 512Os)NM-	{e-
-	,dage_offlTO	= (si4ea7)(sec14e - bio->bi_sec14e) * -512Os)NMbio_* 4_eac_	{	gm.
-(bvl,cbio, i) Ne)NMM6nx0len	= bio_iovec_0xx(bio,i	->bv_len;e)NMM6nx0clen;e)NMM6nx0b_offlTO	= 0;e-e)N	16f (page_offlTO	< 0) Ne)NMM	b_offlTO	= -dage_offlTOOs)NM	,dage_offlTO	+=0b_offlTOOs)NM	,len	-=0b_offlTOOs)NM	}e-e)N	16f (len > 0 && dage_offlTO	+ len > STRIPE_SIZE	s)NM	,clen	= STRIPE_SIZE - dage_offlTOOs)NM	-	{e clen	= len;e-e-N	16f (clen > 0) Ne)NMM	W_PCI_bdC- __bio_kmap_atomic(bio, i, KM_USER0ER_MW		16f (frombio	s)NM	,	memcpy(pa+dage_offlTO,cba+b_offlTO,cclen)0	)NM	,-	{e	)NM	,	memcpy(ba+b_offlTO,cpa+dage_offlTO,cclen)0	)NM	,__bio_kunmap_atomic(ba, KM_USER0ER_MW		}e-N	16f (clen < len),	/*hitcend of.dage */e)NMM	break;	-M	,dage_offlTO	+=0 len;e+M6f (bio->bi_sec14e >= sec1or)-+	,dage_offlTO	= (si4ea7)(bio->bi_sec14e - sec1or) * 512Os+W-	{e	+W	dage_offlTO	= (si4ea7)(sec14e - bio->bi_sec14e) * -512Os+Mbio_* 4_eac_	{	gm.
-(bvl,cbio, i) Ne+MM6nx0len	= bio_iovec_0xx(bio,i	->bv_len;e+MM6nx0clen;e+MM6nx0b_offlTO	= 0;eaea716f (page_offlTO	< 0) Ne+MM	b_offlTO	= -dage_offlTOOs+M	,dage_offlTO	+=0b_offlTOOs+M	,len	-=0b_offlTOOs+	ti_e*4	16f (len > 0 && dage_offlTO	+ len > STRIPE_SIZE	s+M	,clen	= STRIPE_SIZE - dage_offlTOO	+W	-	{e clen	= len;e+e+MM6f (clen > 0) Ne+MM	W_PCI_bdC- __bio_kmap_atomic(bio, i, KM_USER0ER_+		16f (frombio	s+M	,	memcpy(pa+dage_offlTO,cba+b_offlTO,cclen)0	+	W	-	{e	+W			memcpy(ba+b_offlTO,cpa+dage_offlTO,cclen)0	+M	,__bio_kunmap_atomic(ba, KM_USER0ER_U1	}6+	16f (clen < len),	/*hitcend of.dage */e+W		break;	+	,dage_offlTO	+=0 len;e{	XFE}+x	(w,
738},
+735ie22
-	{	M	6f ( i !={pd_0xx && i !={qd_0xx && sh->dev[i].toA_1,	 ) 86231		W_osen	= sh->dev[i].toA_1,	;	X	MM	sh->dev[i].toA_1,	 = 0,	0;eaea711	6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	+wake_up(&ER_P->wait_* 4_hecklap);	+	X		1	6f (sh->dev[i].A_1,ten),BUG();	X	MM	sh->dev[i].A_1,ten
-	c_osen;	X	MMXF(w,
900}265901},
x0688* 14eaad/toA_1,	 po"Ma0to * acfirst	in,a3	}8in.Nmsx T acbi_next 	}8in must be in hrdar.
msx/utodma	= 80825add_s,	3pe_bio (s,		0x0s,	3pe_head *sh, s,		0x0bio *bi,LV/(2dd_0xx,LV/(2* 4A_1,	)+4nd MWit_nt5add_s,	3pe_bio(s,		0x0s,	3pe_head *sh, s,		0x0bio *bi,LV/(2dd_0xx,LV/(2* 4A_1,	)+62	},s,		0x0bio **bip;681{aid6_ER_P	t *ER_P	= sh->{aid_ER_P	0(w,
91 ie22	918,13

-	{	-	{e	U1	bip	= &sh->dev[dd_0xx].toeaad;6811c829 (*bip && (*bip)->bi_sec14e <lbi->bi_sec14e) Ne)NMckmeON((*bip)->bi_sec14e + ((*bip)->bi_size >> 9) >lbi->bi_sec14e);e-1	bip	= & (*bip)->bi_next;6+MM6f ((*bip)->bi_sec14e + ((*bip)->bi_size >> 9) >lbi->bi_sec14e)s+M	,goto hecklap;	+1	bip	= &(*bip)->bi_next;681}  	/*FIXME do I neA_0to worry about	hecklappi
-	bion */e+W6f (*bip && (*bip)->bi_sec14e <lbi->bi_sec14e + ((bi->bi_size)>>9))s+M	goto hecklap;	+XF	6f (*bip && bi->bi_next && (*bip) !={bi->bi_next)_ 	1BUG();	X	6f (*bip)_14ea935x265939x26ER_U1	(16814ea7	},
-	
-	{	sh->sec14e,2dd_0xx);FER_M6f (* 4A_1,	) Ne)NMUDMA_2,  if.dage is checkra7	*/e+W	UDMA_2,  if.dage is checka7	*/eU1	sec14e_tlsec14e = sh->dev[dd_0xx].sec14e;_X		* 4 (bi=sh->dev[dd_0xx].toA_1,	;	X	M     0ec14e <lsh->dev[dd_0xx].sec14e + STRIPE_SECTORS &&_14ea947},
+951,13

-	{		6f (sec14e >= sh->dev[dd_0xx].sec14e + STRIPE_SECTORS)_ 1	
lTODbUD1R5_OVERWRITE, &sh->dev[dd_0xx].06514e21 	}6+	{	/* 2 1;eaea hecklap:915set_bUD1R5_Oecklap, &sh->dev[dd_0xx].06514e21+MXFER_PIO_4,		0x(&ER_P->42	},
-O_4,ER_+	XFER_PIO_4,(&sh->O_4,ER_+	{	/* 2 0;	68_A+x	(w,
1010},
+1021}8FER_U1	
XFER_O_4,		0x(&ER_P->42	},
-O_4,ER_X		1{bi	= F%A->toeaad;681	1dev->toeaad = 0,	0;ea11	6f (test_and_clear_bUD1R5_Oecklap, &dev->06514e	s+M	,	wake_up(&ER_P->wait_* 4_hecklap);	},1	XFER_PIO_4,		0x(&ER_P->42	},
-O_4,ER_X		11c829 ({bi	&& rbi->bi_sec14e < F%A->sec14e + STRIPE_SECTORS) 86231		Wopy_si_d(0, rbi, F%A->dage, F%A->sec14e	0x2c821059},
+1072,90x148MM	sh->dev[i].toA_1,	 = 0,	0;e{	M	6f (bi) to_A_1,	--;	}	+W		6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	wake_up(&ER_P->wait_* 4_hecklap);	+	X		11c829 (bi	&& bi->bi_sec14e < sh->dev[i].sec14e + STRIPE_SECTORS)86231		s,		0x0bio *nextbi	= r5_next_bio(bi, sh->dev[i].sec14e);	X	MM	Wlear_bUD1BIO_UPTODATE, &bi->bi_06514e212c821087},
+1103}8FER_U1	
6f (!test_bUD1R5_Insync, &sh->dev[i].06514e	 86231		bi	= sh->dev[i].toeaad;681	1	sh->dev[i].toeaad = 0,	0;ea11		6f (test_and_clear_bUD1R5_Oecklap, &sh->dev[i].06514e	s+M	,	+wake_up(&ER_P->wait_* 4_hecklap);	X		1	6f (bi) to_eaad--;	}			11c829 (bi	&& bi->bi_sec14e < sh->dev[i].sec14e + STRIPE_SECTORS)86231			s,		0x0bio *nextbi	= r5_next_bio(bi, sh->dev[i].sec14e);	(w,
1566},
+1584},
x068	6f ( bio_si_d_dir(bi) == WRITE )_ 1	md_A_1,	+	#drt(mdF%A);+8	* 4 (;logical_sec14e < lastasec14e; logical_sec14e += STRIPE_SECTORS) 86a7	DEFINE_WAIT(w);	X	X		new_sec14e = {aid6_ERmpu,	+	ec14e(logical_sec14e,e81	,1	M  {aid_disks
 di_d_disks
 &dd_0xx,L&pd_0xx,LER_P);	(w,
1574ie7h+1593,226ER_U1	8888888(16814ea7	},
-	
-	{	new_sec14e,_U1	8888888(16814ea7	},
-	
-	{	logical_sec14e);	}	+W{	/ry:	+	,drepare_to_wait(&ER_P->wait_* 4_hecklap,L&w, TASK_UNINTERRUPTIBLE);	X		sh = gTO_acthpt_s,	3pe(ER_P, new_sec14e, pd_0xx,L(bi->bi_rw&RWA_MASK))Os81	6f (sh) Ne)	-M	,add_s,	3pe_bio(sh,cbi,2dd_0xx,L(bi->bi_rw&RW_MASK))Os-	+W		6f (!add_s,	3pe_bio(sh,cbi,2dd_0xx,L(bi->bi_rw&RW_MASK))) Nea7	
+	/*Add faiMA_0due to hecklap.  Flush x0xrythi
-ea7	
+ * and wait,a31c829ea7	
+ */e+W			raid6_unplug_	ic inemdF%A->queue)0	+M	,W{	least_s,	3pe(sh)0	+M	,Wschedule()0	+M	,Wgoto {	/ry0	+M	,}6+	1	PInish_wait(&ER_P->wait_* 4_hecklap,L&wER_X		1{aid6_plug_	ic ineER_P);	X		1handlt_s,	3pe(sh)0	 	,W{	least_s,	3pe(sh)0	U1	} -	{e 86231	/* AannotlgTO s,	3pe * 4 eaad-ahead,Xjust ghpt-up	*/eU1		Wlear_bUD1BIO_UPTODATE, &bi->bi_06514e21+	1	PInish_wait(&ER_P->wait_* 4_hecklap,L&wER_X		1break;	X		+	}	(w,
173{	XF+1761},
x068XF	XFER_O_4,		nit(&ER_P->42	},
-O_4,ER_X	R_UDMwaitqueue	head1&ER_P->wait_* 4_s,	3pe		0x16_UDMwaitqueue	head1&ER_P->wait_* 4_hecklap);	X	INIT_LIST_HEAD1&ER_P->handlt_	TOD);	X	INIT_LIST_HEAD1&ER_P->delayed_	TOD);	X	INIT_LIST_HEAD1&ER_P->inacthpt_	TOD);		0x06814esctive tim.media/video/KER_PIOce_t hpt366media/video/KER_PIO= ht_h"TA6S};semedia/video/KER_PIO0d0anDD1-,5/*33t0s27hp		.e		evice_t hpt366media/video/KER_PIO0d0anDD2-03 06342:40hp		.e		(w,
146x265146x8
x068XFER_PIOcVIDEO_VINO	X	,	3FER_= "SGI Vino Video F 4 L___A (EXPERIMENTAL)"	-Mdepends,on EXPERIMENTAL	&& VIDEO_DEV	&& SGI0x1depends,on VIDEO_DEV	&& I2C	&& SGI_IP22 && EXPERIMENTAL915selec1 I2C_ALGO_SGI0 	help_U1  Say Y  aracto buil,
-	lsupport * 4 * acVino video __put system0Sr1c82U1  on SGI Indy maint-	s.		0x06814esctive tim.media/video/tda9887.Ee 2or 9s	{	media/video/tda9887.E= ht_h"TA6S};semedia/video/tda9887.E0d0anDD1-,5/*33t0s26hp		.e		evice_t hpt366media/video/tda9887.E0d0anDD2-04 07:5 0R7ini	.e		(w,
305,90+305,90ER_U1pr"Mak("  B5888* 4ce mu,	 audio: %s\n",6818888888(buf[1] &{	X20)E? "yes" : "no");	X	pr"Mak("  B6888output port 1888: %s\n",6-18888888(buf[1] &{	X40)E? "high" : "low"		0x18888888(buf[1] &{	X40)E? "high (inacthpt)" : "low (acthpt)");	X	pr"Mak("  B7888output port 2888: %s\n",6-18888888(buf[1] &{	X80)E? "high" : "low"		0x18888888(buf[1] &{	X80)E? "high (inacthpt)" : "low (acthpt)");	X	X	pr"Mak(PREFIX "A_1,	: bytelC 0x%02x\n",buf[2]);	X	pr"Mak("  C0-4ctop adjustm.
-x8: %s dB\n", adjust[buf[2] &{	X1f]);	(w,
545,19
-545,24,ER_U1R_t rc;	X	X	memset(bux,0,sizeof(bux)ER_+	tda9887	{	XDtvnorm(t,buf)	0 1buf[1] |= cOutputPort1Inacthpt	0 1buf[1] |= cOutputPort2Inacthpt	0-	tda9887	{	XDtvnorm(t,buf)	0 16f (UNSET !={t->pinnaclt_id) NeU1	tda9887	{	XDpinnaclt(t,buf)	0 1+	},tda9887	{	XDER_PIO(t,buf)	0 1tda9887	{	XDinsmod(t,buf)	0 _0,e, 		e68exT is as-is breaks some cards, must be fixA,
-	 a0x18*	card-specific way, probably usi
-	TDA9887	SET_		.inicto0x188* /* 2 on/ox06port2 */R_M6f (t->std &{V4L2_STD_SECAM_L) NeU1	8exsecam fixup	(FIXME: mhec.this #o tvnorms array?)	*/eU1	buf[1] &= ~cOutputPort2Inacthpt	0 	}6+dc62	}	X	X	dpr"Mak(PREFIX "A_1,i
-: b=0x%02x c=0x%02x e=0x%02x\n",eU1	buf[1],buf[2],buf[3]);		0x06814esctive tim.media/video/vino.Ee 2or 9s	{	media/video/vino.E= ht_h"TA6S};semedia/video/vino.E0d0a2aa1-29 i	.30:41hp		.e		evice_t hpt366media/video/vino.E0d0anDD2-03 06342:40hp		.e		(w,
1,262651,34,
x06 	/*$Id: vino.E,v 1.5/*999/10/09 i0001:14 {alf Exp $N- * t hpt366W_PC/vino.E=+/*
+ * (incomplete) D hpt3 * 4 * acVINO (Video In No Out) system0Sr1c8
-	 SGI Indys.
msxN- * (incomplete) D hpt3 * 4 * acVino Video __put system0Sr1c8
-	 SGI Indys.
+8* This f829 is subjec1 to * acDMAms and ER_ditions of * acGNU Genxral Public
+8* L},
n{e pt36ion 2 as published by * acFree SoftwaracFr1c8ation.
msxN- * Copyright (C)/*999 Ulf Carlsson (ulfc@bun.falkenberg.se)+-sxN- * This isn'x0complete yTO, pleast don'x0expec1 any video until I'ec.A_1,ten
- * some more code.
+ * Copyright (C)/d0a3 Ladislav Michl <ladis@6___A-mips.org>N ,DMAE
 3MWit_h"TA6___ALmoduleA			 3MWit_h"TA6___AL6_UDA			 3MWit_h"TA6___ALA_4,sA			 3MWit_h"TA6___ALmmA			+3MWit_h"TA6___ALslabA			+3MWit_h"TA6___ALwrapperA			 3MWit_h"TA6___ALerrno.			+3MWit_h"TA6___ALirq.			+3MWit_h"TA6___ALdelayA			 3MWit_h"TA6___ALvideo_evF			+3MWit_h"TA6___ALi2cF			+3MWit_h"TA6___ALi2c-algo-sg chtwE
 3MWit_h"TAasm/addrspaceA			 3MWit_h"TAasm/systemF			+3MWit_h"TAasm/	XFEinfoF			+3MWit_h"TAasm/pgAa_MW.			+3MWit_h"TAasm/paccess.			+3MWit_h"TAasm/ioF			+3MWit_h"TAasm/sg /ip22F			+3MWit_h"TAasm/sg /hpc3F			+3MWit_h"TAasm/sg /mcchtwE
 3MWit_h"T"vino.h"0 _0/* debuggi
-? */e+,e, 1	{0_},
-	eheckm(x...)88888pr"Mak(x);F+dc	{e	+0_},
-	eheckm(x...)6+dc62	}	+	+	+/* VINO ASIC rAUTODMAs */	+s,		0x0sgi_vino *vino;eaea+#define F_LOW_PCI_vinos,	 = "VINO IndyCam/TV";+4nd MWit_nt5threshold_dC- 512Os+nd MWit_nt5threshold_bC- 512Os+68s,		0x0vino_	ic in62	},s,		0x0video_	ic in6vF%A;	+0_},
-	eVINO_CHAN_A		1	+0_},
-	eVINO_CHAN_B		20x16nx04	},;	+}Os8-
-16814ea7	},
-	4	},;	-0_},
-	eVINO_CHAN_A		0	-0_},
-	eVINO_CHAN_B		1	--
-16814ea7	},
-				0x14-0_},
-	eVINO_DMA_ACTIVE		(1<<0)	+s,		0x0vino_cli.
-xNea7s,		0x0i2c_cli.
-x*t hpt3	0x16nx0ownt3	0 }Os8-
/* We,Aan actually   ce6S} TV and IndyCam __put at,* acs_LO time. Belix0x i-x 4
- * 	{	..
- */utodma	= s,		0x0vino_	ic in6vino[2];	+s,		0x0vino_video Nea7s,		0x0vino_	ic in6chA;ea7s,		0x0vino_	ic in6chB;eaea7s,		0x0vino_cli.
-xdecoder;ea7s,		0x0vino_cli.
-xcamxra;eaea7s,		0x0semaphore __put-O_4,;eaea7/* LoadA,
-		o VINO descrip14es to clear End Of Descrip14es ta_MW0x18*	inDMAupt ER_dition */e+W82ea	},
-
-	{ dummy_dage	0x1AUTODMA,
-		.dummy_buf[4	E0(attribu,	+_((al14eed(8))ER_+}Os8-
/* T_ose rAUTODMAs havacto b	 accessed by eithMA,*one* 640bit A_1,	  4 *one* 64
- * bit eaad. We,neA_0some asmcto fix.this. We,Aan'x0usacmips3 as odmc8ard
- * becausacweXjust savac320bitl at,4ontext switch.
- */u+odma	= s,		0x0vino_video *Vino;etatic ineF__V/lMA___ 16814ea7	},
-	
-	{0vino_rAU_eaad(16814ea7	},
-	addr)	+AUTODMA,
-2c_vino_getctrl(80825*di_d)+62	
-16814ea7	},
-	
-	{ retE0(attribu,	+_ ((al14eed (64))ER_MW16814ea7	},
-	virt_addrC- KSEG1ADDR(addrC+eVINO_BASEER_MW16814ea7	},
-				0x14-	-	sava_and_cli(06514e21-	0(asm+_ __vol inl	+_(	-M	".set\tmips3\n\t"	-M	".set\tnoat\n\t"	-M	"ld\t$1,(%0)\n\t"	-M	"sd\t$1,(%1)\n\t"	-M	".set\tat\n\t"	-M	".set\tmips0"	-M	:_U1	:"r" (virt_addr)
-
-	8"r" (&ret)_U1	:"$1")	0pt36814ea_06514(06514e21-hpt366_chirTOO	+W366_chivino->i2c_control);
-static ineF__V/lMA___ 80825vino_rAU_A_1,	(16814ea7	},
-	
-	{0value
-
-	,188888816814ea7	},
-	addr)	+80825-2c_vino_setctrl(80825*di_d8082ea	},
-val)+62	
-16814ea7	},
-	virt_addrC- KSEG1ADDR(addrC+eVINO_BASEER_MW16814ea7	},
-				0x14+	vino->i2c_controlC- valR_+}s8-
-/* wacmight lose * acupper parts of * acrAUTODMAs 1c8c_0aracnot savad_U18*	if * are comes an	inDMAAupt in hur way, play safe */e+AUTODMA,
-2c_vino_rsi_d(80825*di_d)++{	+W366_chivino->i2c_di_dR_+}s8-
-sava_and_cli(06514e21-	0(asm+_ __vol inl	+_(	-M	".set\tmips3\n\t"	-M	".set\tnoat\n\t"	-M	"ld\t$1,(%0)\n\t"	-M	"sd\t$1,(%1)\n\t"	-M	".set\tat\n\t"	-M	".set\tmips0"	-M	:_U1	:"r" (&value)
-
-	8"r" (virt_addr)_U1	:"$1")	0pt36814ea_06514(06514e21-}e-e)ic ineF__V/lMA___ 80825vino_rAU_and(16814ea7	},
-	
-	{0value
-
-	,1888816814ea7	},
-	addr)	-{_MW16814ea7	},
-	virt_addrC- KSEG1ADDR(addrC+eVINO_BASEER_MW16814ea7	},
-				0x14-	-	sava_and_cli(06514e21-	0(asm+_ __vol inl	+_(	-M	".set\tmips3\n\t"	-M	".set\tnoat\n\t"	-M	"ld\t$1,(%0)\n\t"	-M	"ld\t$2,(%1)\n\t"	-M	"and\t$1,$1,$2\n\t"	-M	"sd\t$1,(%0)\n\t"	-M	".set\tat\n\t"	-M	".set\tmips0"	-M	:_U1	:"r" (virt_addr)
-
-	8"r" (&value)_U1	:"$1","$2")	0pt36814ea_06514(06514e21-}e-e)ic ineF__V/lMA___ 80825vino_rAU_4e(16814ea7	},
-	
-	{0value
-
-	,188816814ea7	},
-	addr)	-{_MW16814ea7	},
-	virt_addrC- KSEG1ADDR(addrC+eVINO_BASEER_MW16814ea7	},
-				0x14-	-	sava_and_cli(06514e21-	0(asm+_ __vol inl	+_(	-M	".set\tmips3\n\t"	-M	".set\tnoat\n\t"	-M	"ld\t$1,(%0)\n\t"	-M	"ld\t$2,(%1)\n\t"	-M	"or\t$1,$1,$2\n\t"	-M	"sd\t$1,(%0)\n\t"	-M	".set\tat\n\t"	-M	".set\tmips0"	-M	:_U1	:"r" (virt_addr)
-
-	8"r" (&value)_U1	:"$1","$2")	0pt36814ea_06514(06514e21+80825-2c_vino_wsi_d(80825*di_d8082ea	},
-val)++{	+Wvino->i2c_di_dC- valR_
-static ineFinx0vino_	ma_setup(8082)u+odma	= s,		0x0i2c_algo_sgi_di_dCi2c_sgi_vino_di_dC-+62	
-{	/* 2 0;	+	.getctrl	= &-2c_vino_getctrl,ea7.setctrl	= &-2c_vino_setctrl,ea7.rsi_d888= &-2c_vino_rsi_d,ea7.wsi_d888= &-2c_vino_wsi_d,ea7.xfer_timeout	=/d0a,ea7.ack_timeout		=/100a,ea};	+	+/*
+ * T aracaractwo possi_MW cli.
-s,on VINO I2C bus,0so waclimix0usage  nly
+ * to * am.
+ */s+nd MWit_nt5-2c_vino_cli.
-_rAU(s,		0x0i2c_cli.
-x*cli.
-)++{	+W1		.  s	= 0;eaea7down(&Vino->i_put-O_4,ER_+	Xwitch (cli.
-->t hpt3->id) Nea7case I2C_DRIVERID_SAA7191:6+MM6f (Vino->decoder.t hpt3	s+M	,  s	= -eckSY;	+W	-	{e	+W		Vino->decoder.t hpt3
-	cli.
-;	+1	break;	+	case I2C_DRIVERID_INDYCAM:6+MM6f (Vino->camxra.t hpt3	s+M	,  s	= -eckSY;	+W	-	{e	+W		Vino->camxra.t hpt3
-	cli.
-;	+1	break;	+	_},ault:	{	1{	s	= -eNOup	;	+,}6+	up(&Vino->i_put-O_4,ER_+	+W366_chiresx1A-static ineF80825vino_	ma_stop(8082)u+odma	= _nt5-2c_vino_cli.
-_unrAU(s,		0x0i2c_cli.
-x*cli.
-)+ {	+W1		.  s	= 0;eaea7down(&Vino->i_put-O_4,ER_+	6f (cli.
-x== Vino->decoder.t hpt3	 Ne+MM6f (Vino->decoder.ownt3	s+M	,  s	= -eckSY;	+W	-	{e	+W		Vino->decoder.t hpt3
-	0,	0;ea1} -	{e 6f (cli.
-x== Vino->camxra.t hpt3	 Ne+MM6f (Vino->camxra.ownt3	s+M	,  s	= -eckSY;	+W	-	{e	+W		Vino->camxra.t hpt3
-	0,	0;ea1}6+	up(&Vino->i_put-O_4,ER_ 	+W366_chiresx1A-static ineFinx0vino_	nit(8082)u+odma	= s,		0x0i2c_adapDMA0vino_	2c_adapDMA0=+62	
-16814ea7	},
-	rTOOs)N16814ea7	short r%A	 id;	
-16814ea7	},
-	
-	{ foo;	
-16814ea7	},
-	*bar14-	-	bar	= (16814ea7	},
-	*) &foo;	
	
-{	/C- vino_rAU_eaad(VINO_REVIDe21-hpt36}	= ({	/C& VINO_REVID_REV_MASK)x1-+6d	= ({	/C& VINO_REVID_ID_MASK) >> 421-hptpr"Mak("Vino: ID:%02hx Rev:%02hx\n", id,l  ve21-hptfooC- vino_rAU_eaad(VINO_A_DESC_DATA0ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_A_DESC_DATA1ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_A_DESC_DATA2ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_A_DESC_DATA3ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx\n", bar[1]ER_MWfooC- vino_rAU_eaad(VINO_B_DESC_DATA0ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_B_DESC_DATA1ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_B_DESC_DATA2ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx ",cbar[1]ER_MWfooC- vino_rAU_eaad(VINO_B_DESC_DATA3ER_MWpr"Mak("0x%lx",cbar[0]ER_MWpr"Mak("%lx\n", bar[1]ER_a7.F_LOW		= "VINO I2C bus",ea7.idW		= I2C_HW_SGI_VINO,ea7.algo_si_d		= &i2c_sgi_vino_di_d,ea7.cli.
-_rAUTODMA	= &-2c_vino_cli.
-_rAU,ea7.cli.
-_unrAUTODMA	= &-2c_vino_cli.
-_unrAU,	+}Os8-
-{	/* 2 0;	+ic ineFinx0vino_	2c_add_bus(8082)u+{	+W366_chii2c_sgi_add_bus(&vino_	2c_adapDMA)x1A-static ineF80825vino_	ma_go(s,		0x0vino_	ic in6*v)	+ic ineFinx0vino_	2c_del_bus(8082)u62	
-	+W366_chii2c_sgi_del_bus(&vino_	2c_adapDMA)x1A-stat/* RelTO	* acvino back0to de,aultXFER_= DMAtatic ineF80825vino_setup(s,		0x0vino_	ic in6*v)	+ic ineF80825vino_inDMAAupt(V/(2irq, 80825*dev_id,l0,		0x0d-_rAUs *rAUs)u62	
-	{}9 aE80D-/mLinx0vino_open(s,		0x0video_	ic in6*F%A	 V/(2*6514e
 Nea7s,		0x0vino_	ic in6*videv	= (s,		0x0vino_	ic in6*)F%A;	+623{	/* 2 0;	68_A+xic ineF80825vino_close(s,		0x0video_	ic in6*F%Ae
 Nea7s,		0x0vino_	ic in6*videv	= (s,		0x0vino_	ic in6*)F%A;	A-static ineFinx0vino_	octl(s,		0x0video_	ic in6*F%A	 AUTODMA,
-		.cmd, 80825*arg)	+ic ineFinx0vino_mmap(s,		0x0video_	ic in6*F%A	 e F_LOW_PCI_adr,ea7	888 082ea	},
-
-	{ size[+62	
-{	/* 2 0;	+	s,		0x0vino_	ic in6*videv	= (s,		0x0vino_	ic in6*)F%A;	+6+	{	/* 2 -EINVAL;68-static ineFinx0vino_mmap(s,		0x0video_	ic in6*F%A	 e F_LOW_PCI_adr,e-7	888 082ea	},
-
-	{ size[++ic ineFinx0vino_	octl(s,		0x0video_	ic in6*F%A	 AUTODMA,
-		.cmd, 80825*arg)	62	
-{	/* 2 0;	+	s,		0x0vino_	ic in6*videv	= (s,		0x0vino_	ic in6*)F%A;	+6+	{	/* 2 -EINVAL;68-static ineFs,		0x0video_	ic in6vino_	ic	= {ea+#define F_LOs,		0x0video_	ic in6vino_	ic in6=62	},.ownt3		= THIS_MODULE,e-7.F_LOW	= "Vino IndyCam/TV",e-7.A_4,W	= VID_TYPE_CAPTURE,ea7.A_4,W	= VID_TYPE_CAPTURE | VID_TYPE_SUBCAPTURE,e},._PCdwara	= VID_HARDWARE_VINO,ea7.F_LOW	= "VINO",eU1.openW	= vino_open,eU1.closeW	= vino_close,eU1.	octlW	= vino_	octl,eU1.mmapW	= vino_mmap,0 }Os8-
-		.a_	nit 6_UDMvino(s,		0x0video_	ic in6*F%Ae
+ic ineFinx0a_	nit vino_	nit(8082)u62	
-inx0MAA;e+W82ea	},
-
-	{ r%A;	+11		.i, ret = 0;FER-+MAAC- vino_	nit()x1-+6f (MAA)_U1	{	/* 2 MAA;e+W/* VINO is Indy specific beast */e+W6f (ip22_is_fullhouse()-	{	1{	/* 2 -ENOup	;	ER-,e, 		-+6f (video_rAUTODMAe	ic ine&vinoF%A	 VFL_TYPE_GRABBER) == -1	 Ne+M/*
+18*	VINO is in,* acEISA address space,0so * acsysidcrAUTODMA will tell
+18*	us	if * acEISA_PRESENT pin hn MC has been pull,
-
-w.
+18*
+18*	IfcEISA_PRESENT is not set we _},
-itely don'x0havaca	VINO equiped
+18*	systemF
+18*/e+W6f (!(sgimc->systemid &{SGIMC_SYSID_EPRESENT)) Nea7	pr"Mak(KERN	ERR "VINO not Sr1c8\n"ER_X		{	/* 2 -ENOup	;	E1}  dc62	}	X	
-{	/* 2 0;	p {
Wvino	= (s,		0x0sgi_vino *)ioremap(VINO_BASE80sizeof(s,		0x0sgi_vino)ER_+	6f (!vino)	{	1{	/* 2 -EIO;eaea7/* Okay, oncacweXknow that,VINO is pres.
-xwe'll eaad itl r%Ai6ion
+18*	safe way. One,nept3
knows...8*/e+W6f (gTO_dbnereA	 &(vino->rev_id))) Nea7	pr"Mak(KERN	ERR "VINO: faiMA_0to {	ad r%Ai6ioncrAUTODMA\n"ER_{	1{	/	= -eNOup	;	+,	goto hu-_unmap;	+1}e+W6f (VINO_ID_VALUEereA) !={VINO_CHIP_ID) Nea7	pr"Mak(KERN	ERR "VINO is not VINO (Rev/ID: 0x%04lx)\n",   ve21{	1{	/	= -eNOup	;	+,	goto hu-_unmap;	+1}e+Wpr"Mak(KERN	{	XF "VINO Rev: 0x%02lx\n", VINO_REV_NUMereA));	ER-,e,_}, MODULE-
-		.6_UDMmodule(8082)u-2	
-inx0MAA;e+WVino	= (s,		0x0vino_video *)	{	1kmal			(sizeof(s,		0x0vino_video), GFP_KERNELER_+	6f (!Vino) Nea7	{	/	= -eNOMEM;	+,	goto hu-_unmap;	+1}e+e+WVino->dummy_dage = gTO_zeroed_dage(GFP_KERNEL | GFP_DMAER_+	6f (!Vino->dummy_dage) Nea7	{	/	= -eNOMEM;	+,	goto hu-_fr	=_vino;ea1}e+W* 4 (i = 0; i < 4; i+1)_+	WVino->dummy_buf[i		= PHYSADDR(Vino->dummy_dage);eaea7vino->controlC- 0;e+W/* pre0xct VINO from throw366,spurious	inDMAAupts */	+7vino->a.next_4_desc	= PHYSADDR(Vino->dummy_buf)	0+7vino->b.next_4_desc	= PHYSADDR(Vino->dummy_buf)	0+7udelay(5)	0+7vino->inD4_s,atus	= 0;ea8888888 8exset5threshold le0xl */	+8888888 vino->a.fifo_thres	= threshold_d	0+7vino->b.fifo_thres	= threshold_b;eaea76_UDMMUTEX(&Vino->i_put-O_4,ER_+	+W6f (request_	0x(SGI_VINO_IRQ,5vino_inDMAAupt, 0,5vinos,	, 0,	0-) Nea7	pr"Mak(KERN	ERR "VINO: 	0x%02dcrAUTODration faiMA_\n",e+1	8888888SGI_VINO_IRQe21{	1{	/	= -eAGAIN;	+,	goto hu-_fr	=_dage	0x1}FER-+MAAC- vino_	nit()x1-+6f (MAA)_U1	{	/* 2 MAA;e+W{	/C- vino_	2c_add_bus(ER_+	6f (ret) Nea7	pr"Mak(KERN	ERR "VINO: I2C buscrAUTODration faiMA_\n");	+,	goto hu-_fr	=_	0x;	+1}e+e+W6f (video_rAUTODMAe	ic ine&Vino->chA.vF%A	 VFL_TYPE_GRABBER, -1	 < 0) Ne+MMpr"Mak("%s	 ehnl %d: 	ic in6rAUTODration faiMA_.\n",e+1		Vino->chA.vF%A.F_LO,iVino->chA.4	},e21{	1{	/	= -eINVAL;6+,	goto hu-_	2c_del_bus;	+1}e+W6f (video_rAUTODMAe	ic ine&Vino->chB.vF%A	 VFL_TYPE_GRABBER, -1	 < 0) Ne+MMpr"Mak("%s	 ehnl %d: 	ic in6rAUTODration faiMA_.\n",e+1		Vino->chB.vF%A.F_LO,iVino->chB.4	},e21{	1{	/	= -eINVAL;6+,	goto hu-_unrAUTODMA_vF%A;	+	}	X681{	/* 2 0;	+
+hu-_unrAUTODMA_vF%A:0+7video_unrAUTODMA_	ic ine&Vino->chA.vF%Ae21{hu-_	2c_del_bus:0+7vino_	2c_del_bus(e21{hu-_fr	=_	0x:0+7fr	=_	0x(SGI_VINO_IRQ,50,	0-21{hu-_fr	=_dage:0+7fr	=_dage(Vino->dummy_dage);eahu-_fr	=_vino:0+7kfr	=(Vino);eahu-_unmap:0+7iounmap(vinoER_+	+W366_chiret;68-stat80825cleanupMmodule(8082)u+ic ineF80825__exit vino_exit(8082)u62	+7video_unrAUTODMA_	ic ine&Vino->chA.vF%Ae21{7video_unrAUTODMA_	ic ine&Vino->chB.vF%Ae21{7vino_	2c_del_bus(e21{7fr	=_	0x(SGI_VINO_IRQ,50,	0-21{7fr	=_dage(Vino->dummy_dage);ea7kfr	=(Vino);ea7iounmap(vinoER_ }  dc62	}	+	+module_	nit(8ino_	nit);eamodule_exit(8ino_exitER_+	+MODULE_DESCRIPTION("Video4L___A d hpt3 * 4 SGI Indy VINO (IndyCam)");	+MODULE_LICENSE("GPL");		0x06814esctive tim.media/video/vino.hce_t hpt366media/video/vino.h= ht_h"TA6S};semedia/video/vino.h0d0a2aD2-04 23:44:55hp		.e		evice_t hpt366media/video/vino.h0d0anDD2-03 06342:40hp		.e		(w,
1,64651,84,ER_U/xN- * Copyright (C)/*999 Ulf Carlsson (ulfc@bun.falkenberg.se)+-sx Copyright (C)/d0a1 Ralf Baech29 ({alf@gnu.org)
+ * Copyright (C)/*999 Ulf Karlsson <ulfc@bun.falkenberg.se>
+ * Copyright (C)/d0a3 Ladislav Michl <ladis@6___A-mips.org>N ,DMAE
-0_},
-	eVINO_BASE		0x00080000W/* IncEISA address space */e+,e,n_}, VINO_H	+0_},
-	eVINO_HAE
-0_},
-	eVINO_REVID		0x0000	-0_},
-	eVINO_CTRL		0x0008	-0_},
-	eVINO_INTSTAT		0x0010W/* InDMAAupt s,atus	DMA-0_},
-	eVINO_I2C_CTRL		0x0018A-0_},
-	eVINO_I2C_DATA		0x0020	-0_},
-	eVINO_A_ALPHA		0x0028W/* C	},nxl A ...8*/e-0_},
-	eVINO_A_CLIPS		0x0030W/* Clippi
-		#drt8*/e-0_},
-	eVINO_A_CLIPE		0x0038W/* Clippi
-	end */e-0_},
-	eVINO_A_FRAMERT		0x0040W/* Framxra_= DMA-0_},
-	eVINO_A_FLDCNT		0x0048W/* Field ERunDMA DMA-0_},
-	eVINO_A_LNSZ		0x0050A-0_},
-	eVINO_A_LNCNT		0x0058A-0_},
-	eVINO_A_PGIX		0x0060W/* Page index DMA-0_},
-	eVINO_A_DESC_PTR		0x0068W/* Ptr0to next fhur descrip14es DMA-0_},
-	eVINO_A_DESC_TLB_PTR	0x0070W/* Ptr0to 	#drt8of descrip14e ta_MW DMA-0_},
-	eVINO_A_DESC_DATA0	0x0078W/* Descrip14e5			d 0 DMA-0_},
-	eVINO_A_DESC_DATA1	0x0080W/* ...8*/e-0_},
-	eVINO_A_DESC_DATA2	0x0088e-0_},
-	eVINO_A_DESC_DATA3	0x0090A-0_},
-	eVINO_A_FIFO_THRESHOLD	0x0098W/* FIFO5threshold DMA-0_},
-	eVINO_A_FIFO_RP		0x00a0A-0_},
-	eVINO_A_FIFO_WP		0x00a8e-0_},
-	eVINO_B_ALPHA		0x00b0W/* C	},nxl B ...8*/e-0_},
-	eVINO_B_CLIPS		0x00b8e-0_},
-	eVINO_B_CLIPE		0x00c0e-0_},
-	eVINO_B_FRAMERT		0x00c8e-0_},
-	eVINO_B_FLDCNT		0x00d0e-0_},
-	eVINO_B_LNSZ		0x00d8e-0_},
-	eVINO_B_LNCNT		0x00e0e-0_},
-	eVINO_B_PGIX		0x00e8e-0_},
-	eVINO_B_DESC_PTR		0x00f0e-0_},
-	eVINO_B_DESC_TLB_PTR	0x00f8e-0_},
-	eVINO_B_DESC_DATA0	0x0100e-0_},
-	eVINO_B_DESC_DATA1	0x0108e-0_},
-	eVINO_B_DESC_DATA2	0x0110e-0_},
-	eVINO_B_DESC_DATA3	0x0118e-0_},
-	eVINO_B_FIFO_THRESHOLD	0x0120e-0_},
-	eVINO_B_FIFO_RP		0x0128e-0_},
-	eVINO_B_FIFO_WP		0x0130	+0_},
-	eVINO_BASE	0x00080000W/* Vino	is in,* acEISA address space,s+M	,	+ * but i-xis not ancEISA busccard,DMAE
-/* Bitl in,* acVINO_REVIDcrAUTODMA */e-
-0_},
-	eVINO_REVID_REV_MASK		0x000fW/* bitl 0:38*/e-0_},
-	eVINO_REVID_ID_MASK		0x00f0W/* bitl 4:7 */e-
-/* Bitl in,* acVINO_CTRLcrAUTODMA */e+s,		0x0sgi_vino_c	},nxl 2	+7u32 _dad_dlphd	0+7vol inl	 u32 dlphd	0+	+0_},
-	eVINO_CLIP_X(x)		((x) &{	X3ff)	W/* bitl 0:9 */e+,_},
-	eVINO_CLIP_ODD(x)	(((x) &{	X1ff) << 10)W/* bitl 10:18 */e+,_},
-	eVINO_CLIP_EVEN(x)	(((x) &{	X1ff) << 19)W/* bitl 19s27h*/e+W832 _dad_clip+	#drt	0+7vol inl	 u32 clip+	#drt	0+7832 _dad_clip+end	0+7vol inl	 u32 clip+end	0+e+,_},
-	eVINO_FRAMERT_PAL	(1<<0)31	/* 0=NTSC 1=PAL */e+,_},
-	eVINO_FRAMERT_RT(x)	(((x) &{	X1fff) << 1)W/* bitl 1:12h*/e+W832 _dad_framx_ra_=	0+7vol inl	 u32 framx_ra_=	0+e+W832 _dad_field_ERunDMA	0+7vol inl	 u32 field_ERunDMA	0+7832 _dad_lMA__size	0+7vol inl	 u32 lMA__size	0+7832 _dad_lMA__ERunD	0+7vol inl	 u32 lMA__ERunD	0+7832 _dad_dage_index	0+7vol inl	 u32 dage_index	0+7832 _dad_next_4_desc	0+7vol inl	 u32 next_4_desc	0+7832 _dad_	#drt_desc_tbl	0+7vol inl	 u32 	#drt_desc_tbl	0+e+,_},
-	eVINO_DESC_JUMP		(1<<30)e+,_},
-	eVINO_DESC_STOP		(1<<31)e+,_},
-	eVINO_DESC_VALID		(1<<32)0+7832 _dad_desc_0	0+7vol inl	 u32 desc_0	0+7832 _dad_desc_1	0+7vol inl	 u32 desc_1	0+7832 _dad_desc_2	0+7vol inl	 u32 desc_2	0+7832 _dad_Bdesc_3	0+7vol inl	 u32 desc_3	0+e+W832 _dad_fifo_thres	0+7vol inl	 u32 fifo_thres	0+7832 _dad_fifo_eaad;6+7vol inl	 u32 fifo_eaad;6+7832 _dad_fifo_A_1,	;	+7vol inl	 u32 fifo_A_1,	;	+};eaea+#		0x0sgi_vino {	+0_},
-	eVINO_CHIP_ID		0xb	+0_},
-	eVINO_REV_NUMex)		((x) &{	X0f)e+,_},
-	eVINO_ID_VALUEex)	(((x) &{	Xf0) >> 4)0+7832 _dad_rev_id;	+7vol inl	 u32 rev_id;	E
 3_},
-	eVINO_CTRL_LITTLE_ENDIAN		(1<<0)	 3_},
-	eVINO_CTRL_A_FIELD_TRANS_INT	(1<<1)W/* Field transfckra7	inx0DMAE3_},
-	eVINO_CTRL_A_FIFO_OF_INT		(1<<2)W/* FIFO5heckflow inx0DMAE3_},
-	eVINO_CTRL_A_END_DESC_TBL_INT	(1<<3)W/* End of.desc	ta_MW inx0DMA+3_},
-	eVINO_CTRL_A_INT			(VINO_CTRL_A_FIELD_TRANS_INT | \s+M	,	+ VINO_CTRL_A_FIFO_OF_INT | \s+M	,	+ VINO_CTRL_A_END_DESC_TBL_INT)	 3_},
-	eVINO_CTRL_B_FIELD_TRANS_INT	(1<<4)W/* Field transfckra7	inx0DMAE3_},
-	eVINO_CTRL_B_FIFO_OF_INT		(1<<5)W/* FIFO5heckflow inx0DMA-3_},
-	eVINO_CTRL_B_END_DESC_TLB_INT	(1<<6)W/* End of.desc	ta_MW inx0DMA+3_},
-	eVINO_CTRL_B_END_DESC_TBL_INT	(1<<6)W/* End of.desc	ta_MW inx0DMA+3_},
-	eVINO_CTRL_B_INT			(VINO_CTRL_B_FIELD_TRANS_INT | \s+M	,	+ VINO_CTRL_B_FIFO_OF_INT | \s+M	,	+ VINO_CTRL_B_END_DESC_TBL_INT)	 3_},
-	eVINO_CTRL_A_DMA_ENBL		(1<<7)	 3_},
-	eVINO_CTRL_A_INTERLEAVE_ENBL	(1<<8)	 3_},
-	eVINO_CTRL_A_SYNC_ENBL		(1<<9)A(w,
67,51 +87,45,ER_U3_},
-	eVINO_CTRL_A_LUMA_ONLY		(1<<12)	 3_},
-	eVINO_CTRL_A_DEC_ENBL		(1<<13)W/* Decimation */e 3_},
-	eVINO_CTRL_A_DEC_SCALE_MASK		X1c000W/* bitl 14:170DMA+3_},
-	eVINO_CTRL_A_DEC_SCALE_SHIFT	(14)	 3_},
-	eVINO_CTRL_A_DEC_HOR_ONLY	(1<<17)W/* Horizontal  nly */e 3_},
-	eVINO_CTRL_A_DITHER		(1<<18)W/* 24 -> 8 bit dithMA,*MAE3_},
-	eVINO_CTRL_B_DMA_ENBL		(1<<19)AE3_},
-	eVINO_CTRL_B_INTERLEAVE_ENBL	(1<<20)AE3_},
-	eVINO_CTRL_B_SYNC_ENBL		(1<<21)AE3_},
-	eVINO_CTRL_B_SELECT		(1<<22)W/* 1=D1 0=Philips0DMA-3_},
-	eVINO_CTRL_B_RGB			(1<<22)W/* 1=RGB 0=YUV0DMA-3_},
-	eVINO_CTRL_B_LUMA_ONLY		(1<<23)A-3_},
-	eVINO_CTRL_B_DEC_ENBL		(1<<24)W/* Decimation */e-3_},
-	eVINO_CTRL_B_DEC_SCALE_MASK		X1c000000W/* bitl 25:280DMA+3_},
-	eVINO_CTRL_B_RGB			(1<<23)W/* 1=RGB 0=YUV0DMA+3_},
-	eVINO_CTRL_B_LUMA_ONLY		(1<<24)A+3_},
-	eVINO_CTRL_B_DEC_ENBL		(1<<25)W/* Decimation */e+3_},
-	eVINO_CTRL_B_DEC_SCALE_MASK		X1c000000W/* bitl 26:280DMA+3_},
-	eVINO_CTRL_B_DEC_SCALE_SHIFT	(26)AE3_},
-	eVINO_CTRL_B_DEC_HOR_ONLY	(1<<29)W/* Decimation horizontal  nly */e 3_},
-	eVINO_CTRL_B_DITHER		(1<<30)W/* C	},B 24 -> 8 bit dithMA,*MA-
-/* Bitl in,* acInDMAAupt and S,atus	rAUTODMA */e+7832 _dad_control);+7vol inl	 u32 control);
e 3_},
-	eVINO_INTSTAT_A_FIELD_TRANS	(1<<0)3/* Field transfckra7	inx0DMAE3_},
-	eVINO_INTSTAT_A_FIFO_OF		(1<<1)W/* FIFO5heckflow inx0DMAE3_},
-	eVINO_INTSTAT_A_END_DESC_TBL	(1<<2)W/* End of.desc	ta_MW inx0DMA+3_},
-	eVINO_INTSTAT_A			(VINO_INTSTAT_A_FIELD_TRANS | \s+M	,	+ VINO_INTSTAT_A_FIFO_OF | \s+M	,	+ VINO_INTSTAT_A_END_DESC_TBL)AE3_},
-	eVINO_INTSTAT_B_FIELD_TRANS	(1<<3)3/* Field transfckra7	inx0DMAE3_},
-	eVINO_INTSTAT_B_FIFO_OF		(1<<4)W/* FIFO5heckflow inx0DMAE3_},
-	eVINO_INTSTAT_B_END_DESC_TBL	(1<<5)W/* End of.desc	ta_MW inx0DMA+3_},
-	eVINO_INTSTAT_B			(VINO_INTSTAT_B_FIELD_TRANS | \s+M	,	+ VINO_INTSTAT_B_FIFO_OF | \s+M	,	+ VINO_INTSTAT_B_END_DESC_TBL)A+7832 _dad_inD4_s,atus);+7vol inl	 u32 inD4_s,atus);+A+7832 _dad_i2c_control);+7vol inl	 u32 i2c_control);+7832 _dad_i2c_di_dR_+7vol inl	 u32 i2c_di_dR_+ea7s,		0x0sgi_vino_c	},nxl a;ea7s,		0x0sgi_vino_c	},nxl bR_+}Os8-
/* Bitl in,* acClippi
-	S#drt8rAUTODMA */e-
-0_},
-	eVINO_CLIPS_START		0x3ff	W/* bitl 0:9 */e-0_},
-	eVINO_CLIPS_ODD_MASK		0x7fc00	W/* bitl 10:18 */e-0_},
-	eVINO_CLIPS_EVEN_MASK		0xff80000W/* bitl 19s27h*/e--
/* Bitl in,* acClippi
-	End rAUTODMA */e-
-0_},
-	eVINO_CLIPE_END			0x3ff	W/* bitl 0:9 */e-0_},
-	eVINO_CLIPE_ODD_MASK		0x7fc00	W/* bitl 10:18 */e-0_},
-	eVINO_CLIPE_EVEN_MASK		0xff80000W/* bitl 19s27h*/e--
/* Bitl in,* acFramx Ra_= rAUTODMA */e-
-0_},
-	eVINO_FRAMERT_PAL		(1<<0)3/* 0=NTSC 1=PAL */e-,_},
-	eVINO_FRAMERT_RT_MASK		0x1ffe	W/* bitl 1:12h*/e-
-/* Bitl in,* acVINO_I2C_CTRL */e-
-0_},
-	eVINO_CTRL_I2C_IDLE		(1<<0)3/* A_1,	: 0=* 4ce idle	)NM	,	+ * eaad: 0=idle 1=not idle */e-3_},
-	eVINO_CTRL_I2C_DIR		(1<<1)W/* 0={	ad 1=A_1,	 */e-3_},
-	eVINO_CTRL_I2C_MORE_BYTES	(1<<2)W/* 0=last bytel1=more bytes */e-3_},
-	eVINO_CTRL_I2C_TRANS_ckSY	(1<<4)W/* 0=trans donel1=trans busy */e-3_},
-	eVINO_CTRL_I2C_ACK		(1<<5)W/* 0=ack0  ce6S}d 1=ack0not */e-3_},
-	eVINO_CTRL_I2C_ckS	ERROR		(1<<7)W/* 0=no bus	MAAC1=bus	MAACDMA+3c62	}		0x06814esctive tim.net/ibmveth.Ee 2or 9s	{	net/ibmveth.E= ht_h"TA6S};senet/ibmveth.E0d0a4-12-07 i0059:45hp		.e		evice_t hpt366net/ibmveth.E0d0anDD2-04 17:23:06hp		.e		(w,
218x265218x8FER_U1	ibmveth_assert(V/dex != IBM_VETH_INVALID_MAP)Os81	6bmveth_assert(pool->skbuff[V/dex] == 0,	0-21ER-+		ma_addrC- vio_map_si
-le(adapDMA->vF%A	 skb->di_d80pool->buff_size, DMA_FROM_DEVICEe21{	1	ma_addrC- 	ma_map_si
-le(&adapDMA->vF%A->42		 skb->di_d8s+M	,	pool->buff_size, DMA_FROM_DEVICEe21X	X		pool->fr	=_map[fr	=_	/dex] = IBM_VETH_INVALID_MAP;	X		pool->	ma_addr[V/dex] = 	ma_addr;	(w,
238x265239,90x148MM	pool->fr	=_map[fr	=_	/dex] = IBM_VETH_INVALID_MAP;	X			pool->skbuff[V/dex] = 0,	0;e{	M	pool->e F_umer_	/dex--;	)NM	vio_unmap_si
-le(adapDMA->vF%A	 pool->	ma_addr[V/dex]80pool->buff_size, DMA_FROM_DEVICEe21{	11	ma_unmap_si
-le(&adapDMA->vF%A->42		s+M	,	+pool->	ma_addr[V/dex]80pool->buff_size,s+M	,	+DMA_FROM_DEVICEe21X1	1dev_kfr	=_skb_any(skbe21X1	1adapDMA->replenish_add_buff_faiMure++R_X		1break;	(w,
260},
+263,156ER_U1	(atomic_eaad(&adapDMA->rx_buff_pool[2].avaiMa_MW	 < adapDMA->rx_buff_pool[2].threshold))x1A-sta+/* kick0t acrAplenish	tasklet	if we,neA_0rAplenishi
-	and i-xisn'x0aleaady runni
-	*/s+nd MWit_nlMA_F808256bmveth_schedule_rAplenishi
-(s,		0x0ibmveth_adapDMA0*adapDMA)++{	+W1f(ibmveth_is_rAplenishi
-_neA_ed(adapDMA) &&_x1888(atomic_dec_0f_posithpt(&adapDMA->not_rAplenishi
-) == 0-) Nea7	schedule_work(&adapDMA->replenish_task);	+1}e+}e+e 8exrAplenish	tasklet	routMA_FDMAEic ineF80825ibmveth_replenish_task(s,		0x0ibmveth_adapDMA0*adapDMA) u62	(w,
276,156+288},
ER_U1Rbmveth_schedule_rAplenishi
-(adapDMA)x1A-stat/* kick0t acrAplenish	tasklet	if we,neA_0rAplenishi
-	and i-xisn'x0aleaady runni
-	*/s-nd MWit_nlMA_F808256bmveth_schedule_rAplenishi
-(s,		0x0ibmveth_adapDMA0*adapDMA)+-2	
-if(ibmveth_is_rAplenishi
-_neA_ed(adapDMA) && 6-1888(atomic_dec_0f_posithpt(&adapDMA->not_rAplenishi
-) == 0-) N		)NMschedule_work(&adapDMA->replenish_task);	-1}  }e-e 8exempty	and fr	=	ana buffer pool t_hlso usA_0to do5cleanup in,MAAor pathsFDMAEic ineF80825ibmveth_fr	=_buffer_pool(s,		0x0ibmveth_adapDMA0*adapDMA,l0,		0x0ibmveth_buff_pool *pool)u62	(w,
299x26+302},
x068		* 4(i = 0; i < pool->size	 ++i	 86231	s,		0x0sk_buff *skbC- dool->skbuff[V];e{	M	6f(skbe Ne)NMM	vio_unmap_si
-le(adapDMA->vF%A	s+M	,		ma_unmap_si
-le(&adapDMA->vF%A->42		s81	,1	M pool->	ma_addr[V]	s81	,1	M pool->buff_size,s81	,1	M DMA_FROM_DEVICEe21(w,
337x26+340},
x068XF	adapDMA->rx_buff_pool[pool].skbuff[V/dex] = 0,	0;e{e)Nvio_unmap_si
-le(adapDMA->vF%A	s+M	ma_unmap_si
-le(&adapDMA->vF%A->42		s81	, adapDMA->rx_buff_pool[pool].	ma_addr[V/dex]8s81	, adapDMA->rx_buff_pool[pool].buff_size,s81	, DMA_FROM_DEVICEe21(w,
408x265411,90x148{R_M6f(adapDMA->buffer_	TOD_addrC!= 0,	0- 862316f(!	ma_mappi
-_MAAor(adapDMA->buffer_	TOD_	ma)e Ne)NMMvio_unmap_si
-le(adapDMA->vF%A	 adapDMA->buffer_	TOD_	ma, 4096, DMA_BIDIRECTIONALe21{	11	ma_unmap_si
-le(&adapDMA->vF%A->42		s+M	,	+adapDMA->buffer_	TOD_	ma, 4096,s+M	,	+DMA_BIDIRECTIONALe21 ,	+adapDMA->buffer_	TOD_	ma = DMA_ERROR_CODE;	X		+	}	7fr	=_dage((16814ea7	},
-)adapDMA->buffer_	TOD_addre21(w,
417x26+422,90x148R_M6f(adapDMA->filter_	TOD_addrC!= 0,	0- 862316f(!	ma_mappi
-_MAAor(adapDMA->filter_	TOD_	ma)e Ne)NMMvio_unmap_si
-le(adapDMA->vF%A	 adapDMA->filter_	TOD_	ma, 4096, DMA_BIDIRECTIONALe21{	11	ma_unmap_si
-le(&adapDMA->vF%A->42		s+M	,	+adapDMA->filter_	TOD_	ma, 4096,s+M	,	+DMA_BIDIRECTIONALe21 ,	+adapDMA->filter_	TOD_	ma = DMA_ERROR_CODE;	X		+	}	7fr	=_dage((16814ea7	},
-)adapDMA->filter_	TOD_addre21(w,
426x265433ie22
-	{R_M6f(adapDMA->rx_queue.queue	addrC!= 0,	0- 862316f(!	ma_mappi
-_MAAor(adapDMA->rx_queue.queue		ma)e Ne)NMMvio_unmap_si
-le(adapDMA->vF%A	 adapDMA->rx_queue.queue		ma	 adapDMA->rx_queue.queue	len, DMA_BIDIRECTIONALe21{	11	ma_unmap_si
-le(&adapDMA->vF%A->42		s+M	,	+adapDMA->rx_queue.queue		ma	s+M	,	+adapDMA->rx_queue.queue	len,s+M	,	+DMA_BIDIRECTIONALe21 ,	+adapDMA->rx_queue.queue		ma = DMA_ERROR_CODE;	X		+	}	7kfr	=(adapDMA->rx_queue.queue	addre21(w,
472,90+482,13

-	{		{	/* 2 -ENOMEM;	 1}FER-+adapDMA->buffer_	TOD_	ma = vio_map_si
-le(adapDMA->vF%A	 adapDMA->buffer_	TOD_addr, 4096, DMA_BIDIRECTIONALe21-+adapDMA->filter_	TOD_	ma = vio_map_si
-le(adapDMA->vF%A	 adapDMA->filter_	TOD_addr, 4096, DMA_BIDIRECTIONALe21-+adapDMA->rx_queue.queue		ma = vio_map_si
-le(adapDMA->vF%A	 adapDMA->rx_queue.queue	addr	 adapDMA->rx_queue.queue	len, DMA_BIDIRECTIONALe21{	adapDMA->buffer_	TOD_	ma = 	ma_map_si
-le(&adapDMA->vF%A->42		s+M	,adapDMA->buffer_	TOD_addr, 4096, DMA_BIDIRECTIONALe21++adapDMA->filter_	TOD_	ma = 	ma_map_si
-le(&adapDMA->vF%A->42		s+M	,adapDMA->filter_	TOD_addr, 4096, DMA_BIDIRECTIONALe21++adapDMA->rx_queue.queue		ma = 	ma_map_si
-le(&adapDMA->vF%A->42		s+M	,adapDMA->rx_queue.queue	addr	s+M	,adapDMA->rx_queue.queue	len, DMA_BIDIRECTIONALe21{R_M6f((	ma_mappi
-_MAAor(adapDMA->buffer_	TOD_	ma) ) ||681888(	ma_mappi
-_MAAor(adapDMA->filter_	TOD_	ma)e ||6(w,
644},
+658},
x068XF	8exmap0t ac	nitial fragm.
-x*/eU1desc[0].fields.length		=/nfrags ? skb->len	- skb->di_d	len : skb->len;	-Mdesc[0].fields.address - vio_map_si
-le(adapDMA->vF%A	 skb->di_d8	+	_}sc[0].fields.address - 	ma_map_si
-le(&adapDMA->vF%A->42		 skb->di_d8s81	,1	desc[0].fields.length, DMA_TO_DEVICEe21X1desc[0].fields.val825		=/1;	}	(w,
662},
+676},
x068	1c829(curfrag--- 86231skb_frag	t *frag	= &skb_shi
fo(skbe->frags[curfrag];e{	Mdesc[curfrag+1].fields.addresse)NMM- vio_map_si
-le(adapDMA->vF%A	s+M	,= 	ma_map_si
-le(&adapDMA->vF%A->42		s81	,1dage_address(frag->dage) + frag->dage_offset	s81	,1frag->size, DMA_TO_DEVICEe21X1Mdesc[curfrag+1].fields.length	= frag->size;A(w,
674},
+688},
x068		,adapDMA->ic is.tx_dropped++R_X		1/* Fr	=	all t acmappi
-scweXjust ceaata7	*/eU1		1c829(curfrag < nfragse Ne)NMM	vio_unmap_si
-le(adapDMA->vF%A	s+M	,		ma_unmap_si
-le(&adapDMA->vF%A->42		s81	,1	M desc[curfrag+1].fields.address	s81	,1	M desc[curfrag+1].fields.length,s81	,1	M DMA_TO_DEVICEe21(w,
714},
+728,90x148M}	X681do Ne)NMvio_unmap_si
-le(adapDMA->vF%A	 desc[nfrags].fields.address	 desc[nfrags].fields.length, DMA_TO_DEVICEe21+11	ma_unmap_si
-le(&adapDMA->vF%A->42		s+M	,	desc[nfrags].fields.address	s+M	,	desc[nfrags].fields.length, DMA_TO_DEVICEe21X1}31c829(--nfrags >= 0-21{R_Mdev_kfr	=_skb(skbe21	0x06814esctive tim.net/tg3.Ee 2or 9s	{	net/tg3.E= ht_h"TA6S};senet/tg3.E0d0anDD1-,6 15:08:48hp		.e		evice_t hpt366net/tg3.E0d0anDD2p		 15:58s27hp		.e		(w,
60,8
+60x8
x068XF0_},
-	ehRV_MODULE_NAME		"tg3"XF0_},
-	ePFXehRV_MODULE_NAME	": "e-3_},
-	ehRV_MODULE_VERSION	"3.19"e-3_},
-	ehRV_MODULE_RELDATE	"January 26x/d0a5"	+0_},
-	ehRV_MODULE_VERSION	"3.21"	+0_},
-	ehRV_MODULE_RELDATE	"February 8x/d0a5"	8XF0_},
-	eTG3_DEF_MAC_MODE	0XF0_},
-	eTG3_DEF_RX_MODE				(w,
893},
+893},
x068		,888888GRC_LCLCTRL_GPIO_OUTPUT1))Os81	7udelay(100)0	U1	} -	{e 86)NMMinx0no_gpio221{	11u32 no_gpio221 	11u32 grc-O_4al_ctrl21X	X		M6f (tp_peerC!= tp &&_14ea901}8F+901}8Fx068		,	{	/* 221X	X		M/* On 5753	and variants	 GPIO2 Aannotlbe usA_.8*/e-		Mno_gpio2	= (tp->nic_sram_si_d_cfg &-
-	,18888NIC_SRAM_DATA_CFG_NO_GPIO2) !={021{	11no_gpio2	= tp->nic_sram_si_d_cfg &-+-	,18888NIC_SRAM_DATA_CFG_NO_GPIO221X	X		Mgrc-O_4al_ctrl	= GRC_LCLCTRL_GPIO_OE0 |s81	,1	 GRC_LCLCTRL_GPIO_OE1 |6(w,
914}290+914}1,
x068		,	,18888GRC_LCLCTRL_GPIO_OUTPUT2)Os81	7+	}	7	tw32_f(GRC_LOCAL_CTRL, tp->grc-O_4al_ctrl	|-
-	,8888888grc-O_4al_ctrl)0	+M	,W	Mgrc-O_4al_ctrl)Os81	7udelay(100)0	U-
-	,grc-O_4al_ctrl	= GRC_LCLCTRL_GPIO_OE0 |s-1	,1	 GRC_LCLCTRL_GPIO_OE1 |6-1	,1	 GRC_LCLCTRL_GPIO_OE2 |6-1	,1	 GRC_LCLCTRL_GPIO_OUTPUT0 |6-1	,1	 GRC_LCLCTRL_GPIO_OUTPUT1 |6-1	,1	 GRC_LCLCTRL_GPIO_OUTPUT2;	)NM	6f (no_gpio2e Ne)NMM	grc-O_4al_ctrl	&= ~(GRC_LCLCTRL_GPIO_OE2 |6-1	,1	18888GRC_LCLCTRL_GPIO_OUTPUT2)Os-M	,}6+	1	grc-O_4al_ctrl	|= GRC_LCLCTRL_GPIO_OUTPUT0;	+	X		1tw32_f(GRC_LOCAL_CTRL, tp->grc-O_4al_ctrl	|-
-	,8888888grc-O_4al_ctrl)0	+M	,W	Mgrc-O_4al_ctrl)Os81	7udelay(100)0	U-
-	,grc-O_4al_ctrl	= GRC_LCLCTRL_GPIO_OE0 |s-1	,1	 GRC_LCLCTRL_GPIO_OE1 |6-1	,1	 GRC_LCLCTRL_GPIO_OE2 |6-1	,1	 GRC_LCLCTRL_GPIO_OUTPUT0 |6-1	,1	 GRC_LCLCTRL_GPIO_OUTPUT1;_U1	
6f (!no_gpio2e Ne+NMM	grc-O_4al_ctrl	&= ~GRC_LCLCTRL_GPIO_OUTPUT2;	8		,	tw32_f(GRC_LOCAL_CTRL, tp->grc-O_4al_ctrl	|- 	-	,8888888grc-O_4al_ctrl)0	 	-	,udelay(100)0	(w,
2146x8
+2134,90x148MM6f (tr32(TG3PCI_DUAL_MAC_CTRL) &{DUAL_MAC_CTRL_ID)e{	M	port_a = 0;FER-+	serdes_cfg = tr32(MAC_SERDES_CFG) &-
-	,((1 << 23e | (1 << 22e | (1 << 21e | (1 << 20)ER_+	W/* preserve bitl 0-11,13,14 * 4 814eal pre-emphasis */	+7W/* preserve bitl 20-23 * 4 voltage regula14e5*/	+7Wserdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;48M}	X681sg_dig_ctrl	= tr32(SG_DIG_CTRL)0	(w,
2158,90+2147,90x148MM	1u32 val	= serdes_cfg21X	X		MM6f (port_a)6-1	,1	val	|= 0xc0108800	+M	,W	val	|= 0xc0100000	 	-	,-	{e	-1	,1	val	|= 0x40108800	+M	,W	val	|= 0x40100000	 	-	,tw32_f(MAC_SERDES_CFG,-val)Os81	7+	}	7	tw32_f(SG_DIG_CTRL, 0x01388400)0	(w,
2183x2652172},
x068XF	6f (sg_dig_ctrl	!={expec1ed_sg_dig_ctrl- 862316f (workarr1c8)6-1	,tw32_f(MAC_SERDES_CFG,-serdes_cfg | 0xc011880)0	+M	,tw32_f(MAC_SERDES_CFG,-serdes_cfg | 0xc011000)0	U1	tw32_f(SG_DIG_CTRL, expec1ed_sg_dig_ctrl | (1 << 30))Os81	udelay(5)	0U1	tw32_f(SG_DIG_CTRL, expec1ed_sg_dig_ctrl)0	(w,
2224,90+2213,90x148MM	11u32 val	= serdes_cfg21X	X		MMM6f (port_a)6-1	,1		val	|= 0xc0108800	+M	,W		val	|= 0xc0100000	 	-	,,-	{e	-1	,1		val	|= 0x40108800	+M	,W		val	|= 0x40100000	 	 	-	,,tw32_f(MAC_SERDES_CFG,-val)Os81	77+	(w,
2234,8
+2223,120x148MM	1tw32_f(SG_DIG_CTRL, 0x01388400)0	 	-	,udelay(40ER_ 	+W		M/* Link parallel detec1ion - lMAkxis up5*/	+7W	M/*  nly if we,havacPCS_SYNC	and not */e+7W	M/*   ce6Si
-	ER_PIOccode words	*/eU1			mac_s,atus	= tr32(MAC_STATUS)Os-M	,M6f (mac_s,atus	& MAC_STATUS_PCS_SYNCEDe Ne+NMM	6f ((mac_s,atus	& MAC_STATUS_PCS_SYNCEDe &&-+-	,18888!(mac_s,atus	& MAC_STATUS_RCVD_CFG)	 86231		1tg3_setup_flow_control(tp, 0,50)0	 	-	,	curr.
-_lMAk_up5=/1;	}1	77+	(w,
5416x8
+5409ie22
-	{,udelay(10e21{R_M6f (tp->tg3_*65142	& TG3_FLG2_PHY_SERDESe Ne)NM6f (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704	 Ne+MM6f ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704	 &&-+-	,!(tp->tg3_*65142	& TG3_FLG2_SERDES_PREEMPHASIS)	 86231	/* Set d hpt transmis6ioncle0xl to 1.2V  */e+7W	/*  nly if * acs14eal pre-emphasis bi-xis not set5	*/eU1		val	= tr32(MAC_SERDES_CFG);eU1		val	&= 0xfffff0000	 	-	val	|= 0x8800	(w,
7513,6 +7508x8FER_U1	tg3_eaad_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg)	0U1	tp->nic_sram_si_d_cfg = nic_cfgR_ 	+W	tg3_eaad_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);	+	X		eeprom_s14ea/* e_Sr1c8
=/1;	}	2316f ((nic_cfg	& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==	(w,
7531}8F+7528},
x068		,eeprom_phy_6d	= 0;	}	2316f (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750e Ne)NMMtg3_eaad_mem(tp, NIC_SRAM_DATA_CFG_2, &led_cfg)	0)NMMled_cfg	&= (NIC_SRAM_DATA_CFG_LED_MODE_MASK	|-+NMMled_cfg	= cfg2	& (NIC_SRAM_DATA_CFG_LED_MODE_MASK	|- 	-	,8888SHASTA_EXT_LED_MODE_MASK)0	U1	} -	{e- 	-	led_cfg	= nic_cfg	& NIC_SRAM_DATA_CFG_LED_MODE_MASK0	(w,
7590,90+7586,13

-	{		6f (nic_cfg	& NIC_SRAM_DATA_CFG_FIBER_WOL)e{	M	tp->tg3_*6514	|= TG3_FLAG_SERDES_WOL_CAP;FER-+	tg3_eaad_mem(tp, NIC_SRAM_DATA_PHY_ID, &cfg2);	{		6f (cfg2	& (1 << 17))e{	M	tp->tg3_*65142	|= TG3_FLG2_CAPACITIVE_COUPLINGR_+ea7	8exserdescs14eal pre-emphasis incrAUTODMA 0x590 set5by */	+7W/* 	XFEcode 6f bi-x18 is set */e+7W6f (cfg2	& (1 << 18)-	{	1	tp->tg3_*65142	|= TG3_FLG2_SERDES_PREEMPHASIS;48M}	X681/* Readi
-	* acPHY IDcrAUTODMA Aan ER_Plict with ASF1	0x06814esctive tim.net/tg3.hce_t hpt366net/tg3.h= ht_h"TA6S};senet/tg3.h0d0anDD1-,4 17:39:280p		.e		evice_t hpt366net/tg3.h0d0anDD2-02 15:40:31hp		.e		(w,
2106},
+2106}7,ER_U3_},
-	eTG3_FLG2_CAPACITIVE_COUPLING	0x00004000	U3_},
-	eTG3_FLG2_FLASH			0x00008000	U3_},
-	eTG3_FLG2_HW_TSO			0x00010000	+0_},
-	eTG3_FLG2_SERDES_PREEMPHASIS	0x00020000	X681u32	-	,splUDMmod=_max_eaqsx1A0_},
-	eSPLIT_MODE_5704_MAX_REQ		31	0x06814esctive tim.pci/hotplug/rpaphp.hce_t hpt366pci/hotplug/rpaphp.h= ht_h"TA6S};sepci/hotplug/rpaphp.h0d0a4-10-06 09:43:44hp	7.e		evice_t hpt366pci/hotplug/rpaphp.h0d0anDD2-02 22342:11hp		.e		(w,
109ie3 +109i,
ER_UexDMAnl0,		0x0	TOD_h	ad rpaphp_sloD_h	ad;_UexDMAnlinx0num_sloDs;static ineFinlMA_F-		.6s_hotplug_capa_MW(s,		0x0	ic in_noF% *dn)	-{_MW16814ea7	W_PCI_p,	 = gTO_property(dn, "ibm,fw-pci-hot-plug-ctrl",50,	0-21-hpt366_chi(V/() (ptrC!= 0,	0-;  }e-e 8exfunc1ion protoA_4,s,DMAE
 /*  paphp_pci.c,DMA	0x06814esctive tim.pci/hotplug/rpaphp_core.Ee 2or 9s	{	pci/hotplug/rpaphp_core.E= ht_h"TA6S};sepci/hotplug/rpaphp_core.E0d0a4-10-06 09:43:44hp	7.e		evice_t hpt366pci/hotplug/rpaphp_core.E0d0anDD2-07 16:10:15hp		.e		(w,
224},
+224},
x068XF	6f (!V/dex,s,|| !F_LOs,|| !A_4,s,|| !domains	 86231/* SloD does not havacdyF_Lically-remova_MW childr.
8*/e-		366_chi1;	{	1{	/* 2 -EINVAL;687+	}	6f (drc_V/dex,s)e{	M*drc_V/dex,s = V/dex,s;	(w,
260},
+260},
x068	}	X681{c = gTO_childr.
_props(dn->dar.
-, &V/dex,s, &n_LOs, &A_4,s, &domains	x1-+6f (rc	 Ne+M6f (rc < 0) Ne 		366_chi1;	8	}	X6(w,
287,2,
+287,43

-	{	366_chi1;	8-static ineFinx06s_php_dn(s,		0x0	ic in_noF% *dn	 V/(2**V/dex,s, V/(2**n_LOs, V/(2**A_4,s,6-188V/(2**powMA_	omains	u+odma	= _nt5-s_php_A_4,(W_PCI_drc_A_4,)++{	+W16814ea7	},
-	value;	+	c_PCI_endptr;eaea7/* PCI Hotplug noF%s havacan	inDMgt3 * 4 drc_A_4, */	+7value	= simple_s,rtoul(drc_A_4,, &endptr, 10ER_+	6f (endptr == drc_A_4,)++	1{	/* 2 0;	+
+	366_chi1;	{}eaea+#defininx06s_php_dn(s,		0x0	ic in_noF% *dn	 V/(2**V/dex,s, V/(2**n_LOs,e+7W6/(2**A_4,s,8V/(2**powMA_	omains	u {	+W1		._drc_A_4,s;stW1		. c;FER-+6f (!Vs_hotplug_capa_MW(dn))_U1	{	/* 2 (0ER_MW{c = gTO_childr.
_props(dn, V/dex,s, n_LOs, A_4,s,8powMA_	omains	x1-+6f (rc	_U1	{	/* 2 (0ER_MW{	/* 2 (1ER_+	{c = gTO_childr.
_props(dn, V/dex,s, n_LOs, &drc_A_4,s,8powMA_	omains	x1+M6f (rc >= 0- Ne+MM6f (-s_php_A_4,((W_PCI_) &drc_A_4,s[1]Ee Ne+NMM*A_4,s = drc_A_4,s;s+M	,  6_chi1;	{	1}	+1}e+e+W{	/* 2 0;	68_A+tic ineFinx06s_dr_dn(s,		0x0	ic in_noF% *dn	 V/(2**V/dex,s, V/(2**n_LOs, V/(2**A_4,s,6-188V/(2**powMA_	omains, V/(2**my_drc_V/dex	u+odma	= _nt5-s_dr_dn(s,		0x0	ic in_noF% *dn	 V/(2**V/dex,s, V/(2**n_LOs,e+7W6/(2**A_4,s,8V/(2**powMA_	omains, V/(2**my_drc_V/dex	u8{R_M6		. c;FER 	*my_drc_V/dex	= (V/(2*) gTO_property(dn, "ibm,my-drc-V/dex",50,	0-21-16f(!*my_drc_V/dex	 			+W1f(!*my_drc_V/dex	u81	{	/* 2 (0ER_8XF	6f (!dn->dar.
-)A(w,
314},
+331},
x068XF	{c = gTO_childr.
_props(dn->dar.
-, V/dex,s, n_LOs, A_4,s,s81	,1dowMA_	omains	x1-+{	/* 2 ({c == 0-21++{	/* 2 ({c >= 0-21{}9 aE80D-/mLinlMA_F-		.6s_v	ic in_rXFE(s,		0x0	ic in_noF% *dn)		0x06814esctive tim.pci/pci-sysfs.Ee 2or 9s	{	pci/pci-sysfs.E= ht_h"TA6S};sepci/pci-sysfs.E0d0anDD1-06 12:30:290p		.e		evice_t hpt366pci/pci-sysfs.E0d0anDD2-02 22342:15hp		.e		(w,
436},
+436},
x068		u81	{om_attr = kmal			(sizeof(*{om_attr), GFP_ATOMIC);	{		6f ({om_attr) Ne+NMMmemset({om_attr, 0x0080sizeof(*{om_attr));eU1		pF%A->{om_attr = {om_attr;eU1		{om_attr->sizeC- dci_easource	len(pF%A	 PCI_ROM_RESOURCEe21X1	1{om_attr->attr.F_LOC- "{om";		0x06814esctive tim.pci/pcie/portdrv.hce_t hpt366pci/pcie/portdrv.h= ht_h"TA6S};sepci/pcie/portdrv.h0d0anDD1-14 15:07:350p		.e		evice_t hpt366pci/pcie/portdrv.h0d0anDD2-02 22341:40hp		.e		(w,
28,14 +28,13,ER_U3_},
-	egTO_descrip14e_id(A_4,, serv in) (((A_4, - 4) << 4e | serv in)9 aEexDMAnl0,		0x0bus_A_4, pcie_port_bus_A_4,x1-exDMAnl0,		0x0	ic in_d hpt3 pcieport_generic_d hpt3;_UexDMAnlinx0pcie_port_	ic in_probW(s,		0x0dci_	ic	*F%Ae21UexDMAnlinx0pcie_port_	ic in_rAUTODMA(s,		0x0dci_	ic	*F%Ae21U,e,_}, CONFIG_PM1-exDMAnlinx0pcie_port_	ic in_suspend(s,		0x0dcie_	ic in6*F%A	 A32 	#dte);e-exDMAnlinx0pcie_port_	ic in_rA_ume(s,		0x0dcie_	ic in6*F%A-21+exDMAnlinx0pcie_port_	ic in_suspend(s,		0x0dci_	ic	*F%A	 A32 	#dte);e+exDMAnlinx0pcie_port_	ic in_rA_ume(s,		0x0dci_	ic	*F%Ae21U,c62	}	-exDMAnl80825pcie_port_	ic in_rAmove(s,		0x0dcie_	ic in6*F%A-21+exDMAnl80825pcie_port_	ic in_rAmove(s,		0x0dci_	ic	*F%Ae21UexDMAnl80825pcie_port_bus_rAUTODMA(8082)21UexDMAnl80825pcie_port_bus_unrAUTODMA(8082)21U		0x06814esctive tim.pci/pcie/portdrv_bus.Ee 2or 9s	{	pci/pcie/portdrv_bus.E= ht_h"TA6S};sepci/pcie/portdrv_bus.E0d0anDD1-14 15:07:350p		.e		evice_t hpt366pci/pcie/portdrv_bus.E0d0anDD2-02 22341:40hp		.e		(w,
14,8
+14,6
x068XF0incluF% <6___A/pcieport_if.h>_A+tic ineFinx0generic_probW (s,		0x0	ic in	*F%Ae {W{	/* 2 0;}+tic ineFinx0generic_rAmove (s,		0x0	ic in	*F%Ae { {	/* 2 0;}+E80D-/mLinx0pcie_port_bus_match(s,		0x0	ic in	*F%A,l0,		0x0	ic in_d hpt3 _drAe21U80D-/mLinx0pcie_port_bus_suspend(s,		0x0	ic in6*F%A	 A32 	#dte);eU80D-/mLinx0pcie_port_bus_rA_ume(s,		0x0	ic in6*F%A-21(w,
27,23 +25,14 x068	.rA_ume	,= pcie_port_bus_rA_ume, 0 }Os8-
0,		0x0	ic in_d hpt3 pcieport_generic_d hpt36=62	-7.F_LO =	"pcieport",e-7.bus	= &pcie_port_bus_A_4,,e-7.probW =0generic_probW,e-7.rAmove =0generic_rAmove,e-}21-hE80D-/mLinx0pcie_port_bus_match(s,		0x0	ic in	*F%A,l0,		0x0	ic in_d hpt3 _drAeu8{R_Ms,		0x0dcie_	ic in6*dcieF%A;	AMs,		0x0dcie_port_serv in_d hpt3 _drhpt3;_U1-+6f (	drA->busC!= &pcie_port_bus_A_4,,|| R-+		eA->busC!= &pcie_port_bus_A_4,	||6-1	drA == &pcieport_generic_d hpt3	 Ne+M6f (drA->busC!= &pcie_port_bus_A_4,,|| 	eA->busC!= &pcie_port_bus_A_4,	u81	{	/* 2 0;	-1} +	u81dcieF%A	= to_dcie_	ic in(F%Ae21U	d hpt36=6to_serv in_d hpt3(drAe21UM6f (888(	 hpt3->id_ta_MW->vendorC!= PCI_ANY_ID && 6	0x06814esctive tim.pci/pcie/portdrv_core.Ee 2or 9s	{	pci/pcie/portdrv_core.E= ht_h"TA6S};sepci/pcie/portdrv_core.E0d0anDD1-14 15:07:350p		.e		evice_t hpt366pci/pcie/portdrv_core.E0d0anDD2-02 22341:40hp		.e		(w,
17,8
+17,6
x068XFexDMAnlinx0pcie_mch_quirk;7/* MSI-quirk Indica14e5*/	 1-exDMAnl0,		0x0	ic in_d hpt3 pcieport_generic_d hpt3;_-hE80D-/mLinx0pcie_port_probW_serv in(s,		0x0	ic in6*F%A-u8{R_Ms,		0x0dcie_	ic in6*dcieF%A;	(w,
103,6 +101},
x068FDMAEic ineF80825release_dcie_	ic in(s,		0x0	ic in6*F%A-u8{R+Wpr"Mak(KERN	DEBUG "Fr	=	Port Serv in[%s]\n", 	eA->bus_82)21U7kfr	=(to_dcie_	ic in(F%Ae);		-	{}9 a(w,
217,18
+216,18

-	{	366_chiserv insx1A-static ineF80825dcie_	ic in_	nit(s,		0x0dcie_	ic in6*dar.
-, 0)NMMs,		0x0dcie_	ic in6*F%A	 6)NMMinx0port_A_4,, inx0serv in_A_4,)++ic ineF80825dcie_	ic in_	nit(s,		0x0dci_	ic	*dar.
-, s,		0x0dcie_	ic in6*F%A	 6+Minx0port_A_4,, inx0serv in_A_4,, inx0irq, inx0irqMmod=-u8{R_Ms,		0x0	ic in6*F%A in;_U1-+6f (dar.
-) Ne)NM	eA->id.vendorC= dar.
-->dort->vendor;e)NM	eA->id.	ic in6=6dar.
-->dort->F%A in;_)NM	eA->id.port_A_4,C- dort_A_4,;_)NM	eA->id.serv in_A_4,	= (1 << serv in_A_4,);	-1} +		eA->dort6=6dar.
-; +		eA->inDMAAuptMmod= = VrqMmod=; +		eA->irq = Vrq; +		eA->id.vendorC= dar.
-->vendor;e+M	eA->id.	ic in6=6dar.
-->F%A in;_+M	eA->id.port_A_4,C- dort_A_4,;_+M	eA->id.serv in_A_4,	= (1 << serv in_A_4,);	X681/* InitializeCgeneric0	ic in6inDMAface */e_Mdev in6=6&F%A->42	 in;_(w,
240,3565239,23

-	{	42	 in->4 hpt36=60,	0;e{	42	 in->4 hpt3_si_d6=60,	0; e{	42	 in->release = {elease_dcie_	ic in;7/* callback0to fr	=	dcie 	ic	*/e-	spr"Maf(&42	 in->bus_82[0], "%s.%02x",5dar.
-->F%A in.bus_82	 6)NMMgTO_descrip14e_id(port_A_4,, serv in_A_4,));	-Mde	 in->dar.
-	= ((dar.
-	== 0,	0- ? 0,	0 : &par.
-->F%A in-21++spr"Maf(&42	 in->bus_82[0], "dcie%02x",56+,	gTO_descrip14e_id(port_A_4,, serv in_A_4,));	+Mde	 in->dar.
-	= &par.
-->F%A;68-static ineFs,		0x0dcie_	ic in* al			_dcie_	ic in(e-	s,		0x0dcie_	ic in6*dar.
-, s,		0x0dci_	ic	*bridge, 0+ic ineFs,		0x0dcie_	ic in* al			_dcie_	ic in(s,		0x0dci_	ic	*dar.
-, R_M6		.port_A_4,, inx0serv in_A_4,, inx0irq, inx0irqMmod=-u8{R_Ms,		0x0dcie_	ic in6*F%A in;_)N80D-/mLinx0NR_PORTS	= 0;	}	23dev in6=6kmal			(sizeof(s,		0x0dcie_	ic in), GFP_KERNELER_F	6f (!dev in)9 1	{	/* 2 0,	0;e{e Mmemset(dev in, 0,5sizeof(s,		0x0dcie_	ic in));	-Mde	 in->dort6=6bridge;	-Mde	 in->inDMAAuptMmod= = VrqMmod=; -Mde	 in->irq = Vrq; -+6f (!dar.
-) Ne)NMdcie_	ic in_	nit(0,	0, dev in, port_A_4,, serv in_A_4,);_)NMNR_PORTS++R_)NM	eA in->4%A in.4 hpt36=6&pcieport_generic_d hpt3;_-	+spr"Maf(&42	 in->F%A in.bus_82[0], "dort%d",50R_PORTS); 6)N} -	{e 8 e)NMdcie_	ic in_	nit(dar.
-, dev in, port_A_4,, serv in_A_4,);_)N}+tWpr"Mak(KERN	DEBUG "Al			a_= Port Dev in[%s]\n", 	eA in->F%A in.bus_82);	+Mdcie_	ic in_	nit(dar.
-, dev in, port_A_4,, serv in_A_4,,0irq,irqMmod=-;R+Wpr"Mak(KERN	DEBUG "Al			a_= Port Serv in[%s]\n", 	eA in->F%A in.bus_82);	{	366_chiF%A in;_U}9 a(w,
291},
+278,6
x068XFinx0pcie_port_	ic in_rAUTODMA(s,		0x0dci_	ic	*F%Aeu62	
-s,		0x0dcie_	ic in6*dar.
-;stW1		.s,atus, A_4,, capa_iliti,s,8VrqMmod=,8V;stW1		.vec14es[PCIE_PORT_DEVICE_MAXSERVICES];e{	u16crAU1621(w,
306,2,
+292,13

-	{	capa_iliti,s = gTO_port_	ic in_capa_ility(F%Ae21U	VrqMmod= = as814e_inDMAAuptMmod=(F%A	 vec14es, capa_iliti,s)0	U-
-/* Al			a_= dar.
-	*/e-	dar.
-	= al			_dcie_	ic in(0,	0, dev, A_4,, 0, 	eA->irq, irqMmod=-;R-+6f (!dar.
-) _U1	{	/* 2 -ENOMEM;	-	_)N80D-us	= 	ic in_rAUTODMA(&par.
-->F%A in-21-+6f (80D-us) Ne)NMkfr	=(dar.
-);_U1	{	/* 2 s,atus);)N}+tWgTO_dec ine&par.
-->F%A in-21-+dci_sTO_drvsi_d(F%A	 dar.
-);	_-hE-/* Al			a_= childiserv ins 6f any */e W* 4 (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i+1) 86231s,		0x0dcie_	ic in6*child;	}	2316f (capa_iliti,s & (1 << i)	 86231	childi= al			_dcie_	ic in(e-		,1dar.
-,7W/* par.
-	*/ 6)NMM	F%A	 7W/* Root/Ups,	eam/Downs,	eam */e+7W	MF%A	 7W/* dar.
-	*/e8MM	1t_4,,7W/* dort A_4, */X	X		MM6,7	8exserc in6A_4, */	X		MMvec14es[i],	8exirq */	(w,
345}1,
+317,21

-	{}68XF0i,_}, CONFIG_PM1-inx0pcie_port_	ic in_suspend(s,		0x0dcie_	ic in6*F%A	 A32 	#dte)
+inx0pcie_port_	ic in_suspend(s,		0x0dci_	ic	*F%A	 A32 	#dte)u62	
-s,		0x0	TOD_h	ad 		*haad;6+7s,		0x0	TOD_h	ad 		*haad, *tmp;R_Ms,		0x0	ic in6NMM*dar.
-, *child;	}	0,		0x0	ic in_d hpt3 	M*drhpt3;_UMs,		0x0dcie_port_serv in_d hpt3 _serv in_d hpt30	U-
-dar.
-	= &F%A->42	 in;_+-dar.
-	= &F%A->42	;_UMh	ad = &par.
-->childr.
21-+1c829 (!	TOD_empty(h	ad)e Ne)NMchildi= container_of(h	ad->next,l0,		0x0	ic in, noF%-;R+Wtmpi= h	ad->next;R+W1c829 (h	ad != tmp) Ne+NMchildi= container_of(tmp,l0,		0x0	ic in, noF%-;R+WWtmpi= tmp->next;R+W16f (child->busC!= &pcie_port_bus_A_4,	u+7W	continue;	X1Md hpt36=6child->drhpt3;_UM	6f (!d hpt3	6231	continue;	(w,
366}1,
+342,21

-	{	{	/* 2 0; 68-statinx0pcie_port_	ic in_rA_ume(s,		0x0dcie_	ic in6*F%A- 
+inx0pcie_port_	ic in_rA_ume(s,		0x0dci_	ic	*F%Ae u62 	
-s,		0x0	TOD_h	ad 		*haad;6+7s,		0x0	TOD_h	ad 		*haad, *tmp;R_Ms,		0x0	ic in6NMM*dar.
-, *child;	}	0,		0x0	ic in_d hpt3 	M*drhpt3;_UMs,		0x0dcie_port_serv in_d hpt3 _serv in_d hpt30	U-
-dar.
-	= &F%A->42	 in;_+-dar.
-	= &F%A->42	;_UMh	ad = &par.
-->childr.
21-+1c829 (!	TOD_empty(h	ad)e Ne)NMchildi= container_of(h	ad->next,l0,		0x0	ic in, noF%-;R+Wtmpi= h	ad->next;R+W1c829 (h	ad != tmp) Ne+NMchildi= container_of(tmp,l0,		0x0	ic in, noF%-;R+WWtmpi= tmp->next;R+W16f (child->busC!= &pcie_port_bus_A_4,	u+7W	continue;	X1Md hpt36=6child->drhpt3;_UM	6f (!d hpt3	6231	continue;	(w,
389,45,+369,46

-	{}68,c62	}	tat80825pcie_port_	ic in_rAmove(s,		0x0dcie_	ic in6*F%A-
+80825pcie_port_	ic in_rAmove(s,		0x0dci_	ic	*F%Aeu62	
-s,		0x0	TOD_h	ad 		*haad;6+7s,		0x0	TOD_h	ad 		*haad, *tmp;R_Ms,		0x0	ic in6NMM*dar.
-, *child;	}	0,		0x0	ic in_d hpt3 	M*drhpt3;_UMs,		0x0dcie_port_serv in_d hpt3 _serv in_d hpt30	+Minx0inDMAAuptMmod= = PCIE_PORT_INTx_MODE0	U-
-dar.
-	= &F%A->42	 in;_+-dar.
-	= &F%A->42	;_UMh	ad = &par.
-->childr.
21-+1c829 (!	TOD_empty(h	ad)e Ne)NMchildi= container_of(h	ad->next,l0,		0x0	ic in, noF%-;R+Wtmpi= h	ad->next;R+W1c829 (h	ad != tmp) Ne+NMchildi= container_of(tmp,l0,		0x0	ic in, noF%-;R+WWtmpi= tmp->next;R+W16f (child->busC!= &pcie_port_bus_A_4,	u+7W	continue;	X1Md hpt36=6child->drhpt3;_UM	6f (d hpt3	 NX	X		Mserv in_d hpt3 =6to_serv in_d hpt3(drhpt3	;_U1	
6f (serv in_d hpt3->remove) X	X		MMserv in_d hpt3->remove(to_dcie_	ic in(child));eU1	}e+7W6/(MAAuptMmod= = (to_dcie_	ic in(child))->inDMAAuptMmod=;	X		put_	ic in(child)21X1Mdev in_unrAUTODMA(child)21X1}_-hE-/* Switch0to INTx5by _},ault	if MSI ena_MWd DMA-	6f (deA->inDMAAuptMmod= == PCIE_PORT_MSIX_MODE)e)NMdci_disa_MW_msix(	eA->dort-21-+-	{e 6f (deA->inDMAAuptMmod= == PCIE_PORT_MSI_MODE)e)NMdci_disa_MW_msi(	eA->dort-21-+put_	ic in(dar.
-);_U1dev in_unrAUTODMA(dar.
-);_+M6f (inDMAAuptMmod= == PCIE_PORT_MSIX_MODE)e+NMdci_disa_MW_msix(	eA);_+M-	{e 6f (inDMAAuptMmod= == PCIE_PORT_MSI_MODE)e+NMdci_disa_MW_msi(	eA-21{}9 aE80825pcie_port_bus_rAUTODMA(8082)u8{R_Mbus_rAUTODMA(&pcie_port_bus_A_4,	;_U1d hpt3_rAUTODMA(&pcieport_generic_d hpt3	21{}9 aE80825pcie_port_bus_unrAUTODMA(8082)u62	
-d hpt3_unrAUTODMA(&pcieport_generic_d hpt3	21{	bus_unrAUTODMA(&pcie_port_bus_A_4,	;_{}9 a	0x06814esctive tim.pci/pcie/portdrv_pci.c,btive tim.pci/pcie/portdrv_pci.c= ht_h"TA6S};sepci/pcie/portdrv_pci.c0d0anDD1-14 15:07:350p		.e		evice_t hpt366pci/pcie/portdrv_pci.c0d0anDD2-02 22341:40hp		.e		(w,
63,34 +63,18
x068XFic ineF80825dcie_portdrv_rAmove (s,		0x0dci_	ic	*F%Aeu62	
-s,		0x0dcie_	ic in6*dcieF%A;	-
-8888881dcieF%A	= (s,		0x0dcie_	ic in6*)dci_gTO_drvsi_d(F%A-21-+6f (dcieF%A) Ne)NMdcie_port_	ic in_rAmove(dcieF%A);e)NMdci_sTO_drvsi_d(F%A	 0,	0-2 	-1} +	dcie_port_	ic in_rAmove(	eA-21{}9 aE0i,_}, CONFIG_PM1E80D-/mLinx0pcie_portdrv_suspend (s,		0x0dci_	ic	*F%A	 A32 	#dte)u62	
-s,		0x0dcie_	ic in6*dcieF%A;	-	
-8888881dcieF%A	= (s,		0x0dcie_	ic in6*)dci_gTO_drvsi_d(F%A-21-+6f (dcieF%A) e)NMdcie_port_	ic in_suspend(dcieF%A, 	#dte);e-1{	/* 2 0;	+1{	/* 2 dcie_port_	ic in_suspend(F%A, 	#dte);e{}9 aE80D-/mLint5dcie_portdrv_rA_ume (s,		0x0dci_	ic	*F%Aeu62	
-s,		0x0dcie_	ic in6*dcieF%A;	-	
-8888881dcieF%A	= (s,		0x0dcie_	ic in6*)dci_gTO_drvsi_d(F%A-21-+6f (dcieF%A) e)NMdcie_port_	ic in_rA_ume(dcieF%A);e)N{	/* 2 0;	+1{	/* 2 dcie_port_	ic in_rA_ume(	eA-21{}9 ,c62	}	ta	0x06814esctive tim.pci/probW.c,btive tim.pci/probW.c= ht_h"TA6S};sepci/probW.c0d0anDD1-14 15:06:550p		.e		evice_t hpt366pci/probW.c0d0anDD2-02 22342:24 -		.e		(w,
879x26+879x26x068XF	6f (dci_find_bus(dci_	omain_nr(b),0bus)	 86231/* If we,aleaady got0to this bus5through a 	0x0er.
-	bridge, ignore i-	*/e-		DBG("PCI: Bus5%04:%02x,aleaady known\n", dci_	omain_nr(b),0bus);R+W1DBG("PCI: Bus5%04x:%02x,aleaady known\n", dci_	omain_nr(b),0bus);R231goto,MAA_out;687+	}		TOD_add_tail(&b->nod=,8&dci_eoot_bus,s)0		0x06814esctive tim.pci/quirks.Ee 2or 9s	{	pci/quirks.E= ht_h"TA6S};sepci/quirks.E0d0anDD1-10 		.52s27hp		.e		evice_t hpt366pci/quirks.E0d0anDD2-02 22342:20hp		.e		(w,
216},
+216,16

-	{DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_2, 	quirk_natoma );	X68/*
+ *  This chip Aan Eaus, PCI darity,MAAors 6f ER_PIOcrAUTODMA 0xA0 is eaad
+ *  1c829 DMAs ar. occurring.
+ */++ic ineF80825__	ic ni-	quirk_citrine(s,		0x0dci_	ic	*F%Aeu+{	+W	eA->cfg_sizeC- 0xA0;	{}eaDECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine );	+	+/*
  *  S3 868	and 968	chips eadort rAUTon5size equal to 32M, but they _}code 64M.
  *  If it's neA_ed, rA-al			a_= t acrAUTon.68FDMA	0x06814esctive tim.pcmcictis.Ee 2or 9s	{	pcmcictis.E= ht_h"TA6S};sepcmcictis.E0d0anDD1-11 16:43:090p		.e		evice_t hpt366pcmcictis.E0d0anDD2-04 17:23:03hp		.e		(w,
660},
+660},
x068	NMd_F%A	= pcmcic_gTO_dec(d_F%A	;_U1	
6f (!d_F%A		X		MMcontinue;	)NM	6f ((!d_F%A->cli.
-.	#dte & CLIENT_UNBOUNDe ||6+1	
6f (!(d_F%A->cli.
-.	#dte & CLIENT_UNBOUNDe ||68		,8888(!d_F%A->F%A.4 hpt3)	 86231		pcmcic_put_	ic(d_F%A	;_U1	
Mcontinue;		0x06814esctive tim.pcmcicti82365.Ee 2or 9s	{	pcmcicti82365.E= ht_h"TA6S};sepcmcicti82365.E0d0anDD1-,5 13:50:250p		.e		evice_t hpt366pcmcicti82365.E0d0anDD2-03 06:42:43hp		.e		(w,
208},
+208}7,ER_U3_},
-	eIS_UNKNOWN	0x0400	U3_},
-	eIS_VG_PWR	0x0800	U3_},
-	eIS_DF_PWR	0x1000	+0_},
-	eIS_REGISTERED	0x2000	U3_},
-	eIS_ALIVE	0x8000	X68A_4,_}, s,		0x0dcic_t62	(w,
1403,120+1404ie22
-	{,8888socket[i].socket.easource	ops	= &pccard_nonic ine	ops;	{,8888socket[i].socket.ownt3 =6THIS_MODULE;	{,8888socket[i].numbt3 =6i;6-1888 {	/	= pcmcic_rAUTODMA_socket(&socket[i].socket);1888 6-1888 6f ({	/	&& i--- 86-	,8888* 4 (; i>= 0; i----
-	,8888pcmcic_unrAUTODMA_socket(&socket[i].socket);6-	,8888break;	-1888 }_x1888 {	/	= pcmcic_rAUTODMA_socket(&socket[i].socket);_x1888 6f (!{	/)e+NM8888socket[i].*6514	|= IS_REGISTERED;	+	X0i, 0 /* d hpt3 mod=l ordering issu, */	X	888class_	ic in_ceaata_file(&socket[i].socket.42		s81	,  {,8888&class_	ic in_attr_i
fo-21(w,
1435},
+1434x8FER_U888 6nx0i;	X688888* 4 (i = 0; i < sockets; i+1) 86-,8888pcmcic_unrAUTODMA_socket(&socket[i].socket);6x1888 6f (socket[i].*6514	& IS_REGISTERED)e+NM8888pcmcic_unrAUTODMA_socket(&socket[i].socket);6 888 }_ 888 plat* 4m_dev in_unrAUTODMA(&i82365_F%A in-21 888 6f (poll_inDMAval	!={0)		0x06814esctive tim.pcmcictm32r_cfc.Ee 2or 9s	{	pcmcictm32r_cfc.E= ht_h"TA6S};sepcmcictm32r_cfc.E0d0anDD1-,5 13:50:250p		.e		evice_t hpt366pcmcictm32r_cfc.E0d0anDD2-03 06:42:44 -		.e		(w,
239,665239,26x068XF/*====================================================================*/	 1+0_},
-	eIS_REGISTERED		0x2000	U3_},
-	eIS_ALIVE		0x8000	X68A_4,_}, s,		0x0dcc_t62	(w,
835}11 +836,90x148MMsocket[i].socket.ownt3 =6THIS_MODULE;	{,	socket[i].numbt3 =6i;6 1	{	/	= pcmcic_rAUTODMA_socket(&socket[i].socket);_)NM6f ({	/	&& i--- 86-	,	* 4 (; i>= 0; i----
-	,	pcmcic_unrAUTODMA_socket(&socket[i].socket);6-	,	break;	-1	}e+7W6f (!{	/)e+NM	socket[i].*6514	|= IS_REGISTERED;	+	X0i, 0	/* d hpt3 mod=l ordering issu, */	X		class_	ic in_ceaata_file(&socket[i].socket.42		s81	,NM8&class_	ic in_attr_i
fo-21(w,
865},
+864x8FER_U	6nx0i;	X68W* 4 (i = 0; i < dcc_sockets; i+1)e)NMdcmcic_unrAUTODMA_socket(&socket[i].socket);6x1	6f (socket[i].*6514	& IS_REGISTERED)e+NMMdcmcic_unrAUTODMA_socket(&socket[i].socket);6X68Wplat* 4m_dev in_unrAUTODMA(&dcc_F%A in-21 	6f (poll_inDMAval	!={0)		0x06814esctive tim.pcmcictm32r_dcc.Ee 2or 9s	{	pcmcictm32r_dcc.E= ht_h"TA6S};sepcmcictm32r_dcc.E0d0anDD1-,5 13:50:250p		.e		evice_t hpt366pcmcictm32r_dcc.E0d0anDD2-03 06:42:44 -		.e		(w,
257,665257,26x068XF/*====================================================================*/	 1+0_},
-	eIS_REGISTERED		0x2000	U3_},
-	eIS_ALIVE		0x8000	X68A_4,_}, s,		0x0dcc_t62	(w,
772}11 +773,90x148MMsocket[i].socket.ownt3 =6THIS_MODULE;	{,	socket[i].numbt3 =6i;6 1	{	/	= pcmcic_rAUTODMA_socket(&socket[i].socket);_)NM6f ({	/	&& i--- 86-	,	* 4 (; i>= 0; i----
-	,	pcmcic_unrAUTODMA_socket(&socket[i].socket);6-	,	break;	-1	}e+7W6f (!{	/)e+NM	socket[i].*6514	|= IS_REGISTERED;	+	X0i, 0	/* d hpt3 mod=l ordering issu, */	X		class_	ic in_ceaata_file(&socket[i].socket.42		s81	,NM8&class_	ic in_attr_i
fo-21(w,
802},
+801}8Fx068	6nx0i;	X68W* 4 (i = 0; i < dcc_sockets; i+1)e)NMdcmcic_unrAUTODMA_socket(&socket[i].socket);6x1	6f (socket[i].*6514	& IS_REGISTERED)e+NMMdcmcic_unrAUTODMA_socket(&socket[i].socket);6X68Wplat* 4m_dev in_unrAUTODMA(&dcc_F%A in-21 	6f (poll_inDMAval	!={0)		0x06814esctive tim.pnp.pnpbios/core.Ee 2or 9s	{	pnp.pnpbios/core.E= ht_h"TA6S};sepnp.pnpbios/core.E0d0anDD1-30 21:12:330p		.e		evice_t hpt366pnp.pnpbios/core.E0d0anDD2-03 06:42:38hp		.e		(w,
61,66561},
x0680incluF% <6___A/spin			k.h>_A0incluF% <6___A/dmi.h>_A0incluF% <6___A/delay.h>_+0incluF% <6___A/acpi.h>_A_A0incluF% <asm/dage.h>_A0incluF% <asm/desc.h>_(w,
539,26+540},
ER_U1}9 aE0i,_}, CONFIG_PNPACPI1-+-xDMAnlinx0pnpacpi_disa_MWdR_F	6f (!acpi_disa_MWd	&& !pnpacpi_disa_MWd	 86231pnpbios_disa_MWd	=/1;	}1	pr"Mak(KERN	INFO "PnPBIOS: Disa_MWd	by ACPI PNP\n")0		0x06814esctive tim.s390/b			k/dasd.Ee 2or 9s	{	s390/b			k/dasd.E= ht_h"TA6S};ses390/b			k/dasd.E0d0anDD1-15 14:01:580p		.e		evice_t hpt366s390/b			k/dasd.E0d0anDD2-03 06:42:42hp		.e		(w,
7x26+7},
x068FD Bugeadorts.to..: <L___A390@de.ibm.com>68FD (C) IBM Cordora1ion, IBM Deutschland Entwicklung GmbH, 1999
200168FD
-FD $R%A 6ion: 1.154 $
+ * $R%A 6ion: 1.156 $
 ,DMAE
 0incluF% <6___A/ER_PIO.h>_(w,
179x26+179x26x068M	eA in->4%bug_aeaa	= 	ibug_rAUTODMA(	eA in->cF%A->F%A.bus_82	 0, 2	s81	,NM88888 * sizeof (},
-)e21X1debug_rAUTODMA_view(	eA in->4%bug_aeaa, &d%bug_spr"Maf_view);_U1debug_set_le0xl(	eA in->4%bug_aeaa, DBF	DEBUG);	+Mdebug_set_le0xl(	eA in->4%bug_aeaa, DBF	EMERG);eU1DBF	DEV_EVENT(DBF	EMERG, dev in, "%s", "4%bug aeaa	ceaata7");	}	23dev in->ic ieC- DASD_STATE_BASIC0	(w,
745}8F+745}90x148Mswitch0(rc	 Ne{	case 0:	X		cqA->ic ius	= DASD_CQR	IN_IO;e-		DBF	DEV_EVENT(DBF	DEBUG, dev in, "%s",-
-	,888888"ic rt_IO: request %p ic rtWd	successful");R+W1DBF	DEV_EVENT(DBF	DEBUG, dev in,e+NMM888888"ic rt_IO: request %p ic rtWd	successful",e+NMM888888cqA	;_U1	break;	{	case -EckSY:	X		DBF	DEV_EVENT(DBF	ERR, dev in, "%s",-(w,
1579x250+1580,2,

-	{}68XF/D
-FD Al			a_= and initializeCrequest queue.
+ * Al			a_= and initializeCrequest queue and _},ault	I/O scheduler.68FDMAEic ineF"Ma
 dasd_al			_queue(s,		0x0	asd_	ic in6* dev in)9 {	+W1		. c;F+e{	42	 in->request_queue6=6blk_	nit_queue(do_	asd_request	s81	,NM8888888&42	 in->request_queue-O_4k-21 	6f (42	 in->request_queue6== 0,	0-	{		{	/* 2 -ENOMEM;	 e{	42	 in->request_queue->queuesi_d6=6F%A in;_)0i, 0F+e{	ele0a14e_exit(42	 in->request_queue->ele0a14eER_MW{c = ele0a14e_	nit(42	 in->request_queue, "noop"ER_+	{c = ele0a14e_	nit(42	 in->request_queue, "deadlMA_"-21 	6f (rc	 Ne{		blk_cleanup_queue(d2	 in->request_queue);	{		{	/* 2  c;FE1}_-,c62	}	tW{	/* 2 0;	68_A+(w,
1963x2651965},
x068	Ngoto,faiMWdR_F	}1X1debug_rAUTODMA_view(	asd_	ibug_aeaa, &d%bug_spr"Maf_view);_U1debug_set_le0xl(	asd_	ibug_aeaa, DBF	DEBUG);	+Mdebug_set_le0xl(	asd_	ibug_aeaa, DBF	EMERG);eUeU1DBF	EVENT(DBF	EMERG, "%s", "4%bug aeaa	ceaata7");	}		0x06814esctive tim.s390/cio/cio.Ee 2or 9s	{	s390/cio/cio.E= ht_h"TA6S};ses390/cio/cio.E0d0anDD1-03 15:49:38hp		.e		evice_t hpt366s390/cio/cio.E0d0anDD2-03 06:42:43hp		.e		(w,
175}90+175}e22
-	{}68XFinx
-cio_ic rt (s,		0x0subchann=l *sch,	8exsubchann=l s,		0xure	*/e-	888s,		0x0ccw16* cpa,7	8exlogical chann=l prog addrC*/e-	888__u8 lpm)	7	8exlogical path mask */++cio_ic rt_key (s,		0x0subchann=l *sch,	8exsubchann=l s,		0xure	*/e+M8888888s,		0x0ccw16* cpa,78exlogical chann=l prog addrC*/e+M8888888__u8 lpm,7	8exlogical path mask */++M8888888__u8 key)                8exs14eage key DMAENe{	c_PCIdbf_txt[15];stW1		.ccod=;	(w,
200,120+201}120x148Msch->orb.c64	=/1;	}1sch->orb.i2k	= 0;	},c62	}	+1sch->orb.key = key >> 4;ea7/* issu, "Sc rt Subchann=l" */	X	sch->orb.cpd6=6(__u32)8__pd6(cpd-21-hpt/D
-	6* Issu, "Sc rt subchann=l" and process ER_di1ion cod=
-	6*/	X	ccod=	= ssch0(sch->irq, &sch->orb);eaea7/* process ER_di1ion cod= */	X	spr"Maf (4bf_txt, "ccod=:%d",5ccod=);	{	CIO_TRACE	EVENT (4,Idbf_txt);	}	(w,
222,665223,120x148M_},ault:7	8exd2	 in/path not opera1ional */	X		{	/* 2 cio_ic rt_handln_notoper(sch, lpm)R_F	}1{}eaeainx
+cio_ic rt (s,		0x0subchann=l *sch,8s,		0x0ccw16*cpa,8__u8 lpm)u+{	+W{	/* 2 cio_ic rt_key(sch, cpa,8lpm, _},ault_s14eage_key);e{}9 aE/D
	0x06814esctive tim.s390/cio/cio.hce_t hpt366s390/cio/cio.h= ht_h"TA6S};ses390/cio/cio.h0d0a4-08-07 11:05:350p	7.e		evice_t hpt366s390/cio/cio.h0d0anDD2-03 06:42:43hp		.e		(w,
122,665122,7
ER_UexDMAnl1		.cio_rA_ume (s,		0x0subchann=l *e21UexDMAnlinx0cio_halt (s,		0x0subchann=l *e21UexDMAnlinx0cio_ic rt (s,		0x0subchann=l *,8s,		0x0ccw16*,8__u8);e+exDMAnlinx0cio_ic rt_key (s,		0x0subchann=l *,8s,		0x0ccw16*,8__u8,8__u8);eUexDMAnlinx0cio_canc=l (s,		0x0subchann=l *e21UexDMAnlinx0cio_iet_op1ions (s,		0x0subchann=l *,8i
-);_UexDMAnlinx0cio_get_op1ions (s,		0x0subchann=l *)0		0x06814esctive tim.s390/cio/dev in_ops.Ee 2or 9s	{	s390/cio/dev in_ops.E= ht_h"TA6S};ses390/cio/dev in_ops.E0d0a4-08-07 11:05:360p	7.e		evice_t hpt366s390/cio/dev in_ops.E0d0anDD2-03 06:42:43hp		.e		(w,
1x2651,7
ER_U/*
  *  or 9s	{	s390/cio/dev in_ops.E=8FD
-FD   $R%A 6ion: 1.50 $
+ *   $R%A 6ion: 1.53 $
 ,D
  *    Copyright (C) d0a2 IBM Deutschland Entwicklung GmbH,
  *,NM8IBM Cordora1ion	(w,
54,66554},
x06816f (c	eA->dr 9ata->ic ieC-= DEV_STATE_NOT_OPER-	{		{	/* 2 -ENODEV;6816f (c	eA->dr 9ata->ic ieC!= DEV_STATE_ONLINE &&-+-8888c	eA->dr 9ata->ic ieC!= DEV_STATE_WAIT4IO &&- -8888c	eA->dr 9ata->ic ieC!= DEV_STATE_W4SENSE-	{		{	/* 2 -EINVAL;687sch0=6to_subchann=l(cF%A->F%A.dar.
-);_(w,
66,8
+67,90x148}68XFinx
-ccw_	ic in_sc rt(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6-	,816814ea7	},
-	inxdarm,8__u8 lpm,816814ea7	},
-	*6514)u+ccw_	ic in_sc rt_key(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6+NM8888816814ea7	},
-	inxdarm,8__u8 lpm,8__u8 key,6+NM8888816814ea7	},
-	*6514)u8{R_Ms,		0x0subchann=l *sch;stW1		. et21(w,
87}290+89,49

-	{	{	/6=6cio_iet_op1ions (sch, *6514)21 	6f (r	/)e{		{	/* 2  et21-	{	/6=6cio_ic rt (sch, cpa,8lpm-21++{	/6=6cio_ic rt_key (sch, cpa,8lpm, key);e{M6f ({	/	== 0-	X		c	eA->dr 9ata->inxdarm = V/xdarm;	{	366_chi et218}68X+XFinx
-ccw_	ic in_sc rt_timeout(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6-	,,816814ea7	},
-	inxdarm,8__u8 lpm,816814ea7	},
-	*6514,6-	,,81		.expire4)u+ccw_	ic in_sc rt_timeout_key(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6+NMM8888816814ea7	},
-	inxdarm,8__u8 lpm,8__u8 key,6+NMM8888816814ea7	},
-	*6514,81		.expire4)u8{R_M6		. et218_F	6f (!cF%A		X		{	/* 2 -ENODEV;681ccw_	ic in_set_timeout(cF%A,lexpire4)21-	{	/6=6ccw_	ic in_sc rt(cF%A,lcpa,8inxdarm,8lpm,8*6514)21+	{	/6=6ccw_	ic in_sc rt_key(cF%A,lcpa,8inxdarm,8lpm,8key, *6514)21 	6f (r	/	!={0)	X		ccw_	ic in_set_timeout(cF%A,l0);	{	366_chi et218}68X inx
+ccw_	ic in_sc rt(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6+	,816814ea7	},
-	inxdarm,8__u8 lpm,816814ea7	},
-	*6514)u+{	+W{	/* 2 ccw_	ic in_sc rt_key(cF%A,lcpa,8inxdarm,8lpm,-+-	,18888_},ault_s14eage_key,8*6514)21+}eaeainx
+ccw_	ic in_sc rt_timeout(s,		0x0ccw_	ic in6*cF%A,l0,		0x0ccw16*cpa,6+	,,816814ea7	},
-	inxdarm,8__u8 lpm,816814ea7	},
-	*6514,6+	,,81		.expire4)u+{	+W{	/* 2 ccw_	ic in_sc rt_timeout_key(cF%A,lcpa,8inxdarm,8lpm,-+-	,118888_},ault_s14eage_key,8*6514,-+-	,118888expire4)21+}eaeaeainx
 ccw_	ic in_halt(s,		0x0ccw_	ic in6*cF%A,l16814ea7	},
-	inxdarm)u8{R_Ms,		0x0subchann=l *sch;s(w,
120,665142},
x06816f (c	eA->dr 9ata->ic ieC-= DEV_STATE_NOT_OPER-	{		{	/* 2 -ENODEV;6816f (c	eA->dr 9ata->ic ieC!= DEV_STATE_ONLINE &&-+-8888c	eA->dr 9ata->ic ieC!= DEV_STATE_WAIT4IO &&- -8888c	eA->dr 9ata->ic ieC!= DEV_STATE_W4SENSE-	{		{	/* 2 -EINVAL;687sch0=6to_subchann=l(cF%A->F%A.dar.
-);_(w,
539,665562}8Fx068EXPORT_SYMBOL(ccw_	ic in_rA_ume);	{EXPORT_SYMBOL(ccw_	ic in_sc rt_timeout);	{EXPORT_SYMBOL(ccw_	ic in_sc rt)21+EXPORT_SYMBOL(ccw_	ic in_sc rt_timeout_key);e+EXPORT_SYMBOL(ccw_	ic in_sc rt_key);e{EXPORT_SYMBOL(ccw_	ic in_gTO_ciw);e{EXPORT_SYMBOL(ccw_	ic in_gTO_path_mask);e{EXPORT_SYMBOL(eaad_ER_P_si_d)0		0x06814esctive tim.s390/net/qeth.hce_t hpt366s390/net/qeth.h= ht_h"TA6S};ses390/net/qeth.h0d0anDD1-03 15:49:39hp		.e		evice_t hpt366s390/net/qeth.h0d0anDD2-03 06:42:43hp		.e		(w,
24},
+24},
x068XF0incluF% "qeth_mpc.h"	8X-3_},
-	eVERSION_QETH_H{		"$R%A 6ion: 1.1290$"	+0_},
-	eVERSION_QETH_H{		"$R%A 6ion: 1.1320$"	 aE0i,_}, CONFIG_QETH_IPV6	U3_},
-	eQETH_VERSION_IPV6 	":IPv6"	(w,
754,6 +754x8FER_U	s,		0x0qeth_perf_s,ats perf_s,ats;	},c62	} 8exCONFIG_QETH_PERF_STATS */	X	1		.usn_hard_s14p0	+Minx0(*orig_hard_h	ader)(s,		0x0sk_bux06*,s,		0x0nTO_dec in6*,-+-	,116814ea7	short,80825*,80825*,16814ea7);e{};9 aE80		0x0qeth_card_	TOD_80		0x02	(w,
828},
+830}1,
x068,c62	}	tW}18}6+80D-/mLinlMA_Fs,		0x0sk_bux06*
+qeth_pskb_168hare(s,		0x0sk_bux06*skb,81		.dr )u+{	+ 8888888s,		0x0sk_bux06*nskb;	+ 88888886f (!skb_c},
ed(skb)-	{                {	/* 2 skb;	+ 8888888nskb	= skb_copy(skb,8dr );	+ 8888888kfr	=_skb(skb); 8exfr	=	our 8hared copy */++        {	/* 2 nskb;	+}eae8X inlMA_Fs, ineF"Ma
 qeth_gTO_initial_mtu_for_card(80		0x0qeth_card6* card)	(w,
1071}8F+1084,4
ER_UexDMAnl1		
 qeth_eaal			_bux0er_pool(80		0x0qeth_card6*,8i
-);_Ue-exDMAnlinx
-qeth_fake_h	ader(s,		0x0sk_bux06*skb,8s,		0x0nTO_dec in6*42		s-                 16814ea7	short A_4,, 80825*daddr, 80825*saddr,6-	,816814ea7	}en);	},c62	} 8ex__QETH_H__FDMA	0x06814esctive tim.s390/net/qeth_main.Ee 2or 9s	{	s390/net/qeth_main.E= ht_h"TA6S};ses390/net/qeth_main.E0d0anDD1-17 13:13:31hp		.e		evice_t hpt366s390/net/qeth_main.E0d0anDD2-03 06:42:43hp		.e		(w,
1x6651},
ER_U/*
  *
-FD 6___A/dve tim.s390/net/qeth_main.Ee($R%A 6ion: 1.181 $)
+ * 6___A/dve tim.s390/net/qeth_main.Ee($R%A 6ion: 1.191 $)
 ,D
  * L___A on zSeri,s OSA Express and HiperSockets0supdort
 ,D
(w,
12x26512},
x068FD,1188Frank PavlneF(pavlne@de.ibm.com) and68FD,1 -88Thomas Spatzier <tspat@de.ibm.com>68FD
-FD    $R%A 6ion: 1.181 $	 $D ie: d0a4/12/27 07:36:40h$
+ *    $R%A 6ion: 1.191 $	 $D ie: d0a5/01/31h13:13:57 $
 ,D
  * This program is fr	=	software; you Aan redTODribute i-	and/o3 modify
  * i-	under t acDMAms of * acGNU General PublneFL innse as publnshWd	by	(w,
41,16
+41,9
x0680incluF% <6___A/ER_PIO.h>_80incluF% <6___A/module.h>_80incluF% <6___A/moduleparam.h>_-680incluF% <6___A/string.h>_80incluF% <6___A/errno.h>_80incluF% <6___A/mm.h>_-6-0incluF% <asm/io.h>_-0incluF% <asm/ebcdic.h>_-0incluF% <6___A/EA_4,.h>_-0incluF% <asm/semaphore.h>_-0incluF% <asm/timex.h>_80incluF% <6___A/ip.h>_80incluF% <6___A/inetF%A in.h>_80incluF% <6___A/netF%A in.h>_(w,
62,23 +55}290x0680incluF% <6___A/tcp.h>_80incluF% <6___A/icmp.h>_80incluF% <6___A/skbux0.h>_-0incluF% <net/route.h>_-0incluF% <net/arp.h>_80incluF% <6___A/in.h>_80incluF% <6___A/igmp.h>_-0incluF% <net/ip.h>_-0incluF% <asm/uaccess.h>_80incluF% <6___A/init.h>_80incluF% <6___A/re	XFE.h>_-0incluF% <asm/qeth.h>_80incluF% <6___A/mii.h>_A0incluF% <6___A/rcupsi_n.h>_8_+0incluF% <net/arp.h>_+0incluF% <net/ip.h>_+0incluF% <net/route.h>_+_+0incluF% <asm/ebcdic.h>_+0incluF% <asm/io.h>_+0incluF% <asm/qeth.h>_+0incluF% <asm/timex.h>_+0incluF% <asm/semaphore.h>_+0incluF% <asm/uaccess.h>_+XF0incluF% "qeth.h"	80incluF% "qeth_mpc.h"	80incluF% "qeth_fs.h"	8X-3_},
-	eVERSION_QETH_C "$R%A 6ion: 1.181 $"	+0_},
-	eVERSION_QETH_C "$R%A 6ion: 1.191 $"	Fs, ineFconic	W_PCI_ timion = "qeth S/390 OSA-Express dve ti";	X68/*D
(w,
514,665513},
x068qeth_iet_offline(s,		0x0ccwgroup_	ic in6*cgF%A-u8{R_Ms,		0x0qeth_card6*card6= (s,		0x0qeth_card6*) cgF%A->F%A.4 hpt3_si_d;	+W1		. c	= 0;	}	enum0qeth_card_ic ies eacopt3_*651218_F	QETH_DBF	TEXT(setup, 3, "setoffl");_(w,
525,1565525,21

-	{	11888CARD_BUS_ID(card));	{		{	/* 2 -ERESTARTSYS;48M}	-	ccw_	ic in_set_offline(CARD_DDEV(card));	-	ccw_	ic in_set_offline(CARD_WDEV(card));	-	ccw_	ic in_set_offline(CARD_RDEV(card));	+M6f (({c = ccw_	ic in_set_offline(CARD_DDEV(card))e ||6+18888({c = ccw_	ic in_set_offline(CARD_WDEV(card))e ||6+18888({c = ccw_	ic in_set_offline(CARD_RDEV(card))Ee Ne+NMQETH_DBF	TEXT_(setup, 2, "1err%d",5rc);	+M}1 	6f (r	copt3_*651C-= CARD_STATE_UP)	X		card->ic ieC- CARD_STATE_RECOVER;48Mqeth_notify_processes();	{	366_chi0;	68_A++odma	= _nt
+qeth_wait_for_theaads(s,		0x0qeth_card6*card,l16814ea7	},
-	theaads);eaeaXFic ineF8082
 qeth_eamove_	ic in(s,		0x0ccwgroup_	ic in6*cgF%A-u8{R(w,
546},
+552}90x148M6f (!card)	{		{	/* 2R_ 	+W6f (qeth_wait_for_theaads(card,l0xffffffff))++	1{	/* 2;F+e{	6f (cgF%A->ic ieC-= CCWGROUP_ONLINE){	X		card->usn_hard_s14p	=/1;	}1	qeth_iet_offline(cgF%A-;_(w,
621x265630},
x06816f (todo->usnrs > 0)86231/* * 4 VIPA and RXIP 6_mi	. efcount0to 1 */	X		6f (todo->A_4, != QETH_IP_TYPE_NORMAL--
-	,addr->usnrs =i1;	{	1	todo->usnrs =/1;	}1	366_chi1;	8	} -	{e- 	-366_chi0;	(w,
2262}8F+2271}8Fx068		skb->ip_summWd	=/CHECKSUM_NONE;aE0i,_}, CONFIG_QETH_VLAN6816f (hdr->hdr.l2.*6514[2] & (QETH_LAYER2_FLAG_VLAN)e Ne)NMskb_pull(skb,8VLAN_HLEN);	{		vlan_6d	= hdr->hdr.l2.vlan_6d;	{	1skb_pull(skb,8VLAN_HLEN);	{	}9 ,c62	}	t	skb->protocol	= qeth_A_4,_trans(skb,8skb->F%A-;_(w,
3262}e3 +3271}156x068XF	QETH_DBF	TEXT(trace,3,"qdioclr"-21 	6f (card->qdio.ic ieC-= QETH_QDIO_ESTABLISHED)Ne)NMqdio_cleanup(CARD_DDEV(card),6x1	6f (({c = qdio_cleanup(CARD_DDEV(card),68		,8888 (card->i
fo.A_4,	== QETH_CARD_TYPE_IQD) ?68		,8888 QDIO_FLAG_CLEANUP_USING_HALT :-
-	,88888QDIO_FLAG_CLEANUP_USING_CLEAR);R+W1,88888QDIO_FLAG_CLEANUP_USING_CLEAR))-	{	1	QETH_DBF	TEXT_(trace, 3, "1err%d",5rc);	X		card->qdio.ic ieC- QETH_QDIO_ALLOCATED;48M}	-	{c = qeth_clear_halt_card(card,l1sn_halt);	+M6f (({c = qeth_clear_halt_card(card,l1sn_halt))-	{	1QETH_DBF	TEXT_(trace, 3, "2err%d",5rc);	X	card->ic ieC- CARD_STATE_DOWN;	{	366_chi c;	68_(w,
3370,6653381,2,

-	{	366_chiF%A;	68_A++/*hard_h	ader fakexfunc1ion;l1snd in case fake_ll is set */e+odma	= _nt
+qeth_fake_h	ader(s,		0x0sk_bux06*skb,8s,		0x0nTO_dec in6*42		s+NM8888816814ea7	short A_4,, 80825*daddr, 80825*saddr,6+NM8888816814ea7	}en)u+{	+Ws,		0x0ethhdrC*hdr;6+7s,		0x0qeth_card6*card;eaea7card6= (s,		0x0qeth_card6*)	eA->dr 9;	+ 8888888hdrC= (s,		0x0ethhdrC*)skb_push(skb,8QETH_FAKE_LL_LEN);	+Mmemcpy(hdr->h_source, card->F%A->F%A_addr, ETH_ALEN);	+ 8888888memcpy(hdr->h_dest	 "FAKELL", ETH_ALEN);	+ 88888886f (t_4, != ETH_P_802_3-	{                hdr->h_proto	= htoni(A_4,	;_{        -	{e-{                hdr->h_proto	= htoni(}en);	+W{	/* 2 QETH_FAKE_LL_LEN;	+}eae880D-/mLinlMA_F-		68qeth_iend_packet(80		0x0qeth_card6*,8s,		0x0sk_bux06*);	}	(w,
3399,6653430}14

-	{	card->perf_s,ats.outbound_cnt++R_{	card->perf_s,ats.outbound_sc rt_time = qeth_gTO_micros();	{,c62	}	+16f (deA->hard_h	ader == qeth_fake_h	adere Ne+               6f ((skb	= qeth_pskb_168hare(skb,8GFP_ATOMIC))	== 0,	0- Ne+                        card->ic is.tx_dropped++R_+                        F%A_kfr	=_skb_irq(skb);_+                        {	/* 2 0;	+                }	+                skb_pull(skb,8QETH_FAKE_LL_LEN);	+M}hE-/*- -8* We only call0nTOif_s14p_queue6in case of,MAAors. Since we've- -8* got0our own synchroniza1ion on queues we,Aan keep * acic ck's_(w,
5219,26+5258}e22
-	{
Fs, ineF"Ma
 qeth_layer2_iend_setF%lmac(s,		0x0qeth_card6*card,l__u8 *mac,-
-	,888enum0qeth_ipa_cmds ipacmd)R+W1,888enum0qeth_ipa_cmds ipacmd,6+NMM888inx0(*reply_cb) (s,		0x0qeth_card6*,-+-	,118888s,		0x0qeth_reply*,-+-	,11888816814ea7	},
-)-u8{R_Ms,		0x0qeth_ipa_cmd6*cmd;	}	0,		0x0qeth_cmd_bux0er *iob;_(w,
5229}90+5271}1390x148Mcmd6= (s,		0x0qeth_ipa_cmd6*)(iob->Fi_d+IPA_PDU_HEADER_SIZE-21 888     cmd->Fi_d.setF%lmac.mac	length0=6OSA_ADDR_LEN;	  8888888memcpy(&cmd->Fi_d.setF%lmac.mac, mac, OSA_ADDR_LEN);e)N{	/* 2 qeth_iend_ipa_cmd(card,liob	 0,	0,50,	0-21+N{	/* 2 qeth_iend_ipa_cmd(card,liob	 reply_cb,50,	0-21+}eaea+#defininx
+qeth_layer2_iend_setgroupmac	cb(s,		0x0qeth_card6*card,-+-	,1s,		0x0qeth_reply *reply,-+-	,116814ea7	},
-	si_d)u+{	+Ws,		0x0qeth_ipa_cmd6*cmd;	+	__u8 *mac;eaea7QETH_DBF	TEXT(trace, 2, "L2Sgmacb"ER_+	cmd6= (s,		0x0qeth_ipa_cmd6*) si_d;	+Wmac	= &cmd->Fi_d.setF%lmac.mac[0];ea7/* MAC,aleaady rAUTODMAed, neA_ed6in couple/uncouple case */++M6f (cmd->hdr.{	/* 2_cod= == 0x2005e Ne+NMPRINT_WARN("Group MAC,%02x:%02x:%02x:%02x:%02x:%02x " \6+NMM88"aleaady exTODing on %s \n",6+NMM88mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],6+NMM88QETH_CARD_IFNAME(card));	+M	cmd->hdr.{	/* 2_cod= = 0;	+1}++M6f (cmd->hdr.{	/* 2_cod=)e+NMPRINT_ERR("Could not set group MAC," \6+NMM88"%02x:%02x:%02x:%02x:%02x:%02x on %s: %x\n",6+NMM88mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],6+NMM88QETH_CARD_IFNAME(card),cmd->hdr.{	/* 2_cod=)21+N{	/* 2 021+}eaea+#defininx
+qeth_layer2_iend_setgroupmac(s,		0x0qeth_card6*card,l__u8 *mac)u+{	+WQETH_DBF	TEXT(trace, 2, "L2Sgmac"-21+N{	/* 2 qeth_layer2_iend_setF%lmac(card,lmac, IPA_CMD_SETGMAC,-+-	,1188qeth_layer2_iend_setgroupmac	cb-21+}eaea+#defininx
+qeth_layer2_iend_F%lgroupmac	cb(s,		0x0qeth_card6*card,-+-	,1s,		0x0qeth_reply *reply,-+-	,116814ea7	},
-	si_d)u+{	+Ws,		0x0qeth_ipa_cmd6*cmd;	+	__u8 *mac;eaea7QETH_DBF	TEXT(trace, 2, "L2Dgmacb"ER_+	cmd6= (s,		0x0qeth_ipa_cmd6*) si_d;	+Wmac	= &cmd->Fi_d.setF%lmac.mac[0];ea76f (cmd->hdr.{	/* 2_cod=)e+NMPRINT_ERR("Could not F%leieCgroup MAC," \6+NMM88"%02x:%02x:%02x:%02x:%02x:%02x on %s: %x\n",6+NMM88mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],6+NMM88QETH_CARD_IFNAME(card), cmd->hdr.{	/* 2_cod=)21+N{	/* 2 021+}eaea+#defininx
+qeth_layer2_iend_F%lgroupmac(s,		0x0qeth_card6*card,l__u8 *mac)u+{	+WQETH_DBF	TEXT(trace, 2, "L2Dgmac"-21+N{	/* 2 qeth_layer2_iend_setF%lmac(card,lmac, IPA_CMD_DELGMAC,-+-	,1188qeth_layer2_iend_F%lgroupmac	cb-21+}eaea+#defininx
+qeth_layer2_iend_setmac	cb(s,		0x0qeth_card6*card,-+-	,888s,		0x0qeth_reply *reply,-+-	,88816814ea7	},
-	si_d)u+{	+Ws,		0x0qeth_ipa_cmd6*cmd;	+	+WQETH_DBF	TEXT(trace, 2, "L2Smaccb"ER_+	cmd6= (s,		0x0qeth_ipa_cmd6*) si_d;	+W6f (cmd->hdr.{	/* 2_cod=) Ne+NMQETH_DBF	TEXT_(trace, 2, "L2er%x",5cmd->hdr.{	/* 2_cod=)21+NMPRINT_WARN("EAAor6in rAUTODMAing MAC,address on " \6+NMM88 "4%c in6%s: x%x\n",8CARD_BUS_ID(card),-+-	,888cmd->hdr.{	/* 2_cod=)21+NMcard->i
fo.layer2_mac	rAUTODMAed = 0;	+1	cmd->hdr.{	/* 2_cod= = -EIO;e+N} -	{e 81+NMcard->i
fo.layer2_mac	rAUTODMAed = 1;	{	1memcpy(card->F%A->F%A_addr,cmd->Fi_d.setF%lmac.mac,6+NM88888  OSA_ADDR_LEN);e+NMPRINT_INFO("MAC,address %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "6+NMM88 "successfully rAUTODMAed on 4%c in6%s\n",6+NMM88 card->F%A->F%A_addr[0], card->F%A->F%A_addr[1],6+NMM88 card->F%A->F%A_addr[2], card->F%A->F%A_addr[3],6+NMM88 card->F%A->F%A_addr[4], card->F%A->F%A_addr[5],6+NMM88 card->F%A->F_LO);	+1}++M{	/* 2 021+}eaea+#defininx
+qeth_layer2_iend_setmac(s,		0x0qeth_card6*card,l__u8 *mac)u+{	+WQETH_DBF	TEXT(trace, 2, "L2Setmac"-21+N{	/* 2 qeth_layer2_iend_setF%lmac(card,lmac, IPA_CMD_SETVMAC,-+-	,1188qeth_layer2_iend_setmac	cb-2168_A++odma	= _nt
+qeth_layer2_iend_F%lmac	cb(s,		0x0qeth_card6*card,-+-	,888s,		0x0qeth_reply *reply,-+-	,88816814ea7	},
-	si_d)u+{	+Ws,		0x0qeth_ipa_cmd6*cmd;	+	+WQETH_DBF	TEXT(trace, 2, "L2Dmaccb"ER_+	cmd6= (s,		0x0qeth_ipa_cmd6*) si_d;	+W6f (cmd->hdr.{	/* 2_cod=) Ne+NMPRINT_WARN("EAAor6in derAUTODMAing MAC,address on " \6+NMM88 "4%c in6%s: x%x\n",8CARD_BUS_ID(card),-+-	,888cmd->hdr.{	/* 2_cod=)21+NMQETH_DBF	TEXT_(trace, 2, "err%d",5cmd->hdr.{	/* 2_cod=)21+NMcmd->hdr.{	/* 2_cod= = -EIO;e+NN{	/* 2 0;	+1}ea7card->i
fo.layer2_mac	rAUTODMAed = 0;	+++M{	/* 2 021+}eaodma	= _nt
+qeth_layer2_iend_F%lmac(s,		0x0qeth_card6*card,l__u8 *mac)u+{	+WQETH_DBF	TEXT(trace, 2, "L2D%lmac");	+M6f (!card->i
fo.layer2_mac	rAUTODMAed)e+NN{	/* 2 0;	+1{	/* 2 qeth_layer2_iend_setF%lmac(card,lmac, IPA_CMD_DELVMAC,-+-	,1188qeth_layer2_iend_F%lmac	cb-21+}e{
Fs, ineF"Ma
 qeth_layer2_iet_mac	address(s,		0x0nTO_dec in6*42		 80825*p)_(w,
5256,32655428}90x148M}XF	QETH_DBF	TEXT_(trace, 3, "%s", CARD_BUS_ID(card));	{	QETH_DBF	HEX(trace, 3, addr->sa_si_d, OSA_ADDR_LEN);e)N6f (card->i
fo.layer2_mac	rAUTODMAed)eU1	{c = qeth_layer2_iend_setF%lmac(card,l&card->F%A->F%A_addr[0],-
-	,			IPA_CMD_DELVMAC);e)N6f (rc	 Ne-NMPRINT_WARN("EAAor6in derAUTODMAing MAC,address on " \6-NMM88 "4%c in6%s: x%x\n",8CARD_BUS_ID(card),5rc);	-NMQETH_DBF	TEXT_(trace, 2, "err%d",5rc);	-NM{	/* 2 -EIO);)N}+tWcard->i
fo.layer2_mac	rAUTODMAed = 0;	-	-	{c = qeth_layer2_iend_setF%lmac(card,laddr->sa_si_d, IPA_CMD_SETVMAC);e)N6f (rc	 Ne-NMPRINT_WARN("EAAor6in rAUTODMAing MAC,address on " \6-NMM88 "4%c in6%s: x%x\n",8CARD_BUS_ID(card),5rc);	-NMQETH_DBF	TEXT_(trace, 2, "2err%d",5rc);	-NM{	/* 2 -EIO);)N}+tWcard->i
fo.layer2_mac	rAUTODMAed = 1);)Nmemcpy(F%A->F%A_addr, addr->sa_si_d, OSA_ADDR_LEN);e)NPRINT_INFO("MAC,address %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "6-MM88 "successfully rAUTODMAed on 4%c in6%s\n",6-MM88 F%A->F%A_addr[0],F%A->F%A_addr[1],F%A->F%A_addr[2],6-MM88 F%A->F%A_addr[3],F%A->F%A_addr[4],F%A->F%A_addr[5],6-MM88 F%A->F_LO);	-_+	{c = qeth_layer2_iend_F%lmac(card,l&card->F%A->F%A_addr[0]);	+M6f (!rc)e+NN{c = qeth_layer2_iend_setmac(card,laddr->sa_si_d);	{	366_chi c;	68_ _(w,
5392,45,+5541,22
x068qeth_layer2_rAUTODMA_addr_entry(s,		0x0qeth_card6*card,- -	,1s,		0x0qeth_ipaddrC*addreu62	
-1		. c	= 0;	-_F	6f (!addr->is_mulineas/)e{		{	/* 2 0;	-_F	QETH_DBF	TEXT(trace, 2, "setgmac");	{	QETH_DBF	HEX(trace,3,&addr->mac[0],OSA_ADDR_LEN);e)N{c = qeth_layer2_iend_setF%lmac(card,l&addr->mac[0],-
-	,		IPA_CMD_SETGMAC);e)N6f (rc	e-NMPRINT_ERR("Could not set group MAC," \6-NMM88"%02x:%02x:%02x:%02x:%02x:%02x on %s: %x\n",6-NMM88addr->mac[0],addr->mac[1],addr->mac[2],6-MMM88addr->mac[3],addr->mac[4],addr->mac[5],6-MMM88QETH_CARD_IFNAME(card),rc);	-N366_chi c;	+1{	/* 2 qeth_layer2_iend_setgroupmac(card,l&addr->mac[0]);e{}9 aE80D-/mLint68qeth_layer2_derAUTODMA_addr_entry(s,		0x0qeth_card6*card,- -	,188s,		0x0qeth_ipaddrC*addreu62	
-1		. c	= 0;	-_F	6f (!addr->is_mulineas/)e{		{	/* 2 0;	-_F	QETH_DBF	TEXT(trace, 2, "F%lgmac");	{	QETH_DBF	HEX(trace,3,&addr->mac[0],OSA_ADDR_LEN);e)N{c = qeth_layer2_iend_setF%lmac(card,l&addr->mac[0],-
-	,		IPA_CMD_DELGMAC);e)N6f (rc	e-NMPRINT_ERR("Could not F%leieCgroup MAC," \6-NMM88"%02x:%02x:%02x:%02x:%02x:%02x on %s: %x\n",6-NMM88addr->mac[0],addr->mac[1],addr->mac[2],6-MMM88addr->mac[3],addr->mac[4],addr->mac[5],6-MMM88QETH_CARD_IFNAME(card),rc);	-N366_chi c;	-	+1{	/* 2 qeth_layer2_iend_F%lgroupmac(card,l&addr->mac[0]);e{}9 aE80D-/mLint6(w,
5526}14
+5652,,

-	{	366_chiqeth_layer3_derAUTODMA_addr_entry(card,laddr);e{}9 a-inx
-qeth_fake_h	ader(s,		0x0sk_bux06*skb,8s,		0x0nTO_dec in6*42		s-NM8888816814ea7	short A_4,, 80825*daddr, 80825*saddr,6-NM8888816814ea7	}en)u-{	-N366_chiQETH_FAKE_LL_LEN;	-}_-hE80D-/mLint68qeth_netF%A_	nit(s,		0x0nTO_dec in6*42	-u8{R(w,
5558}90+5676,120x148M_}A->vlan_rx_kill_v6d	= qeth_vlan_rx_kill_v6d;48M_}A->vlan_rx_add_v6d	= qeth_vlan_rx_add_v6d;	{,c62	}	+1deA->hard_h	ader = card->orig_hard_h	ader21 	6f (qeth_gTO_netF%A_*6514(card)	& IFF_NOARP	 Ne{		deA->rebuild_h	ader = 0,	0;e{		deA->hard_h	ader = 0,	0;e+W16f (card->op1ions.fake_ll)R+W1,deA->hard_h	ader = qeth_fake_h	ader;e{		deA->h	ader_cache_upsi_n = 0,	0;e{		deA->hard_h	ader_cache = 0,	0;e{	}R(w,
5572}100+5693,,

-	{	deA->hard_h	ader_parse = 0,	0;e{	F%A->iet_mac	address = qeth_layer2_iet_mac	address;e{	F%A->*6514	|= qeth_gTO_netF%A_*6514(card);e)N6f (card->op1ions.fake_ll)R-1,deA->hard_h	ader = qeth_fake_h	ader;e-+-	{eR-1,deA->hard_h	ader = 0,	0;e{	6f ((card->op1ions.fake_broadeas/) ||68	888 (card->i
fo.broadeas/_capa_le))e{		deA->*6514	|= IFF_BROADCAST;_(w,
5672}22655789,2,

-	{	MQETH_DBF	TEXT_(setup, 2, "5err%d",5rc);	X		goto,out;687+	a7/*network 4%c in6will be eacopt3ed*/++M6f (card->F%A) 81+NMcard->deA->hard_h	ader = card->orig_hard_h	ader21+NN{	/* 2 0;	+1}eE-/* at first set_onlMA_Fal			a_= netF%A */++Mcard->deA = qeth_gTO_netF%A in(card->i
fo.A_4,,-+-	,1888888 card->i
fo.link_A_4,	;_{M6f (!card->F%A)Ne)NMcard->deA = qeth_gTO_netF%A in(card->i
fo.A_4,,--	-	,1888888 card->i
fo.link_A_4,	;_)NM6f (!card->F%A)Ne)NM	qeth_qdio_clear_card(card,lcard->i
fo.A_4,	==--	-	,188888QETH_CARD_TYPE_OSAE);6-	,	{c = -ENODEV;6-		MQETH_DBF	TEXT_(setup, 2, "6err%d",5rc);	-NM	goto,out;6-1	}e-NMcard->deA->dr 9 = card;e-NMcard->deA->A_4,	= qeth_gTO_arphdr_A_4,(card->i
fo.A_4,,--	-	,11888888 card->i
fo.link_A_4,	;_)NMcard->deA-> ni-	=8qeth_netF%A_	nit21+NNqeth_qdio_clear_card(card,lcard->i
fo.A_4,	==-+-	,188888QETH_CARD_TYPE_OSAE);6+,	{c = -ENODEV;6+	MQETH_DBF	TEXT_(setup, 2, "6err%d",5rc);	+		goto,out;687+	a7card->deA->dr 9 = card;ea7card->orig_hard_h	ader = card->deA->hard_h	ader;	a7card->deA->A_4,	= qeth_gTO_arphdr_A_4,(card->i
fo.A_4,,-+-	,11888888 card->i
fo.link_A_4,	;_+Mcard->deA-> ni-	=8qeth_netF%A_	nit21{	366_chi0;	6out:	X	PRINT_ERR("Initializa1ion in hardsetup,faiMWd!5rc=%d\n",8rc);	(w,
5906,15656027,90x148        }	{	QETH_DBF	HEX(setup,2, card->F%A->F%A_addr, OSA_ADDR_LEN);e e)N{c = qeth_layer2_iend_setF%lmac(card,l&card->F%A->F%A_addr[0],-
-	,		IPA_CMD_SETVMAC);e)        6f (rc	 Ne-NMcard->i
fo.layer2_mac	rAUTODMAed = 0;	-                PRINT_WARN("EAAor6in processing MAC,address on " \6-                           "4%c in6%s: x%x\n",CARD_BUS_ID(card),rc);	+	{c = qeth_layer2_iend_setmac(card,l&card->F%A->F%A_addr[0]);	+        6f (rc		{	MQETH_DBF	TEXT_(setup, 2,"2err%d",rc);	-        } -	{eR-1,card->i
fo.layer2_mac	rAUTODMAed = 1);         {	/* 2 0;	68_ _(w,
6712}90+6827,8Fx068		rtnl_un			k();	{	M6f (!card->usn_hard_s14p	 86231	__u8 *mac	= &card->F%A->F%A_addr[0];	)NM	6f (({c = qeth_layer2_iend_setF%lmac(card,lmac,-
-	,	,118888IPA_CMD_DELVMAC)));	-NM	MQETH_DBF	TEXT_(setup, 2, "Lerr%d",5rc);	+			{c = qeth_layer2_iend_F%lmac(card,lmac);	{	1	QETH_DBF	TEXT_(setup, 2, "Lerr%d",5rc);	 NM	6f (({c = qeth_iend_s14plan(card))E- -	,1QETH_DBF	TEXT_(setup, 2, "1err%d",5rc);	U1	}e(w,
6872}8F+6986}e22
-	{qeth_reUTODMA_netF%A(s,		0x0qeth_card6*card-u8{R_MQETH_DBF	TEXT(setup, 3, "reUnetF");e)N6f (card->deA->reg_ic ieC!= NETREG_UNINITIALIZED)e+N6f (card->deA->reg_ic ieC!= NETREG_UNINITIALIZED) 81+NMqeth_netF%A_	nit(card->F%A);e{		{	/* 2 0;	+1}eE-/* sysfslmag/mL*/	X	SET_NETDEV_DEV(card->F%A,l&card->gF%A->F%A);	{	366_chi eUTODMA_netF%A(card->F%A);e(w,
6961,9
+7077}90x148M}XF	{	36copt3_*651C- card->ic ie;e)N6f (ccw_	ic in_set_online(CARD_RDEV(card)) ||6-,8888ccw_	ic in_set_online(CARD_WDEV(card)) ||6-,8888ccw_	ic in_set_online(CARD_DDEV(card))e{	+M6f (({c = ccw_	ic in_set_online(CARD_RDEV(card))e ||6+18888({c = ccw_	ic in_set_online(CARD_WDEV(card))e ||6+18888({c = ccw_	ic in_set_online(CARD_DDEV(card))e)86231QETH_DBF	TEXT_(setup, 2, "1err%d",5rc);	U1	{	/* 2 -EIO);{	}R(w,
7157x26+7273,8Fx068	card6= qeth_gTO_card_from_dev(	eA-21{N6f (card6== 0,	0-	{		goto,out;6-1if(card->op1ions.layer2)e+N6f((card->op1ions.layer2) ||6+1888(card->deA->hard_h	ader == qeth_fake_h	adere-	{		goto,out;6F	{	3cu_eaad_			k();		0x06814esctive tim.s390/net/qeth_sys.Ee 2or 9s	{	s390/net/qeth_sys.E= ht_h"TA6S};ses390/net/qeth_sys.E0d0anDD1-03 15:49:39hp		.e		evice_t hpt366s390/net/qeth_sys.E0d0anDD2-03 06:42:43hp		.e		(w,
1x6651},
ER_U/*
  *
-FD 6___A/dve tim.s390/net/qeth_sys.Ee($R%A 6ion: 1.48 $)
+ * 6___A/dve tim.s390/net/qeth_sys.Ee($R%A 6ion: 1.49 $)
 ,D
  * L___A on zSeri,s OSA Express and HiperSockets0supdort
 ,D This fileFcontains cod= relata70to sysfs.	(w,
20},
+20},
x0680incluF% "qeth_mpc.h"	80incluF% "qeth_fs.h"	8X-conic	W_PCI_VERSION_QETH_SYS_C = "$R%A 6ion: 1.48 $";	+conic	W_PCI_VERSION_QETH_SYS_C = "$R%A 6ion: 1.49 $";	X68/*DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD/68/*                                                                           D/6(w,
514,190+514,11

-	{	1{	/* 2 -EPERM;	 e{	i = simpln_scrtoul(buf,l&tmp, 16);e)N6f ((i =={0) || (i =={1)	 Ne-NMcard->op1ions.fake_ll =6i;6-1M6f (card->F%A) 81)NM	6f (i)	-  1	
Mcard->deA->hard_h	ader = qeth_fake_h	ader;e-+	+-	{eR-1,
Mcard->deA->hard_h	ader = 0,	0;e-1	}e-N}e-+-	{e {	+M6f ((i	!={0)	&& (i	!={1)	 86231PRINT_WARN("fake_ll: wriieC0 or610to this file!\n")0	{		{	/* 2 -EINVAL;687+	a7card->op1ions.fake_ll =6i;6{	366_chicount;	68_ _	0x06814esctive tim.scsi/ahci.Ee 2or 9s	{	scsi/ahci.E= ht_h"TA6S};sescsi/ahci.E0d0anDD1-,1 07:48:59hp		.e		evice_t hpt366scsi/ahci.E0d0anDD2-05 22357:44 -		.e		(w,
250,665250,8Fx068	  board_ahci },8/* ICH7RL*/	X	{ PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,68	  board_ahci },8/* ICH7RL*/	+	{ PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,6+	  board_ahci },8/* ULi M5288L*/	X	{ }-/* DMAmin ieC	TODL*/	X};_ _	0x06814esctive tim.scsi/ide-scsi.Ee 2or 9s	{	scsi/ide-scsi.E= ht_h"TA6S};sescsi/ide-scsi.E0d0anDD1-03 14:56:40hp		.e		evice_t hpt366scsi/ide-scsi.E0d0anDD2-02 15:21:22hp		.e		(w,
152x265152},
x06811}eE-	count0= min(pc->ig->length0- pc->b_count, bcount	;_U1	buf	= page_address(pc->ig->page) + pc->ig->offset21-		atapi_	nput_byies (t hpt, buf + pc->b_count, count	;_+NMt hpt->hwif->atapi_	nput_byies(t hpt, buf + pc->b_count, count	;_U1	bcount0-=icount; pc->b_count +=icount;	6M	6f (pc->b_count == pc->ig->length	 86231	pc->ig++R_(w,
174x26+174},
x06811}eE-	count0= min(pc->ig->length0- pc->b_count, bcount	;_U1	buf	= page_address(pc->ig->page) + pc->ig->offset21-		atapi_output_byies (t hpt, buf + pc->b_count, count	;_+NMt hpt->hwif->atapi_output_byies(t hpt, buf + pc->b_count, count	;_U1	bcount0-=icount; pc->b_count +=icount;	6M	6f (pc->b_count == pc->ig->length	 86231	pc->ig++R_(w,
481x265481x26
-	{	11M	6f (pc->sgE- -	,1M	6descsi_	nput_bux0ers(t hpt, pc, DMmp	;_U1	
M+-	{eR-1,
M		atapi_	nput_byies(t hpt, pc->curr.
-_posi1ion, DMmp	;_+-	,11Mt hpt->hwif->atapi_	nput_byies(t hpt, pc->curr.
-_posi1ion, DMmp	;_U1	
M+pr"Mak(KERN	ERR "ide-scsi: trans0erAed %d of,%d	byies\n",8DMmp, bcount.all	;_U1	
M}6231		pc->actually_trans0erAed +=iDMmp;	(w,
541,26+541x26
-	{	/* Set * acinDMArupt routMA_F*/	X	1dn_set_handlnr(t hpt, &6descsi_pc_inDr, get_timeout(pc), 6descsi_expiry);e{M/* Send * acactual packetC*/e-	atapi_output_byies(t hpt, scsi->pc->c, 12);	+Md hpt->hwif->atapi_output_byies(t hpt, scsi->pc->c, 12);	816f (test_bit (PC_DMA_OK, &pc->*6514)	 86231set_bit (PC_DMA_IN_PROGRESS, &pc->*6514);_U1	hwif->dma_sc rt(t hpt);		0x06814esctive tim.scsi/libata-core.Ee 2or 9s	{	scsi/libata-core.E= ht_h"TA6S};sescsi/libata-core.E0d0a4-12-27 12:41:22hp		.e		evice_t hpt366scsi/libata-core.E0d0anDD2-01 17:23:51hp		.e		(w,
1700,6651700,690x148MDPRINTK("EXIT\n")0	{8_A++odma	= 80825ata_pr_black	TODed(80		0x0ata_port *ap,8s,		0x0ata_dec in6*42	-u+{	+Wpr"Mak(KERN	WARNING "ata%u: 4%c %u is on DMA black	TOD, disa_Ming DMA\n",6+NMap->82	 F%A->F%Ano-21+}eaea+#definconic	W_PCI_0ata_dma_black	TOD []	= {	+W"WDC AC11000H",6+N"WDC AC22100H",6+N"WDC AC32500H",6+N"WDC AC33100H",6+N"WDC AC31600H",6+N"WDC AC32100H",6+N"WDC AC23d0aL",6+N"Compaq CRD-8241B",6+N"CRD-8400B",6+N"CRD-8480B",6+N"CRD-8482B",6+ N"CRD-84",6+N"SanDisk SDP3B",6+N"SanDisk SDP3B-64",6+N"SANYO CD-ROM CRD",6+N"HITACHI CDR-8",6+N"HITACHI CDR-8335",6+N"HITACHI CDR-8435",6+N"Toshiba CD-ROM XM-6202B",6+N"CD-532E-A",6+N"E-IDE CD-ROM CR-840",6+N"CD-ROM D hpt/F5A",6+N"WPI CDD-820",6+N"SAMSUNG CD-ROM SC-148C",6+N"SAMSUNG CD-ROM SC",6+N"SanDisk SDP3B-64",6+N"SAMSUNG CD-ROM SN-124",6+N"ATAPI CD-ROM DRIVE 40X MAXIMUM",6+N"_NEC DV5800A",6+};eaea+#defininx0ata_dma_black	TODed(80		0x0ata_port *ap,8s,		0x0ata_dec in6*42	-u+{	+W16814ea7	W_PCImod=l_num[40];ea7W_PCI_s;	+W16814ea7	inx0len;	+W1		.i;	+++Mata_dec_id_s1Aing(F%A->82	 mod=l_num, ATA_ID_PROD_OFS,-+-	,88sizeof(mod=l_num));	+Ms = &mod=l_num[0];ea7len = strnlen(s,8sizeof(mod=l_num));	+ea7/* ATAPI specifi,s that Mmpty spain6is blank-filMWdR eamove blanksL*/	+	whileF((}en > 0)	&& (s[}en - 1] == ' 'Ee Ne+NM}en--;	{	1s[}en] = 0;	+1}++	+1* 4 (i = 0; i < ARRAY_SIZE(ata_dma_black	TOD); i+1)e+7W6f (!strncmp(ata_dma_black	TOD[i],8s,	}en))R+W1,366_chi1;	+++M{	/* 2 021+}eahE80D-/mL16814ea7	inx0ata_gTO_mod=_mask(80		0x0ata_port *ap,8inx0shift-u8{R_Ms,		0x0ata_dec in6*masDMA,I_slaveR_(w,
1712}1,
51775,3,
x068XF	6f (shift == ATA_SHIFT_UDMA	 86231mask = ap->udma_mask;6-1M6f (ata_dec_pres.
-(masDMA))e+7W6f (ata_dec_pres.
-(masDMA)) 86231	mask &= (masDMA->82[ATA_ID_UDMA_MODES] & 0xff);6-1M6f (ata_dec_pres.
-(slave))R+W1,6f (ata_dma_black	TODed(ap,8masDMA)) 86+-	,1mask = 0;_+-	,1ata_pr_black	TODed(ap,8masDMA);_+-	,}e+7W}e+7W6f (ata_dec_pres.
-(slave)) 86231	mask &= (slave->82[ATA_ID_UDMA_MODES] & 0xff);6+W1,6f (ata_dma_black	TODed(ap,8slave)) 86+-	,1mask = 0;_+-	,1ata_pr_black	TODed(ap,8slave);_+-	,}e+7W}e8M}XF	-	{e 6f (shift == ATA_SHIFT_MWDMA	 86231mask = ap->mwdma_mask;6-1M6f (ata_dec_pres.
-(masDMA))e+7W6f (ata_dec_pres.
-(masDMA)) 86231	mask &= (masDMA->82[ATA_ID_MWDMA_MODES] & 0x07);6-1M6f (ata_dec_pres.
-(slave))R+W1,6f (ata_dma_black	TODed(ap,8masDMA)) 86+-	,1mask = 0;_+-	,1ata_pr_black	TODed(ap,8masDMA);_+-	,}e+7W}e+7W6f (ata_dec_pres.
-(slave)) 86231	mask &= (slave->82[ATA_ID_MWDMA_MODES] & 0x07);6+W1,6f (ata_dma_black	TODed(ap,8slave)) 86+-	,1mask = 0;_+-	,1ata_pr_black	TODed(ap,8slave);_+-	,}e+7W}e8M}XF	-	{e 6f (shift == ATA_SHIFT_PIO	 86231mask = ap->pio_mask;6(w,
3452,32653535,280x148}68XF80D-/mL80		0x0ata_probe_ent *
-ata_probe_ent_al			(inx0n,8s,		0x0dec in6*42		 80		0x0ata_port_i
fo **port)R+ata_probe_ent_al			(s,		0x0dec in6*42		 80		0x0ata_port_i
fo *port)R8{R_Ms,		0x0ata_probe_ent *probe_ent;	
-1		.i;e e)Nprobe_ent = kmal			(sizeof(*probe_ent)I_0n,8GFP_KERNE0-21+Nprobe_ent = kmal			(sizeof(*probe_ent),8GFP_KERNE0-21{M6f (!probe_ent)I{	}1	pr"Mak(KERN	ERR DRV_NAME "(%s):,out of,mamory\n",6 11888888 kobject_F_LO(&(F%A->kobj)));	{		{	/* 2 0,	0;e{	}R ;)Nmemset(probe_ent, 0, sizeof(*probe_ent)I_0n);	+Mmemset(probe_ent, 0, sizeof(*probe_ent));e e)N* 4 (i = 0; i < n; i+1) 81)NMINIT_LIST_HEAD(&probe_ent[i].nod=)21-		probe_ent[i].deA = F%A;	-1-		probe_ent[i].sht = port[i]->sht21-		probe_ent[i].host_*6514	= port[i]->host_*651421-		probe_ent[i].pio_mask	= port[i]->pio_mask;6-		probe_ent[i].mwdma_mask	= port[i]->mwdma_mask;6-1Mprobe_ent[i].udma_mask	= port[i]->udma_mask;6-1Mprobe_ent[i].port_op4	= port[i]->port_op4;	+MINIT_LIST_HEAD(&probe_ent->nod=)21+Nprobe_ent->deA = F%A;	 e-N}e+Nprobe_ent->sht = port->sht21+Nprobe_ent->host_*6514	= port->host_*651421+Nprobe_ent->pio_mask	= port->pio_mask;6+Nprobe_ent->mwdma_mask	= port->mwdma_mask;6+Nprobe_ent->udma_mask	= port->udma_mask;6+Nprobe_ent->port_op4	= port->port_op4;	 6{	366_chiprobe_ent;	68_(w,
3487x26+3566x26
-	{ata_pci_	nit_nD-/ve_mod=(s,		0x0pci_F%A *p42		 80		0x0ata_port_i
fo **port)R8{R_Ms,		0x0ata_probe_ent *probe_ent =1-		ata_probe_ent_al			(1,0pci_F%A_to_dev(p42	),8port);_+-	ata_probe_ent_al			(pci_F%A_to_dev(p42	),8port[0]);e{M6f (!probe_ent)	{		{	/* 2 0,	0;e{_(w,
3513}396+3592,47

-	{	366_chiprobe_ent;	68_ e-80		0x0ata_probe_ent *
-ata_pci_	nit_legacy_mod=(s,		0x0pci_F%A *p42		 80		0x0ata_port_i
fo **port)R+80D-/mL80		0x0ata_probe_ent *
+ata_pci_	nit_legacy_mod=(s,		0x0pci_F%A *p42		 80		0x0ata_port_i
fo **port,	+    80		0x0ata_probe_ent **ppe2eu62	
-s,		0x0ata_probe_ent *probe_ent =1-		ata_probe_ent_al			(2,0pci_F%A_to_dev(p42	),8port);_+-s,		0x0ata_probe_ent *probe_ent, *probe_ent2;	+++Mprobe_ent = ata_probe_ent_al			(pci_F%A_to_dev(p42	),8port[0]);e{M6f (!probe_ent)	{		{	/* 2 0,	0;e+Mprobe_ent2 = ata_probe_ent_al			(pci_F%A_to_dev(p42	),8port[1]);	+M6f (!probe_ent2) 86+-	kfr	=(probe_ent)21+NN{	/* 2 0,	0;e+M}	+++Mprobe_ent->n_ports =i1;	{	probe_ent->irq =i14;e e)Nprobe_ent[0].n_ports =i1;	)Nprobe_ent[0].irq =i14;e+Nprobe_ent->hard_port_no = 0;_+-probe_ent->legacy_mod= = 1); 	)Nprobe_ent[0].hard_port_no = 0;_)Nprobe_ent[0].legacy_mod= = 1);+Mprobe_ent2->n_ports =i1;	{	probe_ent2->irq =i15); 	)Nprobe_ent[1].n_ports =i1;	)Nprobe_ent[1].irq =i15;	{	probe_ent2->hard_port_no = 1;	{	probe_ent2->legacy_mod= = 1); 	)Nprobe_ent[1].hard_port_no = 1;	)Nprobe_ent[1].legacy_mod= = 1);-_)Nprobe_ent[0].port[0].cmd_addrC= 0x1f0;_)Nprobe_ent[0].port[0].alt80D-us_addrC=_)Nprobe_ent[0].port[0].ctl_addrC= 0x3f6;_)Nprobe_ent[0].port[0].bmdma_addrC= pci_resource_sc rt(p42		 4));-_)Nprobe_ent[1].port[0].cmd_addrC= 0x170;_)Nprobe_ent[1].port[0].alt80D-us_addrC=_)Nprobe_ent[1].port[0].ctl_addrC= 0x376;_)Nprobe_ent[1].port[0].bmdma_addrC= pci_resource_sc rt(p42		 4)+8;6+Nprobe_ent->port[0].cmd_addrC= 0x1f0;_+Nprobe_ent->port[0].alt80D-us_addrC=_+Nprobe_ent->port[0].ctl_addrC= 0x3f6;_+Nprobe_ent->port[0].bmdma_addrC= pci_resource_sc rt(p42		 4)); e-	ata_scd_ports(&probe_ent[0].port[0])21-	ata_scd_ports(&probe_ent[1].port[0])21{	probe_ent2->port[0].cmd_addrC= 0x170;_{	probe_ent2->port[0].alt80D-us_addrC=_+Nprobe_ent2->port[0].ctl_addrC= 0x376;_{	probe_ent2->port[0].bmdma_addrC= pci_resource_sc rt(p42		 4)+8;6+++Mata_scd_ports(&probe_ent->port[0])21{	ata_scd_ports(&probe_ent2->port[0])21 	+W*ppe2C= probe_ent2;	{	366_chiprobe_ent;	68_ e(w,
3579,26+3666,8

-	{	-	{e- 	-port[1]	= port[0];e e)N6f ((port[0]->host_*6514	& ATA_FLAG_NO_LEGACY) =={0) {	+M6f ((port[0]->host_*6514	& ATA_FLAG_NO_LEGACY) =={06+18888&& (pF%A->class >> 8) =={PCI_CLASS_STORAGE_IDE)I{	}1	/* TODO:0supdort transi1ioning to nD-/ve mod=? */	X		pci_read_ER_Pig_byie(p42		 PCI_CLASS_PROG,l&tmp8);	{		mask	= (1 << 2) | (1 << 0-;_(w,
3641,9
+3729x26
-	{	1goto,err_out_reUTons218_F	6f (legacy_mod=) 81)NMprobe_ent = ata_pci_	nit_legacy_mod=(p42		 port);_-1M6f (probe_ent)	-		Mprobe_ent2 = &probe_ent[1]21+NNprobe_ent = ata_pci_	nit_legacy_mod=(p42		 port, &probe_ent2);	81} -	{e- 	-probe_ent = ata_pci_	nit_nD-/ve_mod=(p42		 port);_{M6f (!probe_ent)I{	(w,
3657,8F+3743,120x148M6f (legacy_mod=) 816M	6f (legacy_mod= & (1 << 0-E- -	,ata_dec in_add(probe_ent)21+NN-	{e-{	-	kfr	=(probe_ent)216M	6f (legacy_mod= & (1 << 1-E- -	,ata_dec in_add(probe_ent2)21+NN-	{e-{	-	kfr	=(probe_ent2);	81} -	{e 816M	ata_dec in_add(probe_ent)21{	}R(w,
3848,26+3938},
ER_UaE0i,_}, CONFIG_PCIe{EXPORT_SYMBOL_GPL(pci_test_ER_Pig_bit4)21-EXPORT_SYMBOL_GPL(ata_pci_	nit_legacy_mod=);e{EXPORT_SYMBOL_GPL(ata_pci_	nit_nD-/ve_mod=);e{EXPORT_SYMBOL_GPL(ata_pci_	nit_on=);e{EXPORT_SYMBOL_GPL(ata_pci_eamove_on=);e	0x06814esctive tim.scsi/libata-scsi.Ee 2or 9s	{	scsi/libata-scsi.E= ht_h"TA6S};sescsi/libata-scsi.E0d0anDD1-28 09:14:43hp		.e		evice_t hpt366scsi/libata-scsi.E0d0anDD2-05 17:22:16 -		.e		(w,
202},
+202},
x06811{0x40,811MEDIUM	ERROR, 0x11, 0x04},81// Uncorrecta_le ECC,MAAor88888 Uneacopt3ed read,MAAor	}1	/* BBD - b			k markWd	bad,*/	X		{0x80,811MEDIUM	ERROR, 0x11, 0x04},81// B			k markWd	bad1188Medium,MAAor,l16eacopt3ed read,MAAor	-		{0xFF, 0xFF, 0xFF, 0xFF},8// END mark 	+W	{0xFF, 0xFF, 0xFF, 0xFF},8// END mark1{	};	}	0,D-/mL16814ea7	W_PCI0,D-_ta_le[][4]	= {	}1	/* Must be first becau{e BUSY means no other bit4 valid D/6(w,
210}2265210}226x06811{0x20,811HARDWARE	ERROR,  0x00, 0x00},81// Dec in6,ault6811{0x08,811ABORTED_COMMAND, 0x47, 0x00},1// TimWd	out in xfMA,Ifakexparity * 4 now6811{0x04,811RECOVERED_ERROR, 0x11, 0x00},1// Racopt3ed ECC,MAAor188Medium,MAAor,leacopt3ed	-		{0xFF, 0xFF, 0xFF, 0xFF},8// END mark 	+W	{0xFF, 0xFF, 0xFF, 0xFF},8// END mark1{	};	}	1		.i	= 0;	}48Mcmd->result	= SAM_STAT_CHECK_CONDITION;	-	F+e{	/*- -8*	Is this an,MAAor8we,Aan process/parse- -8*/e-	 F+e{	6f(drv_ic i	& ATA_ERR)	}1	/* Read,* acMAA bit4 */	X		MAA = ata_chk_MAA(qc->ap	;_Ue{M/* Display,* acATA level,MAAor8i
fo */	-	F+e{	pr"Mak(KERN	WARNING "ata%u: 80D-us=0x%02x { ", qc->ap->82	 Frv_ic i);_{M6f(drv_ic i	& 0x80)	}1{	(w,
242},
+242},
x0681M6f(drv_ic i	& 0x01)	pr"Mak("EAAor6");	{	}9 	pr"Mak("}\n")0	-	F+e{	6f(MAA)	}1{	}1	pr"Mak(KERN	WARNING "ata%u: MAAor=0x%02x { ", qc->ap->82	 MAA);	(w,
259,11
+259,11
x0681M6f(MAA & 0x02)1	pr"Mak("TrackZeroNotFound6");	{	M6f(MAA & 0x01)1	pr"Mak("AddrMarkNotFound6");	{	Mpr"Mak("}\n")0	-		F+e{	M/* Should we,dump sector8i
fo here too ?? */	X	}e-NM	-	F+e+e{	/* Look * 4 MAA */	X	while(snnse_ta_le[i][0]	!={0xFF)	}1{	(w,
301,26+301,26
-	{	/* No,MAAor8?? */	X	pr"Mak(KERN	ERR "ata%u: called with no MAAor8(%02X)!\n",8qc->ap->82	 Frv_ic i);_{M/* addi1ional-snnse-cod=[-qualifier] */	-	F+e{	sb[0]	={0x70;	}	sb[2]	={MEDIUM	ERROR;	}	sb[7]	={0x0AR_(w,
488,190+488,240x148M}XF	{	6f (lba48) 86+-	tf->command = ATA_CMD_VERIFY_EXT;F+e{		tf->hob_nsect	= (n_sect	>> 8) & 0xff;_Ue{M	tf->hob_lbah6= (sect	>> 40) & 0xff;_UM	tf->hob_lbam6= (sect	>> 32) & 0xff;_UM	tf->hob_lbal6= (sect	>> 24) & 0xff;_-1} -	{e-+N} -	{e 81+NMtf->command = ATA_CMD_VERIFY;F+e{		tf->dec in6|= (sect	>> 24) & 0xf;	+1}eEe{	tf->nsect	= n_sect	& 0xff;_Ue-	tf->hob_lbah6= (sect	>> 16) & 0xff;_-1tf->hob_lbam6= (sect	>> 8) & 0xff;_-1tf->hob_lbal6= sect	& 0xff;_+1tf->lbah6= (sect	>> 16) & 0xff;_+1tf->lbam6= (sect	>> 8) & 0xff;_+1tf->lbal6= sect	& 0xff;_ 	{	366_chi0;	68_(w,
600},
+605x26
-	{	11M366_chi1;	8	{	11/* stores LBA27:24 in lower 4 bit4 of0dec in6reU */	-			tf->dec in6|= scsicmd[2];	{	1	tf->dec in6|= scsicmd[6];	8	{	11qc->nsect	= scsicmd[13];	U1	}e	0x06814esctive tim.scsi/qla2xxx/qla_os.Ee 2or 9s	{	scsi/qla2xxx/qla_os.E= ht_h"TA6S};sescsi/qla2xxx/qla_os.E0d0a4-12-08 22315:37hp		.e		evice_t hpt366scsi/qla2xxx/qla_os.E0d0anDD2-07 18:25:11hp		.e		(w,
859,26+859,26x068	 * InFal	 other cases we'l	 le-	an irq pi	k up0our IO and submi	.it68	 * to theFcontroller to improve aff	nity.- -8*/e-	6f (smp_processor_id() =={ha->las/_irq_cpu || was_Mmpty)e+N6f (_smp_processor_id() =={ha->las/_irq_cpu || was_Mmpty)e}1	qla2x00_next(ha	;_Ue{Mspin_			k_irq(ha->host->host_			k);e	0x06814esctive tim.scsi/sata_nv.Ee 2or 9s	{	scsi/sata_nv.E= ht_h"TA6S};sescsi/sata_nv.E0d0a4-12-22 15:58:44 -		.e		evice_t hpt366scsi/sata_nv.E0d0anDD1-20 14:39:17 -		.e		(w,
20,66520}e22
-	{ *  If you do not F%leieCtheFprov 6ions abopt, aleacipient may,u{e your	{ *   timion of * is fileFunder either theFOSL or6* acGPL.
 ,D
+ *  0.06
+ *     - Added gener/mLSATA supdort by,u{ing a0pci_F%A in_id that filtnrs on
+ *      6* acIDE storageFclass cod=.
+ *	{ *  0.03	{ *     - Fixed a bug where t achotplug handlnrs * 4 non-CK804/MCP04 were u{ing	{ *       mmio_base, which is only set for6* acCK804/MCP04 case.	(w,
44x26548},
x0680incluF% <6___A/libata.h>_8_ 0_},
-	eDRV_NAME	11"sata_nv"X-3_},
-	eDRV_VERSION	11"0.5"	+0_},
-	eDRV_VERSION	11"0.6"_8_ 0_},
-	eNV_PORTS	112_ 0_},
-	eNV_PIO_MASK	110x1f_(w,
108,665112},
x068
8enum0nv_host_A_4,
 81+NGENERIC,6 1NFORCE2,6 1NFORCE3,6 1CK804
(w,
128,665133}90x148M	PCI_ANY_ID, PCI_ANY_ID, 0, 0,cCK804 },	X	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,6 1	PCI_ANY_ID, PCI_ANY_ID, 0, 0,cCK804 },	+	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,e+NMPCI_ANY_ID, PCI_ANY_ID,e+NMPCI_CLASS_STORAGE_IDE<<8,l0xffff00, GENERIC },	X	{ 0, } /* DMAmin ieC	TODL*/	X};_ _(w,
136x26+144},
ER_Us,		0x0nv_host_descR8{R_Menum0nv_host_A_4,	host_A_4,;_-116814ea7	},
-		host_*651421 	8082	11(*ena_le_hotplug)(s,		0x0ata_probe_ent *probe_ent)21 	8082	11(*disa_Me_hotplug)(s,		0x0ata_host_set *host_set)21 	8082	11(*che	k_hotplug)(s,		0x0ata_host_set *host_set)21(w,
144}2165151,240x148};_ 80D-/mL80		0x0nv_host_desc0nv_F%A in_tbl[]	= {	}181+NM.host_A_4,	= GENERIC,6+NM.ena_le_hotplug	= 0,	0,6+NM.disa_Me_hotplug= 0,	0,6+NM.che	k_hotplug	= 0,	0,6+N},	+	{6 1	.host_A_4,	= NFORCE2,6-1	.host_*6514	={0x00000000,6 1	.ena_le_hotplug	= nv_ena_le_hotplug,6 1	.disa_Me_hotplug= nv_Fisa_Me_hotplug,6 1	.che	k_hotplug	= nv_che	k_hotplug,6 1},	X	{6 1	.host_A_4,	= NFORCE3,6-1	.host_*6514	={0x00000000,6 1	.ena_le_hotplug	= nv_ena_le_hotplug,6 1	.disa_Me_hotplug= nv_Fisa_Me_hotplug,6 1	.che	k_hotplug	= nv_che	k_hotplug,6 1},	X	{	.host_A_4,	= CK804,6-1	.host_*6514	={NV_HOST_FLAGS_SCR_MMIO,6 1	.ena_le_hotplug	= nv_ena_le_hotplug_ck804,6 1	.disa_Me_hotplug= nv_Fisa_Me_hotplug_ck804,6 1	.che	k_hotplug	= nv_che	k_hotplug_ck804,6(w,
168,665178},
x06880		0x0nv_hostR8{R_Ms,		0x0nv_host_desc	*host_desc;	+W16814ea7	},
-		host_*651421 };_ _ 80D-/mL80		0x0pci_F hpt30nv_pci_F hpt30=I{	(w,
284}8F+295,8

-	{	6f (sc	rAU > SCR_CONTROL)e{		{	/* 2 0xffffffffU;e e)N6f (host->host_desc->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	-NM{	/* 2 readl(ap->8oaddr.scA_addr + (sc	rAU * 4));	+M6f (host->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	+NM{	/* 2 readl((8082*)ap->8oaddr.scA_addr + (sc	rAU * 4));	{	-	{e- 	-{	/* 2 inl(ap->8oaddr.scA_addr + (sc	rAU * 4));	68_(w,
298,8F+309,8

-	{	6f (sc	rAU > SCR_CONTROL)e{		{	/* 2;e e)N6f (host->host_desc->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	-NMwriiel(val, ap->8oaddr.scA_addr + (sc	rAU * 4));	+M6f (host->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	+NMwriiel(val, (8082*)ap->8oaddr.scA_addr + (sc	rAU * 4));	{	-	{e- 	-outl(val, ap->8oaddr.scA_addr + (sc	rAU * 4));	68_(w,
322,665333}14

-	{	80		0x0ata_port_i
fo *ppi;R_Ms,		0x0ata_probe_ent *probe_ent;	 -1		. c;	+W132 bar;6+++        // Makexsure t is is aLSATA controller by,counting t acnumber of bars++        // (NVIDIALSATA controllers6will always have six bars).  Otherwise,++        // it's an,IDE controller and we 14eore it.	+1* 4 (bar=0; bar<6; bar+1)e+7W6f (pci_resource_sc rt(p42		 bar) =={0)R+W1,366_chi-ENODEV;6 _{M6f (!prinDMd_ timion+1)e}1	pr"Mak(KERN	DEBUG DRV_NAME "  timion "eDRV_VERSION "\n")0	(w,
352,11
+371}156x068M6f (!host)	{	1goto,err_out_fr	=_ent;	 	+Mmemset(host, 0, sizeof(s,		0x0nv_host));	{	host->host_desc = &nv_F%A in_tbl[ent->d hpt3_si_d];	8	{	probe_ent->p hp ie_si_d	= host;e e)N6f (host->host_desc->host_*6514	& NV_HOST_FLAGS_SCR_MMIO) {	+M6f (pci_resource_*6514(p42		 5)	& IORESOURCE_MEM)R+W1host->host_*6514	|={NV_HOST_FLAGS_SCR_MMIO;6+++M6f (host->host_*6514	& NV_HOST_FLAGS_SCR_MMIO) {	}1	16814ea7	},
-	base;	8	{	1probe_ent->mmio_base =6ioremap(pci_resource_sc rt(p42		 5),6(w,
395x265418},
x068	366_chi0;	6
,err_out_iounmap:e)N6f (host->host_desc->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	+M6f (host->host_*6514	& NV_HOST_FLAGS_SCR_MMIO)	{	M6ounmap(probe_ent->mmio_base);	{err_out_fr	=_host:	X	kfr	=(host);e	0x06814esctive tim.scsi/sata_promise.Ee 2or 9s	{	scsi/sata_promise.E= ht_h"TA6S};sescsi/sata_promise.E0d0a4-11
13 11:24:05 -		.e		evice_t hpt366scsi/sata_promise.E0d0anDD2-05 18:54:29hp		.e		(w,
156}e22+156}e8Fx068	  board_2037x },	X	{ PCI_VENDOR_ID_PROMISE,l0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,68	  board_2037x },	+	{ PCI_VENDOR_ID_PROMISE,l0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,6+	  board_2037x },	+	{ PCI_VENDOR_ID_PROMISE,l0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,6+	  board_2037x },	+	X	{ PCI_VENDOR_ID_PROMISE,l0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,68	  board_20319 },	X	{ PCI_VENDOR_ID_PROMISE,l0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,68	  board_20319 },	+	{ PCI_VENDOR_ID_PROMISE,l0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,6+	  board_20319 },	+	X	{ }-/* DMAmin ieC	TODL*/	X};_ _(w,
406,9
+414,11

-	{	1{	/* 2 IRQ_NONE;e{	}R ;)        spin_			k(&host_set->			k);e+	spin_			k(&host_set->			k);e+	+	wriiel(mask, mmio_base + PDC_INT_SEQMASK)); e-        * 4 (i = 0; i < host_set->n_ports; i+1) 81+1* 4 (i = 0; i < host_set->n_ports; i+1) 81{	1VPRINTK("dort %u\n",8i);	{	Map	= host_set->ports[i];	U1	tmp	= mask & (1 << (i + 1-E;e	0x06814esctive tim.scsi/sata_sil.Ee 2or 9s	{	scsi/sata_sil.E= ht_h"TA6S};sescsi/sata_sil.E0d0anDD1-27 12:37:33 -		.e		evice_t hpt366scsi/sata_sil.E0d0anDD2-05 18:29:05 -		.e		(w,
86,66586x26
-	{	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },	X	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },	X	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },	+	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },	X	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },	X	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },	X	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },		0x06814esctive tim.scsi/wd33c93.hce_t hpt366scsi/wd33c93.h= ht_h"TA6S};sescsi/wd33c93.h0d0a4-06-20 09:01:32hp	7.e		evice_t hpt366scsi/wd33c93.h0d0anDD2-03 06:42:40 -		.e		(w,
22,66522,8

-	{#ifn_}, WD33C93_H_ 0_},
-	eWD33C93_H_ 
+0incluF% <6___A/ER_Pig.h>_+_ 0_},
-	ePROC_INTERFACE     /* add cod= * 4 /proc6scsi/wd33c93/xxxcinDMAfain6*/	X0i,_}, ePROC_INTERFACE_ 0_},
-	ePROC_STATISTICS    /* add cod= * 4 keeping var6ous real time 80D-4 */		0x06814esctive tim.serial/8250.Ee 2or 9s	{	serial/8250.E= ht_h"TA6S};seserial/8250.E0d0a4-12-01 12:53:57hp		.e		evice_t hpt366serial/8250.E0d0anDD2-07 18:25:11hp		.e		(w,
987,8F+987,11

-	{	1/* Th= * llowing is not al		wWd	by,* actty layer and6 11888168afe. Ix0should be fixed ASAP */	X		6f (unlikely(tty->*6ip.count >= TTY_FLIPBUF_SIZE-) 81)NM	6f(tty->		w_latancy)R+W1,6f (tty->		w_latancy) 86+-	,1spin_un			k(&up->port.			k);e{	11Mtty_*6ip_bux0er_push(tty	;_+-	,1spin_			k(&up->port.			k);e+	
M}6231	/* If * is faiMWd,* an we will throw away,* a6231	888byies but must do so to clearcinDMArupt4 */	X		}_(w,
1059,26+1062}90x148M14eore_W_PC:	X		lsr6= serial_	np(up, UART_LSR);	81} whileF((}sA & UART_LSR_DR)	&& (max_countht_> 0));e+	spin_un			k(&up->port.			k);e{	tty_*6ip_bux0er_push(tty	;_+-spin_			k(&up->port.			k);e 	*80D-us6= }sA;	68_ _	0x06814esctive tim.serial/MakefileFbtive tim.serial/Makefile= ht_h"TA6S};seserial/Makefile0d0anDD1-15614:31:04hp		.e		evice_t hpt366serial/Makefile0d0anDD2-03 06:42:40 -		.e		(w,
48,36548}4

-	{obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o	{obj-$(CONFIG_SERIAL_MPSC) += mpsc.o	{obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o	+obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o		0x06814esctive tim.serial/ip22zilog.Ee 2or 9s	{	serial/ip22zilog.E= ht_h"TA6S};seserial/ip22zilog.E0d0a4-02-e8F19:42:44hp		.e		evice_t hpt366serial/ip22zilog.E0d0anDD2-03 06:42:40 -		.e		(w,
47,8F+47,,
ER_UaE0incluF% "ip22zilog.h"	8X-1		.ip22serial_curr.
-_minor6= 64;	-_F80825ip22_do_break(8082);	X68/*	(w,
59}100+57}e22
-	{0_},
-	eZSDELAY_LONG()1	1delay(20)	}0_},
-	eZS_WSYNC(W_Pnnel)	do { } whileF(0)	}X-3_},
-	eNUM_IP22ZILOG	1X-3_},
-	eNUM_CHANNELS	(NUM_IP22ZILOG * 2)e+3_},
-	eNUM_IP22ZILOG		1X+3_},
-	eNUM_CHANNELS		(NUM_IP22ZILOG * 2)e}X-3_},
-	eZS_CLOCK		4915d0a /* Zilog 	nput cl		k rata.L*/	+3_},
-	eZS_CLOCK		367d0a0	/* Zilog 	nput cl		k rata.L*/	 3_},
-	eZS_CLOCK_DIVISOR	16      /* Divisor6* is F hpt30uses.L*/	 68/*	(w,
86x26+84},
x0683_},
-	eIP22ZILOG_FLAG_TX_STOPPED	0x00000080683_},
-	eIP22ZILOG_FLAG_TX_ACTIVE	0x000001e		 _-116814ea7	1		.c*651;	+W16814ea7	inx,
Mc*651;	Ue{M/* L1-A keyboard break 80D-a.LF*/	X	1nx,
M	kbd_6d;	(w,
642,3665640,280x148M}62}R ;)/* Th= dort l		k is not held.LF*/	+/* Th= dort l		k is held and inDMArupt4 are disa_Med.LF*/	 odma	= 80825ip22zilog_s14p_rx(s,		0x0uart_port *port)R8{R_Ms,		0x0uart_ip22zilog_port *up	= UART_ZILOG(port);_{Ms,		0x0zilog_W_Pnnel *W_Pnnel;_-116814ea7	},
- *651421 68M6f (ZS_IS_CONS(up))e{		{	/* 2;e e)Nspin_			k_irqsave(&port->			k, *6514);_-_F	W_Pnnel = ZILOG_CHANNEL_FROM_PORT(port);_{e{M/* Disa_le al	 RX inDMArupt4.LF*/	X	up->curr.gs[R1] &= ~RxINT_MASK;	 -1p22zilog_maybe_upsi_n	rAUs(up, W_Pnnel));-_)Nspin_un			k_irqrestore(&port->			k, *6514);_2}R ;)/* Th= dort l		k is not held.LF*/	+/* Th= dort l		k is held.LF*/	 odma	= 80825ip22zilog_ena_le_ms(s,		0x0uart_port *port)R8{R_Ms,		0x0uart_ip22zilog_port *up	= (s,		0x0uart_ip22zilog_port *) dort;_{Ms,		0x0zilog_W_Pnnel *W_Pnnel = ZILOG_CHANNEL_FROM_PORT(port);_{W16814ea7	W_PCInew	rAU;_-116814ea7	},
- *651421-e)Nspin_			k_irqsave(&port->			k, *6514);_{e{Mnew	rAU = up->curr.gs[R15] | (DCDIE | SYNCIE | CTSIE);_{M6f (new	rAU != up->curr.gs[R15])I{	(w,
680}8F+670,,

-	{		/* NOTE: Not subject to 'transmitter ac-/ve' rula.LF*/8	{	1wriie_zsr.g(W_Pnnel, R15, up->curr.gs[R15]);e{	}R-_)Nspin_un			k_irqrestore(&port->			k, *6514);_2}R ; /* Th= dort l		k is not held.LF*/	(w,
807x26+795x26
-	{	up->curr.gs[R4]	|={X16CLK;	 -up->curr.gs[R12]	={brg & 0xff;_UMup->curr.gs[R13]	={(brg >> 8) & 0xff;_-1up->curr.gs[R14]	= BRSRC | BRENAB;	+W1p->curr.gs[R14]	= BRENAB;	{e{M/* C_PCac-er size	 80op bit4, and parity.F*/	X	up->curr.gs[3] &= ~RxN_MASK;	(w,
950,1365938},
ER_U80D-/mL80		0x0uart_ip22zilog_port *ip22zilog_irq_chain;hE80D-/mLint zilog_irq = -1); 	)80D-/mL80		0x0uart_F hpt30ip22zilog_rAU = 81)N.owner		=	THIS_MODULE,6-1.d hpt3_F_LO	=	"ttyS",6-1.devfs_F_LO	=	"tty/",6-1.major		=	TTY_MAJOR,6-};_-hE80D-/mL80825* __	nitFal			_on=_ta_le(16814ea7	},
- size)R8{R_M80825*ret21(w,
990},
+971,26
-	{	}	{e{M/* Not probe-a_le, hard cod= it.8*/e-	base =6(16814ea7	},
-) &sgioc->serdort;_+	base =6(16814ea7	},
-) &sgioc->uart;	{e{Mzilog_irq = SGI_SERIAL_IRQ;	{	36quest_mem_reUTon(base, 8, "IP22-Zilog")0	(w,
1047}90+1028},
ER_U-1		.parity = 'n';	 -1		.f		w = 'n';	 e)N6f (!serial_console)	-NM{	/* 2;	-_F	6f (op1ions)e{		uart_parse_op1ions(op1ions, &baud,l&parity, &bit4, &f		w);_ _(w,
1077}80+1055x26
-	{	u6814ea7	},
- *651421 -1		.baud,lbrg); 	)Npr"Mak("Console:cttyS%d (IP22-Zilog)\n",6-N       (ip22zilog_rAU.minor6- 64) + con->i
dex)21{	pr"Mak("Console:cttyS%d (IP22-Zilog)\n", con->i
dex)21{e{M/* Get firmware console setting4.LF*/	X	ip22serial_console_DMAmios(con, op1ions)0	(w,
1112}6651089,8

-	{	{	/* 2 0;	68_ _+80D-/mL80		0x0uart_F hpt30ip22zilog_rAU;eahE80D-/mL80		0x0console ip22zilog_console = {	}1.F_LO	=	"ttyS",6}1.wriie	=	ip22zilog_console_wriie,6(w,
1121,32651100,222
-	{	.i
dex	=	-1,6}1.si_d	=	&ip22zilog_rAU,	X};_-3_},
-	eIP22ZILOG_CONSOLE	(&ip22zilog_console)R-_)80D-/mLint __	nitFip22zilog_console_	nit(8082)u-{	-N1		.i;e-e)N6f (con_is_pres.
-())	-NM{	/* 2 0;	-	-	* 4 (i = 0; i < NUM_CHANNELS; i+1) 81)NM1		.* is_minor6= ip22zilog_rAU.minor6+.i;	+,c62	} /* CONFIG_SERIAL_IP22_ZILOG_CONSOLEL*/	 6-1M6f ((* is_minor6- 64) == (serial_console - 1))	-NM	break);)N}+tW6f (i6== 0,M_CHANNELS)	-NM{	/* 2 0;	-	-	ip22zilog_console.i
dex =6i;6-1 eUTODMA_console(&ip22zilog_console);	-N366_chi0;	-}_-#-	{e /* CONFIG_SERIAL_IP22_ZILOG_CONSOLEL*/	-3_},
-	eIP22ZILOG_CONSOLE		(NU	0-	-3_},
-	eip22zilog_console_	nit()	do { } whileF(0)	+80D-/mL80		0x0uart_F hpt30ip22zilog_rAU = 81+N.owner		= THIS_MODULE,6+1.d hpt3_F_LO	= "serial",6+1.devfs_F_LO	= "tts/",6+1.dev_F_LO	= "ttyS",6+1.major		= TTY_MAJOR,6+1.minor		= 64,6+1.nr		= 0,M_CHANNELS,
+0i,_}, CONFIG_SERIAL_IP22_ZILOG_CONSOLE6+1.cons		= &ip22zilog_console,	{,c62	}	+};_ _ 80D-/mL80825__	nitFip22zilog_prepare(8082)uI{	(w,
1160}1,
51127,240x148M* 4 (W_Pnnel = 0; W_Pnnel < NUM_CHANNELS; W_Pnnel+1)e}1	spin_			k_init(&ip22zilog_port_ta_le[W_Pnnel].port.			k);e 	-	ip22zilog_irq_chain = up = &ip22zilog_port_ta_le[0];	)N* 4 (W_Pnnel = 0; W_Pnnel < NUM_CHANNELS - 1; W_Pnnel+1)e-NMup[W_Pnnel].next = &up[W_Pnnel + 1];	{	ip22zilog_irq_chain = &ip22zilog_port_ta_le[NUM_CHANNELS - 1];	+        up = &ip22zilog_port_ta_le[0];	+N* 4 (W_Pnnel = NUM_CHANNELS - 1 ; W_Pnnel > 0; W_Pnnel--)R+W1up[W_Pnnel].next = &up[W_Pnnel - 1];	 1up[W_Pnnel].next = 0,	0;e{_8M* 4 (W_ip = 0; W_ip <eNUM_IP22ZILOG; W_ip+1) 81{	16f (!ip22zilog_c_ip	rAUs[c_ip]) 86231	ip22zilog_c_ip	rAUs[c_ip] = rp = gTO_zs(W_ip);e 	-	W1up[(W_ip * 2) + 0].port.membase =6(W_PCI_) &rp->c_PnnelA;	-	W1up[(W_ip * 2) + 1].port.membase =6(W_PCI_) &rp->c_PnnelB;e+	
Mup[(W_ip * 2) + 0].port.membase =6(W_PCI_) &rp->c_PnnelB;e+	
Mup[(W_ip * 2) + 1].port.membase =6(W_PCI_) &rp->c_PnnelA;	+e+	
M/* InFtheory mapbase isCtheFphysical,address ...LF*/	+	
Mup[(W_ip * 2) + 0].port.mapbase =-+-	,1(16814ea7	},
-) ioremap((16814ea7	},
-) &rp->c_PnnelB, 8);e+	
Mup[(W_ip * 2) + 1].port.mapbase =-+-	,1(16814ea7	},
-) ioremap((16814ea7	},
-) &rp->c_PnnelA, 8);e811}eE	{		/* C_Pnnel AF*/	(w,
1182x2651156}26
-	{	1up[(W_ip * 2) + 0].port.A_4,	= PORT_IP22ZILOG;	{	1up[(W_ip * 2) + 0].port.*6514	= 0;	{	1up[(W_ip * 2) + 0].port.lMA_F= (W_ip * 2) + 0;e-NMup[(W_ip * 2) + 0].*6514	|= IP22ZILOG_FLAG_IS_CHANNEL_A;R+W1up[(W_ip * 2) + 0].*6514	= 0;	}48M	/* C_Pnnel B */	X		up[(W_ip * 2) + 1].port.ioA_4,	= UPIO_MEM0	(w,
1191,9
+1165}90x148M	up[(W_ip * 2) + 1].port.fifosize = 1); M	up[(W_ip * 2) + 1].port.op4	= &ip22zilog_pop4;	 M	up[(W_ip * 2) + 1].port.A_4,	= PORT_IP22ZILOG;	-M	up[(W_ip * 2) + 1].port.f6514	= 0;	+M	up[(W_ip * 2) + 1].port.f6514	|= IP22ZILOG_FLAG_IS_CHANNEL_A;R M	up[(W_ip * 2) + 1].port.lMA_F= (W_ip * 2) + 1;	-M	up[(W_ip * 2) + 1].f6514	|= 0;	+M	up[(W_ip * 2) + 1].*6514	= 0;	{	}	68_ e(w,
1228,8F+1202}e22
-	{M	brU = BPS_TO_BRG(baud,lZS_CLOCK /eZS_CLOCK_DIVISOR);R M	up->curr.gs[R12]	={(brg & 0xff);R M	up->curr.gs[R13]	={(brg >> 8) & 0xff;_-11up->curr.gs[R14]	= BRSRC | BRENAB;	+WW1p->curr.gs[R14]	= BRENAB;	{1	__load_zsr.gs(W_Pnnel, 1p->curr.gs);e+	        /* set masDMAcinDMArupt ena_leF*/	+	        wriie_zsr.g(W_Pnnel, R9, up->curr.gs[R9])21{e{MNspin_un			k_irqrestore(&up->port.			k, *6514);_2	}_(w,
1250,15651226,,
ER_UaE	ip22zilog_init_hw();e 	-	/* We,Aan only 	nitF* is onin6we have probed,* acZilogs6-N * in * acsysDMm.6-N */	-	ip22zilog_rAU.nr = NUM_CHANNELS;	-	ip22zilog_rAU.cons =eIP22ZILOG_CONSOLE;	-	-	ip22zilog_rAU.minor6=.ip22serial_curr.
-_minor;	-	ip22serial_curr.
-_minor6+= NUM_CHANNELS;	-	{	{	/ = uart_ eUTODMA_d hpt3(&ip22zilog_rAU);_{M6f ({	/ =={0) {	 	N1		.i;e(w,
1276,11
+1243,8Fx06880D-/mLint __	nitFip22zilog_	nit(8082)u {	 	/* IP22 Zilog setup,is hard cod=d,lno probing to do.LF*/	-aE	ip22zilog_al			_ta_les();_-_F	ip22zilog_ports_	nit();	-	ip22zilog_console_	nit();	 	{	366_chi0;	68_	0x06814esctive tim.usb/class/cdc-acm.Ee 2or 9s	{	usb/class/cdc-acm.E= ht_h"TA6S};seusb/class/cdc-acm.E0d0anDD1-14 16:02:24 p		.e		evice_t hpt366usb/class/cdc-acm.E0d0anDD2-02 22319:36 -		.e		(w,
261,1665261,226x0686880D-/mLint acm_tty_open(s0		0x0tty_s0		0x0*tty, s0		0x0fileF*filpeu62	
-s,		0x0acm *acm = acm_ta_le[tty->i
dex];_+-s,		0x0acm *acm;	+W1		.rv = -EINVAL;687dbg("EnDMAing acm_tty_open.\n")0	+		+Mdown(&open_sem)21 	+Wacm = acm_ta_le[tty->i
dex];_8M6f (!acm || !acm->F%A)	-NM{	/* 2 -EINVAL;6+	1goto,err_out;6+	-	{e-{	-rv = 0;	}48Mtty->d hpt3_si_d = acm;_8Macm->tty = tty); e-        down(&open_sem)21+1 68M6f (acm->used) {	 	Ngoto,doneR_(w,
279,26+285,8

-	{	acm->ctrlurb->deA = acm->F%A;_8M6f (usb_submi	_urb(acm->ctrlurb,8GFP_KERNE0-) {	 	Ndbg("usb_submi	_urb(ctrl irq) faiMWd")0	-		goto,baiM_out;6+		rv = -EIO;6+	1goto,err_out;6{	}	{e{Macm->readurb->deA = acm->F%A;_(w,
297}14
+304}14

-	{
,done:e{Macm->used++R_+err_out:	 1up(&open_sem)21-	{	/* 2 0;	+1{	/* 2 rA;	 e full_baiMout:	 1usb_kill_urb(acm->readurb)21 baiM_out_and_un	ink:	 1usb_kill_urb(acm->ctrlurb)21-baiM_out:	 1up(&open_sem)21 	{	/* 2 -EIO);{8_	0x06814esctive tim.usb/core/F%A o.Ee 2or 9s	{	usb/core/F%A o.E= ht_h"TA6S};seusb/core/F%A o.E0d0anDD1-14 16:01:56 p		.e		evice_t hpt366usb/core/F%A o.E0d0anDD2-02 22320:50 -		.e		(w,
123,1365123,260x148M}XF	{	6f (pos <esizeof(s,		0x0usb_F%A in_descriptor)) 86+-	s,		0x0usb_F%A in_descriptor6*42sc = kmal			(sizeof(*42sc),8GFP_KERNE0-21+NM6f (!42sc) 86+-	,{	/ = -ENOMEM0	+-	,goto,err;e+7W}e+7Wmemcpy(42sc, &F%A->F%scriptor, sizeof(F%A->F%scriptor));e+		le16_to_cpus(&desc->bcdUSB);e+		le16_to_cpus(&desc->idVendor);e+		le16_to_cpus(&desc->idProd	0x);e+		le16_to_cpus(&desc->bcdDec in);F+e{		len = sizeof(s,		0x0usb_F%A in_descriptor)0- pos216M	6f (len > nbyiesE- -	,len = nbyies;6-1M6f (copy_to_user(buf,l((W_PCI_)&F%A->F%scriptor) + pos,	}en)) 86+-	6f (copy_to_user(buf,l((W_PCI_)42sc) + pos,	}en)) 86+-		kfr	=(42sc);e{	11{	/ = -EFAULT;e{	11goto,err;e 7W}e+7Wkfr	=(42sc);e{e 7W*ppos += len;	U1	buf	+= len;		0x06814esctive tim.usb/core/hcd.Ee 2or 9s	{	usb/core/hcd.E= ht_h"TA6S};seusb/core/hcd.E0d0anDD1-25 13:50:18 p		.e		evice_t hpt366usb/core/hcd.E0d0anDD2-02 22320:55 -		.e		(w,
676,665676,26
-	{	INIT_LIST_HEAD (&bus->bus_	TOD);	}48Mclass_F%A in_initialize(&bus->class_F%A);e+	bus->class_F%A.class = &usb_host_class;	68_ EXPORT_SYMBOL (usb_bus_init);_ _(w,
732x265733,60x148M}XF	{	snpr"Maf(bus->class_F%A.class_82	 BUS_ID_SIZE, "usb%d",5busnum);6-1bus->class_F%A.class = &usb_host_class;	61bus->class_F%A.deA = bus->controller21 	{	/val6= class_F%A in_add(&bus->class_F%A);e{M6f ({	/val) 86	0x06814esctive tim.usb/	nput/hid-core.Ee 2or 9s	{	usb/	nput/hid-core.E= ht_h"TA6S};seusb/	nput/hid-core.E0d0anDD1-22 02319:23 p		.e		evice_t hpt366usb/	nput/hid-core.E0d0anDD2-02 22318:48 -		.e		(w,
1295,120+1295,150x148M	u6814ea7	W_PCIA_4,,L80825*buf,linx0size)R8{R_M1		.result,leatri,s = 4;	+e+	memset(buf,0,size);	// Makexsure wexparse really recehptd si_dF+e{	do {e{		{	sult	= usb_control_msg(F%A, usb_rcvctrlpipe(F%A, 0),e{	11MUSB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN,e{	11M(A_4,	<< 8),lifnum, buf,lsize	 HZ * USB_CTRL_GET_TIMEOUT);	{		{	/ri,s--;	-1} whileF({	sult	< 0	&& {	/ri,s);e+	} whileF({	sult	< size && {	/ri,s);e M{	/* 2 result;	68_ e(w,
1663x2651666x26
-	{	pr"Mak("\n")0	{,c62	}	 e)N6f (!(hid	= hid_parse_report(r42sc, rsize))) {	+M6f (!(hid	= hid_parse_report(r42sc, n)-) {	 	Ndbg("parsing report descriptor6faiMWd")0	 7Wkfr	=(r42sc);e{	1{	/* 2 0,	0;e(w,
1740x26+1743}26
-	{	1s,	cat(hid->F_LO, buf)216M	6f (usb_s1Aing(F%A	 F%A->F%scriptor.iProd	0x, buf,l64) > 0)e{	11snpr"Maf(hid->F_LO, 64, "%s %s",5hid->F_LO, buf)21-1} -	{e 6f (usb_s1Aing(F%A	 F%A->F%scriptor.iProd	0x, buf,l128) > 0) {	+M} -	{e 6f (usb_s1Aing(F%A	 F%A->F%scriptor.iProd	0x, buf,l64) > 0) 86231	snpr"Maf(hid->F_LO, 128, "%s", buf)216M} -	{e- 	-snpr"Maf(hid->F_LO, 128, "%04x:%04x", 6	0x06814esctive tim.usb/net.usbnet.Ee 2or 9s	{	usb/net.usbnet.E= ht_h"TA6S};seusb/net.usbnet.E0d0anDD1-14 16:01:50 p		.e		evice_t hpt366usb/net.usbnet.E0d0anDD2-02 22320:02hp		.e		(w,
3286,6653286,e22
-	{M// Sueacom EP-1427X-2	{MUSB_DEVICE (0x1189, 0x0893),6}1.s hpt3_i
fo =6(16814ea7	},
-) &ax8817x_i
fo,6+}, {	+M// goodway,corp usb gwusb2e-{	USB_DEVICE (0x1631, 0x6d0a),6+1.d hpt3_i
fo =6(16814ea7	},
-) &ax8817x_i
fo,6 },	X,c62	}	 e	0x06814esctive tim.usb/serial/KER_Pigce_t hpt366usb/serial/KER_Pig= ht_h"TA6S};seusb/serial/KER_Pig0d0a4-12-05 10:44:05 -		.e		evice_t hpt366usb/serial/KER_Pig0d0anDD2-02 22318:38 -		.e		(w,
203},
+203}26
-	{	  module will be called io_ti.XF	{ER_PigcUSB_SERIAL_GARMINe-       1Ai80D-a "GaAmin GPS F hpt3"	+       1Ai80D-a "USB GaAmin GPS F hpt3"	        depends on USB_SERIAL	        help	          Say,Y here if you want to ER_nect to your GaAmin GPS.e	0x06814esctive tim.usb/serial/ftdi_sio.cce_t hpt366usb/serial/ftdi_sio.c= ht_h"TA6S};seusb/serial/ftdi_sio.c0d0anDD1-14 16:00:58 -		.e		evice_t hpt366usb/serial/ftdi_sio.c0d0anDD2-02 22320:59hp		.e		(w,
1140x26+1140x26
-	{	1goto,che	k_and_exit;e{	}R ;)N6f ((new	serial.baud_base != priA->baud_base) ||	+M6f ((new	serial.baud_base != priA->baud_base) &&	{	    (new	serial.baud_base < 9600))e{		{	/* 2 -EINVAL;68e	0x06814esctive tim.usb/serial/gaAmin_gps.cce_t hpt366usb/serial/gaAmin_gps.c= ht_h"TA6S};seusb/serial/gaAmin_gps.c0d0anDD1-14 16:01:56 p		.e		evice_t hpt366usb/serial/gaAmin_gps.c0d0anDD2-02 22318:38 -		.e		(w,
1,26+1,26
-	{/*	{ * GaAmin GPS F hpt3
 ,D
- * Copyright (C) d0a4 Hermann Kneissel hkneissel@t-on	ine.de
+ * Copyright (C) d0a4 Hermann Kneissel herkne@users.sourceforge.net
 ,D
{ * Th= latast  timion of * e F hpt30Aan be found6at
 ,D http://sourceforge.net/projects/gaAmin-gps/e	0x06814esctive tim.usb/storage/unusual_F%As.hce_t hpt366usb/storage/unusual_F%As.h= ht_h"TA6S};seusb/storage/unusual_F%As.h0d0anDD1-14 16:02:13 p		.e		evice_t hpt366usb/storage/unusual_F%As.h0d0anDD2-02 22319:27 -		.e		(w,
210x26+210x150x148M	a), 	{,c62	}	 e)UNUSUAL_DEV(  0x04e6, 0x0006, 0x0100, 0x0205, 	+/* ReportWd	by,Markus Demleitnt30<msdemlei@cl.uni-heidelberg.de>F*/	+UNUSUAL_DEV(  0x04e6, 0x0006, 0x0100, 0x0100, e+7W"SCM MicrosysDMms Inc.",6+NM"eUSB MMC Adaptt3",6+NMUS_SC_SCSI, US_PR_CB, 0,	0, 6+NMUS_FL_SINGLE_LUN), 	+	+/* ReportWd	by,Daniel Nouri <dpunktnpunkt@web.de>F*/	+UNUSUAL_DEV(  0x04e6, 0x0006, 0x0205, 0x0205, 	 7W"Shuttle",6 11"eUSB MMC Adaptt3",6 NMUS_SC_SCSI, US_PR_DEVICE, 0,	0, 6	0x06814esctive tim.video/cg14.cce_t hpt366video/cg14.c= ht_h"TA6S};sevideo/cg14.c0d0a4-11
27 06:52:49 p		.e		evice_t hpt366video/cg14.c0d0anDD2-04 21:32:58 -		.e		(w,
469,9
+469,9
ER_U-1		.is_8mb, 	inebyies,.i;e e8M6f (!sF%A) 81)NMprom_gTOproperty(nod=, "address",6-N31	8(W_PCI_) &bases[0], sizeof(bases));_-1M6f (!bases[0]) 86+-	6f (prom_gTOproperty(nod=, "address",6+-	,1     (W_PCI_) &bases[0], sizeof(bases)) <={06+11    || !bases[0]) 86 	1	pr"Mak(KERN	ERR "cg14: Dec in6is not mapped.\n")0	 			{	/* 2;e 1	}e	0x06814esctive tim.video/console/newport_con.cce_t hpt366video/console/newport_con.c= ht_h"TA6S};sevideo/console/newport_con.c0d0a4-07-29 09:00:39hp	7.e		evice_t hpt366video/console/newport_con.c0d0anDD2-03 06:42:40 -		.e		(w,
21,66521},
x0680incluF% <6___A/module.h>_80incluF% <6___A/slab.h>_8_+0incluF% <asm/io.h>_80incluF% <asm/uaccess.h>_80incluF% <asm/sysDMm.h>_80incluF% <asm/page.h>_(w,
73x26574},
x06880D-/mLinlMA_F80825newport_render_background(inx0xsc rt,linx0ysc rt,e{	11M1     inx0xend,linx0yend,linx0cieu62	
-newport_wait();	+-newport_wait(npre14);_2	npre14->set.wrmask = 0xffffffff;_2	npre14->set.drawmod=0 =6(NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK |e{	11M NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX1(w,
90},
+91x26
-	{	u6814ea7	short i;e{_8M* 4 (i = 0; i < 16; i+1) 81)NMnewport_bfwait();	+-Mnewport_bfwait(npre14);_2	Mnewport_cmap_setaddr(npre14, color_ta_le[i]);_2	Mnewport_cmap_setrgb(npre14,e{	11M    de,ault_red[i],_(w,
107,190+108,196
-	{	u6814ea7	},
- i;e{_8M* 4 (i = 0; i < logo->clutsize; i+1) 81)NMnewport_bfwait();	+-Mnewport_bfwait(npre14);_2	Mnewport_cmap_setaddr(npre14, i + 0x20);_2	Mnewport_cmap_setrgb(npre14, clut[0], clut[1], clut[2]);_2	Mclut	+= 3;e{	}R ;)Nnewport_wait();	+-newport_wait(npre14);_2	npre14->set.drawmod=0 =6(NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK |e{	11M NPORT_DMODE0_CHOST);_{e{Mnpre14->set.xysc rti = ((newport_xsize - logo->width) << 16) | (0);_2	npre14->set.xyendi = ((newport_xsize - 1) << 16);;)Nnewport_wait();	+-newport_wait(npre14);_2_8M* 4 (i = 0; i < logo->width*logo->height; i+1)_2	Mnpre14->go.hostrw0 =6*si_dvic<< 24;e(w,
132x265133}70x148M6f (logo_ac-/ve)e{		{	/* 2;e e)Nnewport_wait();	+-newport_wait(npre14);_2	npre14->set.wrmask = 0xffffffff;_2	npre14->set.drawmod=0 =6(NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK |e{	11M NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX1(w,
154x265155x26
-	{	u6814ea7	short trAU;e -1		.i;e e)Nnewport_wait();	+-newport_wait(npre14);_2	trAU = newport_vc2_gTO(npre14, VC2_IREG_CONTROL);e{Mnewport_vc2_sTO(npre14, VC2_IREG_CONTROL,e{	11(trAU | VC2_CTRL_EVIDEO))0	(w,
164x265165x26
-	{	npre14->set.dcbmod= = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM |e{	11       NPORT_DMODE_W2 | VC2_PROTOCOL);e{M* 4 (i = 0; i < 128; i+1) 81)NMnewport_bfwait();	+-Mnewport_bfwait(npre14);_2	M6f (i6== 92 || i6== 94)e{	11npre14->set.dcbsi_d0.byshort.s1 = 0xff00;	{	1-	{e-(w,
204},
+205x26
-	{	npre14->set.dcbmod= = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM |e{	11       NPORT_DMODE_W2 | VC2_PROTOCOL);e{M* 4 (i = 0; i < 128; i+1) 81)NMnewport_bfwait();	+-Mnewport_bfwait(npre14);_2	MlMA_ta_le[i] = npre14->set.dcbsi_d0.byshort.s1;e{	}R ;(w,
215,120+216,120x148M	npre14->set.dcbmod= = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM |e{	111       NPORT_DMODE_W2 | VC2_PROTOCOL);e{M	do {e-N31newport_bfwait();	+-MMnewport_bfwait(npre14);_2	M	trAU = npre14->set.dcbsi_d0.byshort.s1;e{	1M6f ((*rAU & 1) =={0)R{	111cols += (*rAU >> 7) & 0xfe;e{	1M6f ((*rAU & 0x80) =={0) {	-N31	newport_bfwait();	+-MMMnewport_bfwait(npre14);_2	M		trAU = npre14->set.dcbsi_d0.byshort.s1;e{	1M}6231} whileF((*rAU & 0x8000) =={0);_(w,
290,1665291,166ER_UaE	if (!sgi_gfxaddr)	{		{	/* 2 0,	0;e-	npre14	= (s,		0x0newport_re14	_) (KSEG1 + sgi_gfxaddr);	+-npre14	= (s,		0x0newport_re14	_)	/* ioremap0Aannot faiMF*/	+	
 ioremap(sgi_gfxaddr, sizeof(s,		0x0newport_re14));_2	npre14->cset.ER_Pigc= NPORT_CFG_GD0;	 e)N6f (newport_wait()) {	-N3{	/* 2 0,	0;e-	}	+M6f (newport_wait(npre14))6+	1goto,out_unmap;_{e{Mnpre14->set.xsc rti = TESTVAL;6876f (npre14->set._xsc rt.word != XSTI_TO_FXSTART(TESTVAL))	-NM{	/* 2 0,	0;e+M1goto,out_unmap;_{e{M* 4 (i = 0; i < MAX_NR_CONSOLES; i+1)_2	Mfont_si_d[i] = FONT_DATAR_(w,
309,665310}e22
-	{Mnewport_gTO_screensize();	 	{	366_chi"SGI Newport";	+e+out_unmap:	+M6ounmap((80825*)npre14);_+	{	/* 2 0,	0;e{}_ _ 80D-/mL80825newport_	nit(s,		0x0vc_si_d *vc,linx0init)	(w,
362,26+367x26
-	{	11M  (W_PCattA & 0xf0) >> 4)21{e{M/* Set theFcolor and drawing mod=.8*/e-	newport_wait();	+-newport_wait(npre14);_2	npre14->set.colori = W_PCattA & 0xf;_2	npre14->set.drawmod=0 =6(NPORT_DMODE0_DRAW | NPORT_DMODE0_BLOCK |e{	11M NPORT_DMODE0_STOPX | NPORT_DMODE0_ZPENAB |e(w,
371,26+376,26
-	{	/* Set coordin ies * 4 bitmap0opera1ion.F*/	X	npre14->set.xysc rti = (xpos << 16) | ((ypos + topsAan) & 0x3ff);R Mnpre14->set.xyendi = ((xpos + 7) << 16);;)Nnewport_wait();	+-newport_wait(npre14);_2_8M/* Go	 baby, go...F*/	X	RENDER(npre14, p)0	(w,
395x265400x26
-	{	11MM  xpos + ((count - 1) << 3), ypos,e{	11M1  (W_PCattA & 0xf0) >> 4)21{e)Nnewport_wait();	+-newport_wait(npre14);_2_8M/* Set theFcolor and drawing mod=.8*/e2	npre14->set.colori = W_PCattA & 0xf;_(w,
406,265411x26
-	{	* 4 (i = 0; i < count; i+1, xpos += 8) 86 	1p = &font_si_d[vc->vc_num][(scA_readw(s+1) & 0xff) << 4];e e)NNnewport_wait();	+--newport_wait(npre14);_2_8M	/* Set coordin ies * 4 bitmap0opera1ion.F*/	X		npre14->set.xysc rti =_(w,
459,26+464},
x068	366_chi1;_2}R ;)80D-/mLint newport_blank(s,		0x0vc_si_d *c,linx0blank)	+80D-/mLint newport_blank(s,		0x0vc_si_d *c,linx0blank,linx0mod=_switch)R8{R_Mu6814ea7	short trAU;e 	(w,
684},
+689x26
-	{	1x= = xs216M	x4	= tmp;e{	}R-Nnewport_wait();	+-newport_wait(npre14);_2	npre14->set.drawmod=0 =6(NPORT_DMODE0_S2S | NPORT_DMODE0_BLOCK |e{	11M NPORT_DMODE0_DOSETUP | NPORT_DMODE0_STOPX1{	11M | NPORT_DMODE0_STOPY)0	(w,
701,240+706,240x1480_},
-	eDUMMY (80825*) newport_dummyXF	{ER_stL80		0x0consw newport_con = 81)    .owner =		THIS_MODULE,6-    .con_sc rtup =-newport_sc rtup,6-    .con_	nitF=--newport_	nit,6-    .con_de	nitF=-newport_de	nit,6-    .con_clearc=-newport_clear,6-    .con_putcF=--newport_putc,6-    .con_putcsc=-newport_putcs,6-    .con_cursor6=-newport_cursor,6-    .con_scroll =-newport_scroll,6-    .con_bmove =-newport_bmove,6-    .con_switch =-newport_switch,6-    .con_blank =-newport_blank,6-    .con_font_set =-newport_font_set,6-    .con_font_de,ault =-newport_font_de,ault,6-    .con_set_palette =-newport_set_palette,6-    .con_scrolldel_d =-newport_scrolldel_d,6-    .con_set_origin =	DUMMY,6-    .con_save_screen =	DUMMY1+N.owner		  = THIS_MODULE,6+1.con_sc rtup	  = newport_sc rtup,6+1.con_	nit	  = newport_	nit,6+1.con_de	nit	  = newport_de	nit,6+1.con_clear	  = newport_clear,6+1.con_putc	  = newport_putc,6+1.con_putcs	  = newport_putcs,6+1.con_cursor	  = newport_cursor,6+1.con_scroll	  = newport_scroll,6+1.con_bmove 	  = newport_bmove,6+1.con_switch	  = newport_switch,6+1.con_blank	  = newport_blank,6+1.con_font_set	  = newport_font_set,6+1.con_font_de,ault = newport_font_de,ault,6+1.con_set_palette  = newport_set_palette,6+1.con_scrolldel_d  = newport_scrolldel_d,6+1.con_set_origin	  = DUMMY,6+1.con_save_screen  = DUMMY1 };_ _ 0i,_}, MODULE_(w,
730,665735},
x06880D-/mL80825__exit newport_console_exit(8082)u {	 	g/ve_up_console(&newport_con);	+M6ounmap((80825*)npre14);_{}_ _ module_	nit(newport_console_init);_	0x06814esctfs/KER_Pigce_fs/KER_Pig= ht_h"fs/KER_Pig0d0anDD1-18 18:41:01 p		.e		evice_fs/KER_Pig0d0anDD2-04 17:23:03 -		.e		(w,
1401,6651401,26
-	{	depends on INET	{	select LOCKD	{	select SUNRPC_+-select EXPORTFS	{	help	 	  If you want your L___A box to a0x0as an,NFS *server*, so that other	 	  computnrs on your local,network which supdort NFS Aan access certain	(w,
1474x2651475,,
ER_UaEER_PigcEXPORTFS	{	1Ai80D-aR-Nde,ault NFSD_UaEER_PigcSUNRPC_{	1Ai80D-aR	0x06814esctfs/ext2/xattA.cce_fs/ext2/xattA.c= ht_h"fs/ext2/xattA.c0d0anDD1-31 01:48:26 p		.e		evice_fs/ext2/xattA.c0d0anDD2-05 12:51:44hp		.e		(w,
881,665881,,
x0681M6f (IS_LAST_ENTRY(entry2))e{			366_chi1;_21M6f (entry1->e_hash != entry2->e_hash ||	+M1    entry1->e_F_LO_i
dex != entry2->e_F_LO_i
dex ||6 11888 entry1->e_F_LO_len != entry2->e_F_LO_len ||6 11888 entry1->e_value_size != entry2->e_value_size ||6 11888 memcmp(entry1->e_F_LO, entry2->e_F_LO, entry1->e_F_LO_len))e	0x06814esctfs/ext3/xattA.cce_fs/ext3/xattA.c= ht_h"fs/ext3/xattA.c0d0anDD1-22 07:45:09 p		.e		evice_fs/ext3/xattA.c0d0anDD2-05 12:51:44hp		.e		(w,
1162}6651162,,
x0681M6f (IS_LAST_ENTRY(entry2))e{			366_chi1;_21M6f (entry1->e_hash != entry2->e_hash ||	+M1    entry1->e_F_LO_i
dex != entry2->e_F_LO_i
dex ||6 11888 entry1->e_F_LO_len != entry2->e_F_LO_len ||6 11888 entry1->e_value_size != entry2->e_value_size ||6 11888 memcmp(entry1->e_F_LO, entry2->e_F_LO, entry1->e_F_LO_len))e	0x06814esctfs/hostfs/hostfs.hce_fs/hostfs/hostfs.h= ht_h"fs/hostfs/hostfs.h0d0a4-10-08 02:57:33 -	7.e		evice_fs/hostfs/hostfs.h0d0anDD2-07 18:25:10 -		.e		(w,
16,8F+16,290x1480_},
-	eHOSTFS_ATTR_CTIME	64480_},
-	eHOSTFS_ATTR_ATIME_SET	128480_},
-	eHOSTFS_ATTR_MTIME_SET	256	+	+/* These two are unusWd	by,hostfs.L*/	 3_},
-	eHOSTFS_ATTR_FORCE	512M/* Not a W_PngO, but a W_PngO itL*/	 3_},
-	eHOSTFS_ATTR_ATTR_FLAG	1024	+	+/* If you are very Aareful, you'l	 not in6that these two are missing:
+ *	+ * 3_},
-	eATTR_KILL_SUID0d048	+ * 3_},
-	eATTR_KILL_SGID04096
+ *	+ * and t is is becau{e they were added in 2.5 F%Aelopmenx0in t is patch:
+ *	+ * http://6___A.bkbit4.net:8080/6___A-2.5/	+ * cset@3caf4a12k4XgDzK7wyK-TGpSZ9u2Ww?nav=i
dex.html	+ * |src/.|src/incluF%|src/incluF%/6___A|relatad/incluF%/6___A/fs.h=+ *	+ * Actually, they are not needWd	by,most ->setattA() methods - they are set by	+ * callers6of not fy_W_PngO() to not fy6that the setuid/setg825bit4 must be
+ * dropped.
+ * not fy_W_PngO() will F%leieCtho{e *6514, makexsure attA->ia_val825&eATTR_MODE
+ * is on, and remove the appropriD-a bit4 from attA->ia_mod= (attA is a
+ * "80		0x0iattA *"). -BlaisorBlade
+ */_ _ 80		0x0hostfs_iattA {R_Mu6814ea7	1nx,ia_val82;e	0x06814esctfs/hostfs/hostfs_kern.cce_fs/hostfs/hostfs_kern.c= ht_h"fs/hostfs/hostfs_kern.c0d0anDD1-15614:01:55 p		.e		evice_fs/hostfs/hostfs_kern.c0d0anDD2-07 18:25:10 -		.e		(w,
823,665823,122
-	{MW_PCI_F_LO;e -1		.err;e 6+	-rr6=.inod=_W_PngO_ok(dentry->d_inod=, attA);	+M6f (-rr)	+NM{	/* 2 err;e+6876f(append)e{		attA->ia_val825&= ~ATTR_SIZE;68e	0x06814esctfs/nfsd/nfsproc.cce_fs/nfsd/nfsproc.c= ht_h"fs/nfsd/nfsproc.c0d0anDD1-04 18:48:24 p		.e		evice_fs/nfsd/nfsproc.c0d0anDD2-08 02:36:15 -		.e		(w,
540x26+540x26
-	{ ePROC(sym	ink,	 sym	inkar14,M8082,		none,		RC_REPLSTAT, ST),6} ePROC(mkdir,	 creD-aar14,Mdiropres,	fhandln,	RC_REPLBUFF, ST+FH+AT),6} ePROC(rmdir,	 diropar14,M8082,		none,		RC_REPLSTAT, ST),6- ePROC(readdir,	 readdirar14,Mreaddirres,	none,		RC_REPLBUFF, a),6+ ePROC(readdir,	 readdirar14,Mreaddirres,	none,		RC_NOCACHE, 0),e{ ePROC(statfs,	 fhandln,	statfsres,	none,		RC_NOCACHE, ST+5),6 };_ _	0x06814esctfs/nfsd/vfs.cce_fs/nfsd/vfs.c= ht_h"fs/nfsd/vfs.c0d0anDD1-20 21:02:13 p		.e		evice_fs/nfsd/vfs.c0d0anDD2-08 02:36:15 -		.e		(w,
656,120+656,156
-	{	dentry6=.fhp->fh_dentry;e -1	od= = dentry->d_inod=;e 	-	/* Disal		w access to files6with the append-only bit set or6-N * with mandatory 			king ena_led	+M/* Disal		w wriie access to files6with the append-only bit set	+	 * or any access w an mandatory 			king ena_led	 	F*/	X	-rr6=.nfserr_perm;e)N6f (IS_APPEND(inod=) || IS_ISMNDLK(inod=))	+M6f (IS_APPEND(inod=) && (access & MAY_WRITE))	{	1goto,out;6+	6f (IS_ISMNDLK(inod=))	+M1goto,out;6+aE	if (!inod=->i_fop)	{	1goto,out;6 _	0x06814esctfs/read_wriie.cce_fs/read_wriie.c= ht_h"fs/read_wriie.c0d0anDD1-25 20:29:40 p		.e		evice_fs/read_wriie.c0d0anDD2-03 10:18:50 -		.e		(w,
186,e4F+186,21

-	{1		.rw_ ti fy_area(1		.read_wriie, s0		0x0fileF*file, loff_t *ppos,	size_t count)R8{R_Ms,		0x01	od= *inod=;e+	loff_t pos216e)N6f (count >0file->f_maxcount)R-NM{	/* 2 -EINVAL;6+	6f (unlikely(count >0file->f_maxcount))	+M1goto,Einval21{	po4	= *ppos;6+	6f (unlikely((pos <e0) || (loff_t) (pos + count) <e0))	+M1goto,Einval21 e -1	od= = file->f_dentry->d_inod=;e M6f (inod=->i_fl		k && MANDATORY_LOCK(inod=))	-NM{	/* 2 l		ks_mandatory_area(read_wriie =={READ ? FLOCK_VERIFY_READ : FLOCK_VERIFY_WRITE, inod=, file, *ppos,	count);	+NM{	/* 2 l		ks_mandatory_area(read_wriie =={READ ? FLOCK_VERIFY_READ : FLOCK_VERIFY_WRITE, inod=, file, pos,	count);	{	366_chi0;	+	+Einval:_+	{	/* 2 -EINVAL;68}_ _ 8size_t do_sync_read(s0		0x0fileF*filp,	W_PCI__user5*buf,lsize_t len, loff_t *ppos)	(w,
220,665227,8

-	{		{	/* 2 -EBADF;_8M6f (!file->f_op || (!file->f_op->read && !file->f_op->aio_read))e{		{	/* 2 -EINVAL;6+	6f (unlikely(!access_ok(VERIFY_WRITE, buf,lcount)))	+NM{	/* 2 -EFAULT;e{	{	{	/ = rw_ ti fy_area(READ, file, pos,	count);	{	6f (!{	/)I{	(w,
266,665275,8

-	{		{	/* 2 -EBADF;_8M6f (!file->f_op || (!file->f_op->wriie && !file->f_op->aio_wriie))e{		{	/* 2 -EINVAL;6+	6f (unlikely(!access_ok(VERIFY_READ, buf,lcount)))	+NM{	/* 2 -EFAULT;e{	{	{	/ = rw_ ti fy_area(WRITE, file, pos,	count);	{	6f (!{	/)I{	(w,
397,,
+408,9
ER_U_ EXPORT_SYMBOL(iov_shorten)21 	+/* A wriie opera1ion does aLread from user5spain6and c in6pt36aL*/	+3_},
-	evrfy_dir(A_4,)F((*_4,)F=={READ ? VERIFY_WRITE : VERIFY_READ)eahE80D-/mL8size_t do_readv_wriiev(1		.A_4,,Ls0		0x0fileF*file,e{	11       ER_stL80		0x0iovecI__user5* uvector,e{	11       u6814ea7	},
- nr_se14, loff_t *pos)	(w,
450}8F+464}11

-	{	tot_len = 0;	{	{	/ = -EINVAL;687* 4 (sAU = 0; sAU < nr_se14; sAU+1) 81+1	80825__user5*buf =6iov[sAU].iov_base;	8		ssize_t len	= (ssize_t)iov[sAU].iov_len;	U6+-	6f (unlikely(!access_ok(vrfy_dir(A_4,), buf,llen)))	+-	,goto,E,ault216M	6f (len <e0)M/* size_t not fitting an,ssize_t ..F*/	X		1goto,out;6 		tot_len += len;	(w,
510,665527}90x148M	dnot fy_parent(file->f_dentry,e{	11M(A_4,	=={READ) ? DN_ACCESS : DN_MODIFY);e M{	/* 2 ret;6+E,ault:_+	{	/ = -EFAULT;e+1goto,out;6 }_ _ 8size_t vfs_readv(s0		0x0fileF*file, ER_stL80		0x0iovecI__user5*vec,_	0x06814esctfs/reiserfs/super.cce_fs/reiserfs/super.c= ht_h"fs/reiserfs/super.c0d0anDD1-07 21:44:20 p		.e		evice_fs/reiserfs/super.c0d0anDD2-03 06:42:39hp		.e		(w,
1835,9
+1835,11

-	{    inx0ret;6 
     /* We may creD-a quotaL80		0xure so wexneed to res.rve enough bl		ksL*/	+    reiserfs_wriie_			k(inod=->i_sb)21     jo* 2al_begin(&th, inod=->i_sb, 2*REISERFS_QUOTA_INIT_BLOCKS)21     {	/ = dquot_initialize(inod=, A_4,)21     jo* 2al_end(&th, inod=->i_sb, 2*REISERFS_QUOTA_INIT_BLOCKS)21+    reiserfs_wriie_un			k(inod=->i_sb)21     {	/* 2 ret;668_ e(w,
1847}90+1849,11

-	{    inx0ret;6 
     /* We may F%leieCquotaL80		0xure so wexneed to res.rve enough bl		ksL*/	+    reiserfs_wriie_			k(inod=->i_sb)21     jo* 2al_begin(&th, inod=->i_sb, 2*REISERFS_QUOTA_INIT_BLOCKS)21     {	/ = dquot_drop(inod=)21     jo* 2al_end(&th, inod=->i_sb, 2*REISERFS_QUOTA_INIT_BLOCKS)21+    reiserfs_wriie_un			k(inod=->i_sb)21     {	/* 2 ret;668_ e(w,
1858}90+1862,11

-	{    80		0x0reiserfs_transac-/on_handln th;	{    inx0ret;6 
+    reiserfs_wriie_			k(dquot->dq_sb)21     jo* 2al_begin(&th, dquot->dq_sb, REISERFS_QUOTA_TRANS_BLOCKS)21     {	/ = dquot_commit(dquot)21     jo* 2al_end(&th, dquot->dq_sb, REISERFS_QUOTA_TRANS_BLOCKS)21+    reiserfs_wriie_un			k(dquot->dq_sb)21     {	/* 2 ret;668_ e(w,
1869,9
+1875,11

-	{    80		0x0reiserfs_transac-/on_handln th;	{    inx0ret;6 
+    reiserfs_wriie_			k(dquot->dq_sb)21     jo* 2al_begin(&th, dquot->dq_sb, REISERFS_QUOTA_INIT_BLOCKS)21     {	/ = dquot_acquire(dquot)21     jo* 2al_end(&th, dquot->dq_sb, REISERFS_QUOTA_INIT_BLOCKS)21+    reiserfs_wriie_un			k(dquot->dq_sb)21     {	/* 2 ret;668_ e(w,
1880,9
+1888,11

-	{    80		0x0reiserfs_transac-/on_handln th;	{    inx0ret;6 
+    reiserfs_wriie_			k(dquot->dq_sb)21     jo* 2al_begin(&th, dquot->dq_sb, REISERFS_QUOTA_INIT_BLOCKS)21     {	/ = dquot_r%lease(dquot)21     jo* 2al_end(&th, dquot->dq_sb, REISERFS_QUOTA_INIT_BLOCKS)21+    reiserfs_wriie_un			k(dquot->dq_sb)21     {	/* 2 ret;668_ e(w,
1904,9
+1914,11

-	{    inx0ret;6 
     /* Di_d bl		k6+.i	od= bl		k6*/	+    reiserfs_wriie_			k(sb)21     jo* 2al_begin(&th, sb, 2)21     {	/ = dquot_commit_i
fo(sb, A_4,)21     jo* 2al_end(&th, sb, 2)21+    reiserfs_wriie_un			k(sb)21     {	/* 2 ret;668_ e(w,
1993},
+2005}90x148Mtocopy = sb->s_bl		ksize - offset < toread ? sb->s_bl		ksize - offset : toread;_2	tmp_bh.b_s1D-a = 0;	{	/* QuotaLfiles6are without tails so wexAan 8afely u{e this func-/onF*/	+	reiserfs_wriie_			k(sb)21 	-rr6=.reiserfs_gTO_b			k(inod=, blk, &tmp_bh,{0);_+	reiserfs_wriie_un			k(sb)21 M6f (-rr)	{	    {	/* 2 err;e{	6f (!bux0er_mapped(&tmp_bh))    /* A hole?F*/	(w,
2041}8F+2055x11

-	{	888 err6=.-EIO);{	888 goto,out;6 	}e+	lock_bux0er(bh);6 	memcpy(bh->b_si_d+offset, si_d, Aocopy);_+	flush_dcache_page(bh->b_page);_{MsTO_bux0er_uptosi_n(bh);6+W16lock_bux0er(bh);6 	reiserfs_prepare_* 4_jo* 2al(sb, bh,{1);6 	jo* 2al_mark_dirty(curr.
-->jo* 2al_i
fo, sb, bh);	{	6f (!jo* 2al_quota)e	0x06814esctfs/xfs/6___A-2.6/xfs_file.cce_fs/xfs/6___A-2.6/xfs_file.c= ht_h"fs/xfs/6___A-2.6/xfs_file.c0d0anDD1-24 17:15:18 p		.e		evice_fs/xfs/6___A-2.6/xfs_file.c0d0anDD2-07 18:25:10 -		.e		(w,
531,665531,76x0686880D-/mLs,		0x0vm_opera1ions_s0		0x06__vfs_file_vm_ops = {	}1.Fopage		= filemap_Fopage,6+1.populata	= filemap_populata,_ 0i,_}, HAVE_VMOP_MPROTECT	{	.mprotect	= 6__vfs_mprotect,	X,c62	}		0x06814esctincluF%/asm-arm/arch-pxa/pxa-re14.hce_incluF%/asm-arm/arch-pxa/pxa-re14.h= ht_h"incluF%/asm-arm/arch-pxa/pxa-re14.h0d0anDD2-01 		.46:37 p		.e		evice_incluF%/asm-arm/arch-pxa/pxa-re14.h0d0anDD2-06614:17:18 -		.e		(w,
444x265444x8

-	{L*/	 68/* FIXME: This clash6with SA1111 _},
-	sL*/	-3ifn_}, CONFIG_SA1111
+0i,n_}, _ASM_ARCH_SA1111
+	 3_},
-	eSACR01	__REG(0x40400000)  /* Global Control ReUTODMAL*/	 3_},
-	eSACR11	__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Just fied Control ReUTODMAL*/	 3_},
-	eSASR01	__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Just fied InDMAfain6and FIFO S0D-us6ReUTODMAL*/	(w,
452,4565453,3,
x0683_},
-	eSAICR1	__REG(0x40400018)  /* Serial Audio InDMArupt ClearcReUTODMAL*/	 3_},
-	eSADIV1	__REG(0x40400060)  /* Audio Cl		k6DividercReUTODMA.L*/	 3_},
-	eSADR1	__REG(0x40400080)  /* Serial Audio Di_d ReUTODMAL(TX6and RX FIFO access ReUTODMA).8*/e-,c62	}	 e)3_},
-	eSACR0_RFTH(x)	(x << 12)M	/* Rx FIFO InDMArupt or DMA TriggMALThresholdL*/	-3_},
-	eSACR0_TFTH(x)	(x << 8)M	/* Tx FIFO InDMArupt or DMA TriggMALThresholdL*/	-3_},
-	eSACR0_STRF		(1 << 5)M	/* FIFO Select * 4 EFWR Special Func-/onF*/	-3_},
-	eSACR0_EFWR		(1 << 4)M	/* Ena_leFEFWR Func-/onFF*/	-3_},
-	eSACR0_RST		(1 << 3)M	/* FIFO, i2s6ReUTODMALReset */	-3_},
-	eSACR0_BCKD		(1 << 2)8M	/* Bit Cl		k6Direc-/onF*/	-3_},
-	eSACR0_ENB		(1 << 0)M	/* Ena_leFI2S L__kF*/	-a-3_},
-	eSACR1_ENLBF		(1 << 5)M	/* Ena_leFLoopbackF*/	-3_},
-	eSACR1_DRPL		(1 << 4)8M	/* Disa_le Replaying Func-/onF*/	-3_},
-	eSACR1_DREC		(1 << 3)M	/* Disa_le Recording Func-/onF*/	-3_},
-	eSACR1_AMSL		(1 << 1)M	/* Specify AlDMAn ie Mod= */	-a-3_},
-	eSASR0_I2SOFF	(1 << 7)M	/* Controller S0D-us6*/	-3_},
-	eSASR0_ROR		(1 << 6)M	/* Rx FIFO OvMArun6*/	-3_},
-	eSASR0_TUR		(1 << 5)M	/* Tx FIFO Underrun6*/	-3_},
-	eSASR0_RFS		(1 << 4)M	/* Rx FIFO Serc in6R6quest6*/	-3_},
-	eSASR0_TFS		(1 << 3)M	/* Tx FIFO Serc in6R6quest6*/	-3_},
-	eSASR0_BSY		(1 << 2)
M/* I2S Busy6*/	-3_},
-	eSASR0_RNE		(1 << 1)M	/* Rx FIFO Not Empty6*/	-3_},
-	eSASR0_TNF		(1 << 0) M	/* Tx FIFO Not Empty6*/	-	-3_},
-	eSADIV_3_058M	0x0c	M	/* Serial Cl		k6Dividerc3.058MHz6*/	-3_},
-	eSADIV_2_836M	0x0d	M	/* 2.836 MHz6*/	-3_},
-	eSADIV_1_405M	0x1a	M	/* 1.405 MHz6*/	-3_},
-	eSADIV_1_026M	0x24	M	/* 1.026 MHz6*/	-3_},
-	eSADIV_702K		0x34	M	/* 702 kHz6*/	-3_},
-	eSADIV_513K		0x48	M	/* 513 kHz6*/	-	-3_},
-	eSAICR_ROR		(1 << 6)M	/* ClearcRx FIFO OvMArun6InDMArupt */	-3_},
-	eSAICR_TUR		(1 << 5)M	/* ClearcTx FIFO Underrun6InDMArupt */	-	-3_},
-	eSAIMR_ROR		(1 << 6)M	/* Ena_leFRx FIFO OvMArun6Condi-/onFInDMArupt */	-3_},
-	eSAIMR_TUR		(1 << 5)M	/* Ena_leFTx FIFO Underrun6Condi-/onFInDMArupt */	-3_},
-	eSAIMR_RFS		(1 << 4)M	/* Ena_leFRx FIFO Serc in6InDMArupt */	-3_},
-	eSAIMR_TFS		(1 << 3)M	/* Ena_leFTx FIFO Serc in6InDMArupt */	+3_},
-	eSACR0_RFTH(x)	(x << 12)M/* Rx FIFO InDMArupt or DMA TriggMALThresholdL*/	+3_},
-	eSACR0_TFTH(x)	(x << 8)M/* Tx FIFO InDMArupt or DMA TriggMALThresholdL*/	+3_},
-	eSACR0_STRF	(1 << 5)M/* FIFO Select * 4 EFWR Special Func-/onF*/	+3_},
-	eSACR0_EFWR	(1 << 4)M/* Ena_leFEFWR Func-/onFF*/	+3_},
-	eSACR0_RST	(1 << 3)M/* FIFO, i2s6ReUTODMALReset */	+3_},
-	eSACR0_BCKD	(1 << 2)8M/* Bit Cl		k6Direc-/onF*/	+3_},
-	eSACR0_ENB	(1 << 0)M/* Ena_leFI2S L__kF*/	+3_},
-	eSACR1_ENLBF	(1 << 5)M/* Ena_leFLoopbackF*/	+3_},
-	eSACR1_DRPL	(1 << 4)8M/* Disa_le Replaying Func-/onF*/	+3_},
-	eSACR1_DREC	(1 << 3)M/* Disa_le Recording Func-/onF*/	+3_},
-	eSACR1_AMSL	(1 << 1)M/* Specify AlDMAn ie Mod= */	+	+3_},
-	eSASR0_I2SOFF	(1 << 7)M/* Controller S0D-us6*/	+3_},
-	eSASR0_ROR	(1 << 6)M/* Rx FIFO OvMArun6*/	+3_},
-	eSASR0_TUR	(1 << 5)M/* Tx FIFO Underrun6*/	+3_},
-	eSASR0_RFS	(1 << 4)M/* Rx FIFO Serc in6R6quest6*/	+3_},
-	eSASR0_TFS	(1 << 3)M/* Tx FIFO Serc in6R6quest6*/	+3_},
-	eSASR0_BSY	(1 << 2)
/* I2S Busy6*/	+3_},
-	eSASR0_RNE	(1 << 1)M/* Rx FIFO Not Empty6*/	+3_},
-	eSASR0_TNF	(1 << 0) M/* Tx FIFO Not Empty6*/	+	+3_},
-	eSAICR_ROR	(1 << 6)M/* ClearcRx FIFO OvMArun6InDMArupt */	+3_},
-	eSAICR_TUR	(1 << 5)M/* ClearcTx FIFO Underrun6InDMArupt */	+	+3_},
-	eSAIMR_ROR	(1 << 6)M/* Ena_leFRx FIFO OvMArun6Condi-/onFInDMArupt */	+3_},
-	eSAIMR_TUR	(1 << 5)M/* Ena_leFTx FIFO Underrun6Condi-/onFInDMArupt */	+3_},
-	eSAIMR_RFS	(1 << 4)M/* Ena_leFRx FIFO Serc in6InDMArupt */	+3_},
-	eSAIMR_TFS	(1 << 3)M/* Ena_leFTx FIFO Serc in6InDMArupt */	 	+,c62	}	 68/*
 ,D AC97 Controller  eUTODMAs		0x06814esctincluF%/asm-frv/bitops.hce_incluF%/asm-frv/bitops.h= ht_h"incluF%/asm-frv/bitops.h0d0anDD1-04 18:48:09 p		.e		evice_incluF%/asm-frv/bitops.h0d0anDD2-04 06:24:36 -		.e		(w,
178}90+178,9
ER_U3_},
-	e,
-d_first_zero_bit(addr, size) \	         ,
-d_next_zero_bit((addr), (size),{0)R{;)80D-/mLinlMA_Finx0,
-d_next_zero_bit (80825* addr, inx0size, inx0offset)	+80D-/mLinlMA_Finx0,
-d_next_zero_bit(ER_stL80825*addr, inx0size, inx0offset)	 {	-Nu6814ea7	},
- *p = ((u6814ea7	},
- *) addr) + (offset >> 5);6+WER_stLu6814ea7	},
- *p = ((ER_stLu6814ea7	},
- *) addr) + (offset >> 5);6{	u6814ea7	},
- {	sult	= offset & ~31UL;6{	u6814ea7	},
- tmp;e{_(w,
277,11
+277,11
ER_U3_},
-	eext2_,
-d_first_zero_bit(addr, size) \	         ext2_,
-d_next_zero_bit((addr), (size),{0)R{;)80D-/mLinlMA_Fu6814ea7	},
- ext2_,
-d_next_zero_bit(80825*addr,	+80D-/mLinlMA_Fu6814ea7	},
- ext2_,
-d_next_zero_bit(ER_stL80825*addr,e{	11M1	    u6814ea7	},
- size,e{	11M1	    u6814ea7	},
- offset)	 {	-Nu6814ea7	},
- *p = ((u6814ea7	},
- *) addr) + (offset >> 5);6+WER_stLu6814ea7	},
- *p = ((ER_stLu6814ea7	},
- *) addr) + (offset >> 5);6{	u6814ea7	},
- {	sult	= offset & ~31UL;6{	u6814ea7	},
- tmp;e{_	0x06814esctincluF%/asm-frv/processor.hce_incluF%/asm-frv/processor.h= ht_h"incluF%/asm-frv/processor.h0d0anDD1-04 18:48:06 p		.e		evice_incluF%/asm-frv/processor.h0d0anDD2-04 07:33:28 -		.e		(w,
113x265113,76x06868extMAn asm	inkag_Finx0kernel_thread(inx0(*fn)(80825*),L80825* arg,Lu6814ea7	},
- *6514);_2extMAn asm	inkag_F80825save_user_re14(s,		0x0user_context *target)21-extMAn asm	inkag_F80825restore_user_re14(ER_stL80		0x0user_context *target)21+extMAn asm	inkag_F80825*restore_user_re14(ER_stL80		0x0user_context *target, ...);_2_83_},
-	ecopy_segmenxs(tsk, mm)M	do { } whileF(0)R{3_},
-	er%lease_segmenxs(mm)M	do { } whileF(0)R	0x06814esctincluF%/asm-frv/sysDMm.hce_incluF%/asm-frv/sysDMm.h= ht_h"incluF%/asm-frv/sysDMm.h0d0anDD1-04 18:48:06 p		.e		evice_incluF%/asm-frv/sysDMm.h0d0anDD2-04 08:12:47 -		.e		(w,
26,136526,16

-	{L* Th= `mb' isCto tell GCC not to,cache `curr.
-' across this call.	{L*/	 extMAn asm	inkag_
-80825__switch_to(s0		0x0thread_s0		0x0*pr%A	 s0		0x0thread_s0		0x0*next)21+s0		0x0task_s0		0x0*__switch_to(s0		0x0thread_s0		0x0*pr%A_thread,6+-	,1s0		0x0thread_s0		0x0*next_thread,6+-	,1s0		0x0task_s0		0x0*pr%A)21{e)3_},
-	eswitch_to(pr%A	 next, last)	11M1	\
-do {										\
-	pr%A->thread.sched_lr =6(16814ea7	},
-) __builtin_{	/* 2_address(0);	\
-	__switch_to(&pr%A->thread, &next->thread);				\
-	mb();									\
+3_},
-	eswitch_to(pr%A	 next, last)	11M1\
+do {									\
+	(pr%A)->thread.sched_lr =					\
+		(16814ea7	},
-) __builtin_{	/* 2_address(0);		\
+	(last) =6__switch_to(&(pr%A)->thread, &(next)->thread, (pr%A));	\
+	mb();								\	 } while(0)R{68/*
	0x06814esctincluF%/asm-frv/thread_i
fo.hce_incluF%/asm-frv/thread_i
fo.h= ht_h"incluF%/asm-frv/thread_i
fo.h0d0anDD1-04 18:48:06 p		.e		evice_incluF%/asm-frv/thread_i
fo.h0d0anDD2-04 04:29:39hp		.e		(w,
132}665132,,
x0683_},
-	eTIF_SINGLESTEP		4M/* restore singlestep on {	/* 2 to,user5mod= */	83_},
-	eTIF_IRET		5M/* re/* 2 with iret */	83_},
-	eTIF_POLLING_NRFLAG	16M/* 0		e if poll_idlO() is polling TIF_NEED_RESCHED */	+3_},
-	eTIF_MEMDIE		17M/* OOM killer5killed processL*/	 683_},
-	e_TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)683_},
-	e_TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)R	0x06814esctincluF%/asm-ia64/kre14.hce_incluF%/asm-ia64/kre14.h= ht_h"incluF%/asm-ia64/kre14.h0d0a4-12-10 13:25:43 p		.e		evice_incluF%/asm-ia64/kre14.h0d0anDD1-26 10:01:36 -		.e		(w,
14x26514x26
-	{ */	83_},
-	eIA64_KR_IO_BASE		0M/* ar.k0: legacy I/O base address */	83_},
-	eIA64_KR_TSSD		1M/* ar.k1: IVE,uses this as the TSSD */	-3_},
-	eIA64_KR_PA_CPU_INFO	3M/* ar.k3: phys addr of * is cpu's cpu_i
fo s0		0x0*/	+3_},
-	eIA64_KR_PER_CPU_DATA	3M/* ar.k3: physical,per-CPU base */	83_},
-	eIA64_KR_CURRENT_STACK	4M/* ar.k4: what's mapped0in IA64_TR_CURRENT_STACK */	83_},
-	eIA64_KR_FPU_OWNER	5M/* ar.k5: fpu-owner (UP only, at the momenx) */	83_},
-	eIA64_KR_CURRENT		6M/* ar.k6: "curr.
-"0task poinDMAL*/		0x06814esctincluF%/asm-ia64/mca.hce_incluF%/asm-ia64/mca.h= ht_h"incluF%/asm-ia64/mca.h0d0anDD1-07 13:54:29 p		.e		evice_incluF%/asm-ia64/mca.h0d0anDD1-26 10:01:37 -		.e		(w,
11}66511x8

-	{0i,n_}, _ASM_IA64_MCA_H683_},
-	e_ASM_IA64_MCA_H68	+3_},
-	eIA64_MCA_STACK_SIZE	8192
+	 3if !_},
-	d(__ASSEMBLY__)_ _ 0incluF% <6___A/inDMArupt.h>_(w,
102,21
+104,21

-	{	11M1	 */	8} ia64_mca_os_to_sal_s1D-a_t21{e)3_},
-	eIA64_MCA_STACK_SIZE 	1024	)3_},
-	eIA64_MCA_STACK_SIZE_BYTES 	(1024L* 8)	)3_},
-	eIA64_MCA_BSPSTORE_SIZE 	1024	)
-A_4,_}, 80		0x0ia64_mca_cpu_s {	-Nu64	ia64_mca_s1Dck[IA64_MCA_STACK_SIZE] 1	__attAibu-a__((al14ea7(16)));_-1u64	ia64_mca_proc_s1D-a_dump[512]	1	__attAibu-a__((al14ea7(16)));_-1u64	ia64_mca_s1Dckframe[32]	1		__attAibu-a__((al14ea7(16)));_-1u64	ia64_mca_bspstore[IA64_MCA_BSPSTORE_SIZE]	__attAibu-a__((al14ea7(16)));_-1u64	ia64_init_s1Dck[KERNE0_STACK_SIZE/8] 1	__attAibu-a__((al14ea7(16)));_-}0ia64_mca_cpu_t;6+/* Per-CPU MCA s1D-a that isCtoo big * 4 normal,per-CPU varia_les.  */	+	+80		0x0ia64_mca_cpu 81+1u64 s1Dck[IA64_MCA_STACK_SIZE/8];M/* MCA memory-s1DckF*/	+	u64 proc_s1D-a_dump[512];1+1u64 s1Dckframe[32];1+1u64 rbstore[IA64_MCA_STACK_SIZE/8];M/* MCA re1.-backing store */	+	u64 init_s1Dck[KERNE0_STACK_SIZE/8];1+} __attAibu-a__ ((al14ea7(16)));_{e)3_},
-	ePERCPU_MCA_SIZE sizeof(ia64_mca_cpu_t)	+/* Array of physical,addresses6of each CPU's MCA area.  */	+extMAn u6814ea7	},
- __per_cpu_mca[NR_CPUS];e e extMAn 80825ia64_mca_	nit(8082)21+extMAn 80825ia64_mca_cpu_i
it(80825*);_2extMAn 80825ia64_os_mca_dispatch(8082)212extMAn 80825ia64_os_mca_dispatch_end(8082)212extMAn 80825ia64_mca_ucmc_handlnr(8082)21	0x06814esctincluF%/asm-ia64/mca_asm.hce_incluF%/asm-ia64/mca_asm.h= ht_h"incluF%/asm-ia64/mca_asm.h0d0anDD1-06 16:22:36 -		.e		evice_incluF%/asm-ia64/mca_asm.h0d0anDD1-26 10:01:38 -		.e		(w,
46,40F+46}90x148Mmov	DMmp	= 0x7	;;							\	 	dep	addr	= DMmp, addr, 61, 3_{e)/D
- * This macro gets the physical,address of * is cpu's cpui
fo s0		0xure.
- */	-3_},
-	eGET_PERCPU_PADDR(re1)							\
-	mov	re1	= ar.k3;;						\
-	addl	re1	= IA64_CPUINFO_PERCPU_PADDR,re1	-	-3_},
-	eGET_CPUINFO_PAL_PADDR(re1)						\
-	mov	re1	= ar.k3;;						\
-	addl	re1	= IA64_CPUINFO_PAL_PADDR,re1	-	-/D
- * This macro gets the physical,address of * is cpu's MCA save s0		0xure.
- */	-3_},
-	eGET_CPUINFO_MCA_PADDR(re1)						\
-	mov	re1	= ar.k3;;						\
-	addl	re1	= IA64_CPUINFO_PA_MCA_INFO,re1;;			\
-	ld8	re1	= [re1]	-	-3_},
-		GET_MCA_BSPSTORE(re1)							\
-	GET_CPUINFO_MCA_PADDR(re1);;						\
-	addl	re1	= IA64_MCA_BSPSTORE,re1	-	-3_},
-		GET_MCA_STACKFRAME(re1)							\
-	GET_CPUINFO_MCA_PADDR(re1);;						\
-	addl	re1	= IA64_MCA_STACKFRAME,re1	-	-3_},
-		GET_MCA_STACK(re1)							\
-	GET_CPUINFO_MCA_PADDR(re1);;						\
-	addl	re1	= IA64_MCA_STACK,re1	-	-3_},
-		GET_MCA_DUMP_PADDR(re1)							\
-	GET_CPUINFO_MCA_PADDR(re1);;						\
-	addl	re1	= IA64_MCA_PROC_STATE_DUMP,re1	+3_},
-	eGET_THIS_PADDR(re1, var)		\
+	mov	re1 =eIA64_KR(PER_CPU_DATA);;	\	+        addl	re1 = THIS_CPU(var),leag	 68/*
 ,D This macro jumpsCto th_Fins0		0x/onFat the g/ven 8irtual,address1	0x06814esctincluF%/asm-ia64/page.hce_incluF%/asm-ia64/page.h= ht_h"incluF%/asm-ia64/page.h0d0anDD1-30 22320:53 p		.e		evice_incluF%/asm-ia64/page.h0d0anDD2-09 01:53:37 -		.e		(w,
79,26+79,8
x0683_},
-	eal		c_zeroed_user_highpage(vma, vaddr) \	 ({						\	 	80		0x0page *page =eal		c_page_vma(GFP_HIGHUSER | __GFP_ZERO, vma, vaddr); \
-	flush_dcache_page(page);		\
+	6f (page)				\
+2	Mflush_dcache_page(page);	\	 	page;					\	 })e{_	0x06814esctincluF%/asm-ia64/percpu.hce_incluF%/asm-ia64/percpu.h= ht_h"incluF%/asm-ia64/percpu.h0d0anDD1-06 16:23:02hp		.e		evice_incluF%/asm-ia64/percpu.h0d0anDD2-02 12:22:04hp		.e		(w,
56,8F+56,,
ER_UaE,c62	}M/* SMPL*/	 6-extMAn u6814ea7	},
- __per_cpu_mca[NR_CPUS];e-683_},
-	eEXPORT_PER_CPU_SYMBOL(var)		EXPORT_SYMBOL(per_cpu__##var)683_},
-	eEXPORT_PER_CPU_SYMBOL_GPL(var)		EXPORT_SYMBOL_GPL(per_cpu__##var)68_	0x06814esctincluF%/asm-ia64/processor.hce_incluF%/asm-ia64/processor.h= ht_h"incluF%/asm-ia64/processor.h0d0a4-12-10 13:24:20 p		.e		evice_incluF%/asm-ia64/processor.h0d0anDD1-26 10:01:41 -		.e		(w,
151,120+151,90x148M__u64 itc_freq;M	/* frequency of ITC	countMAL*/	 M__u64 proc_freq;M/* frequency of processorL*/	 M__u64 cyc_per_usec;M/* itc_freq/10000008*/e-	__u64 percpu_paddr;	 M__u64 ptce_base;	8	__u32 ptce_count[2];18	__u32 ptce_80	ide[2];1-	__u64 pal_paddr;	-	__u64 pal_base;	8	s0		0x0task_s0		0x0*ksoftirqd;M/* kernel softirq daemon * 4 * is CPU */	 683i,_}, CONFIG_SMP	(w,
177x265174,,
ER_U3i,_}, CONFIG_NUMAR_Ms,		0x01a64_nod=_si_d *nod=_si_d;	X,c62	}	-	__u64 *1a64_pa_mca_di_d;M/* prt to,MCA/INIT processorLs1D-a */	8};e e DECLARE_PER_CPU(s0		0x0cpui
fo_1a64, cpu_i
fo)21	0x06814esctincluF%/asm-ia64/sn/shubio.hce_incluF%/asm-ia64/sn/shubio.h= ht_/dev/null	Wa7	Dec 31 16:00:0081969e		evice_incluF%/asm-ia64/sn/shubio.h0d0anDD1-28 15:36:08 -		.e		(w,
0,06+1,347,
ER_+/*
+ * This fileFis subject to the tMAms6and condi-/ons of * e GNU General,Public
+ * License.  See the fileF"COPYING"0in t e main direc-ory of * is arch/ve
+ * * 4 more details.=+ *	+ * Copyright (C) 1992 - 1997, d0a0-d0a4 Silicon Graphics, Inc. All rights res.rved.
+ */	+	+3i,n_}, _ASM_IA64_SN_SHUBIO_H	+3_},
-	e_ASM_IA64_SN_SHUBIO_H	+	+3_},
-	eHUB_WIDGET_ID_MAX 0xf	+3_},
-	eIIO_NUM_ITTES   7	+3_},
-	eHUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)	+	+3_},
-	eeeeIIO_WID                   0x00400000    /* Crosstalk Widget Identifica-/onF*/	+                                                   /* This  eUTODMA is also accessi_leFfrom	+                                                    * Crosstalk at address 0x0.FF*/	+3_},
-	eeeeIIO_WSTAT                 0x00400008    /* Crosstalk Widget S0D-us6*/	+3_},
-	eeeeIIO_WCR                   0x00400020    /* Crosstalk Widget Control ReUTODMAL*/	+3_},
-	eeeeIIO_ILAPR                 0x00400100    /* IO Local,Access Protect/onFReUTODMAL*/	+3_},
-	eeeeIIO_ILAPO                 0x00400108    /* IO Local,Access Protect/onFOvMArid= */	+3_},
-	eeeeIIO_IOWA                  0x00400110    /* IO Outbound Widget Access */	+3_},
-	eeeeIIO_IIWA                  0x00400118    /* IO Inbound Widget Access */	+3_},
-	eeeeIIO_IIDEM                 0x00400120    /* IO Inbound Dec in6Err 4 Mask */	+3_},
-	eeeeIIO_ILCSR                 0x00400128    /* IO LLP Control and S0D-us6ReUTODMAL*/	+3_},
-	eeeeIIO_ILLR                  0x00400130    /* IO LLP Log6ReUTODMAL   */	+3_},
-	eeeeIIO_IIDSR                 0x00400138    /* IO InDMArupt Destin i/onF*/	+	+3_},
-	eeeeIIO_IGFX0                 0x00400140    /* IO Graphics Nod=-Widget Map 0 */	+3_},
-	eeeeIIO_IGFX1                 0x00400148    /* IO Graphics Nod=-Widget Map 1F*/	+	+3_},
-	eeeeIIO_ISCR0                 0x00400150    /* IO Scratch6ReUTODMAL0 */	+3_},
-	eeeeIIO_ISCR1                 0x00400158    /* IO Scratch6ReUTODMAL1F*/	+	+3_},
-	eeeeIIO_ITTE1                 0x00400160    /* IO Transl i/onFTa_leFEntry61 */	+3_},
-	eeeeIIO_ITTE2                 0x00400168    /* IO Transl i/onFTa_leFEntry62 */	+3_},
-	eeeeIIO_ITTE3                 0x00400170    /* IO Transl i/onFTa_leFEntry63 */	+3_},
-	eeeeIIO_ITTE4                 0x00400178    /* IO Transl i/onFTa_leFEntry64 */	+3_},
-	eeeeIIO_ITTE5                 0x00400180    /* IO Transl i/onFTa_leFEntry65 */	+3_},
-	eeeeIIO_ITTE6                 0x00400188    /* IO Transl i/onFTa_leFEntry66 */	+3_},
-	eeeeIIO_ITTE7                 0x00400190    /* IO Transl i/onFTa_leFEntry67F*/	+	+3_},
-	eeeeIIO_IPRB0                 0x00400198    /* IO PRBFEntry60         */	+3_},
-	eeeeIIO_IPRB8                 0x004001A0    /* IO PRBFEntry68         */	+3_},
-	eeeeIIO_IPRB9                 0x004001A8    /* IO PRBFEntry69         */	+3_},
-	eeeeIIO_IPRBA                 0x004001B0    /* IO PRBFEntry6A         */	+3_},
-	eeeeIIO_IPRBB                 0x004001B8    /* IO PRBFEntry6B         */	+3_},
-	eeeeIIO_IPRBC                 0x004001C0    /* IO PRBFEntry6C         */	+3_},
-	eeeeIIO_IPRBD                 0x004001C8    /* IO PRBFEntry6D         */	+3_},
-	eeeeIIO_IPRBE                 0x004001D0    /* IO PRBFEntry6E         */	+3_},
-	eeeeIIO_IPRBF                 0x004001D8    /* IO PRBFEntry6F         */	+	+3_},
-	eeeeIIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */	+3_},
-	eeeeIIO_IMEM                  0x004001E8    /* IO Miscellaneous6Err 4 Mask */	+3_},
-	eeeeIIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout ThresholdL*/	+3_},
-	eeeeIIO_IECLR                 0x004001F8    /* IO Err 4 ClearcReUTODMAL*/	+3_},
-	eeeeIIO_IBCR                  0x00400200    /* IO BTE Control ReUTODMAL*/	+	+3_},
-	eeeeIIO_IXSM                  0x00400208    /* IO Crosstalk Spurious6Message */	+3_},
-	eeeeIIO_IXSS                  0x00400210    /* IO Crosstalk Spurious6Sid=band */	+	+3_},
-	eeeeIIO_ILCT                  0x00400218    /* IO LLP Channel Test6   */	+	+3_},
-	eeeeIIO_IIEPH1                0x00400220    /* IO Incoming Err 4 Packet Header, Part61 */	+3_},
-	eeeeIIO_IIEPH2                0x00400228    /* IO Incoming Err 4 Packet Header, Part62 */	+	+	+3_},
-	eeeeIIO_ISLAPR                0x00400230    /* IO SXB Local,Access Protect/onFReUODMAL*/	+3_},
-	eeeeIIO_ISLAPO                0x00400238    /* IO SXB Local,Access Protect/onFOvMArid= */	+	+3_},
-	eeeeIIO_IWI                   0x00400240    /* IO Wrapper InDMArupt ReUTODMAL*/	+3_},
-	eeeeIIO_IWEL                  0x00400248    /* IO Wrapper Err 4 Log6ReUTODMAL*/	+3_},
-	eeeeIIO_IWC                   0x00400250    /* IO Wrapper Control ReUTODMAL*/	+3_},
-	eeeeIIO_IWS                   0x00400258    /* IO Wrapper S0D-us6ReUTODMAL*/	+3_},
-	eeeeIIO_IWEIM                 0x00400260    /* IO Wrapper Err 4 InDMArupt Masking ReUTODMAL*/	+	+3_},
-	eeeeIIO_IPCA                  0x00400300    /* IO PRBFCountMALAdjustF*/	+	+3_},
-	eeeeIIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Ta_leFEntry60, Part6A */	+3_},
-	eeeeIIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Ta_leFEntry61, Part6A */	+3_},
-	eeeeIIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Ta_leFEntry62, Part6A */	+3_},
-	eeeeIIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Ta_leFEntry63, Part6A */	+3_},
-	eeeeIIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Ta_leFEntry64, Part6A */	+3_},
-	eeeeIIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Ta_leFEntry65, Part6A */	+3_},
-	eeeeIIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Ta_leFEntry66, Part6A */	+3_},
-	eeeeIIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Ta_leFEntry67, Part6A */	+	+3_},
-	eeeeIIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Ta_leFEntry60, Part6B */	+3_},
-	eeeeIIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Ta_leFEntry61, Part6B */	+3_},
-	eeeeIIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Ta_leFEntry62, Part6B */	+3_},
-	eeeeIIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Ta_leFEntry63, Part6B */	+3_},
-	eeeeIIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Ta_leFEntry64, Part6B */	+3_},
-	eeeeIIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Ta_leFEntry65, Part6B */	+3_},
-	eeeeIIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Ta_leFEntry66, Part6B */	+3_},
-	eeeeIIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Ta_leFEntry67, Part6B */	+	+3_},
-	eeeeIIO_IPDR                  0x00400388    /* IO PIO Deal		cat/onFReUTODMAL*/	+3_},
-	eeeeIIO_ICDR                  0x00400390    /* IO CRBFEntry6Deal		cat/onFReUTODMAL*/	+3_},
-	eeeeIIO_IFDR                  0x00400398    /* IO IOQ FIFO DepthFReUTODMAL*/	+3_},
-	eeeeIIO_IIAP                  0x004003A0    /* IO IIQ Arbitra1ion Parametnrs */	+3_},
-	eeeeIIO_ICMR                  0x004003A8    /* IO CRBFManagemenx0ReUTODMAL*/	+3_},
-	eeeeIIO_ICCR                  0x004003B0    /* IO CRBFControl ReUTODMAL*/	+3_},
-	eeeeIIO_ICTO                  0x004003B8    /* IO CRBFTimeout         */	+3_},
-	eeeeIIO_ICTP                  0x004003C0    /* IO CRBFTimeout PrescalaAL*/	+	+3_},
-	eeeeIIO_ICRB0_A               0x00400400    /* IO CRBFEntry60_A       */	+3_},
-	eeeeIIO_ICRB0_B               0x00400408    /* IO CRBFEntry60_B       */	+3_},
-	eeeeIIO_ICRB0_C               0x00400410    /* IO CRBFEntry60_C       */	+3_},
-	eeeeIIO_ICRB0_D               0x00400418    /* IO CRBFEntry60_D       */	+3_},
-	eeeeIIO_ICRB0_E               0x00400420    /* IO CRBFEntry60_E       */	+	+3_},
-	eeeeIIO_ICRB1_A               0x00400430    /* IO CRBFEntry61_A       */	+3_},
-	eeeeIIO_ICRB1_B               0x00400438    /* IO CRBFEntry61_B       */	+3_},
-	eeeeIIO_ICRB1_C               0x00400440    /* IO CRBFEntry61_C       */	+3_},
-	eeeeIIO_ICRB1_D               0x00400448    /* IO CRBFEntry61_D       */	+3_},
-	eeeeIIO_ICRB1_E               0x00400450    /* IO CRBFEntry61_E       */	+	+3_},
-	eeeeIIO_ICRB2_A               0x00400460    /* IO CRBFEntry62_A       */	+3_},
-	eeeeIIO_ICRB2_B               0x00400468    /* IO CRBFEntry62_B       */	+3_},
-	eeeeIIO_ICRB2_C               0x00400470    /* IO CRBFEntry62_C       */	+3_},
-	eeeeIIO_ICRB2_D               0x00400478    /* IO CRBFEntry62_D       */	+3_},
-	eeeeIIO_ICRB2_E               0x00400480    /* IO CRBFEntry62_E       */	+	+3_},
-	eeeeIIO_ICRB3_A               0x00400490    /* IO CRBFEntry63_A       */	+3_},
-	eeeeIIO_ICRB3_B               0x00400498    /* IO CRBFEntry63_B       */	+3_},
-	eeeeIIO_ICRB3_C               0x004004a0    /* IO CRBFEntry63_C       */	+3_},
-	eeeeIIO_ICRB3_D               0x004004a8    /* IO CRBFEntry63_D       */	+3_},
-	eeeeIIO_ICRB3_E               0x004004b0    /* IO CRBFEntry63_E       */	+	+3_},
-	eeeeIIO_ICRB4_A               0x004004c0    /* IO CRBFEntry64_A       */	+3_},
-	eeeeIIO_ICRB4_B               0x004004c8    /* IO CRBFEntry64_B       */	+3_},
-	eeeeIIO_ICRB4_C               0x004004d0    /* IO CRBFEntry64_C       */	+3_},
-	eeeeIIO_ICRB4_D               0x004004d8    /* IO CRBFEntry64_D       */	+3_},
-	eeeeIIO_ICRB4_E               0x004004e0    /* IO CRBFEntry64_E       */	+	+3_},
-	eeeeIIO_ICRB5_A               0x004004f0    /* IO CRBFEntry65_A       */	+3_},
-	eeeeIIO_ICRB5_B               0x004004f8    /* IO CRBFEntry65_B       */	+3_},
-	eeeeIIO_ICRB5_C               0x00400500    /* IO CRBFEntry65_C       */	+3_},
-	eeeeIIO_ICRB5_D               0x00400508    /* IO CRBFEntry65_D       */	+3_},
-	eeeeIIO_ICRB5_E               0x00400510    /* IO CRBFEntry65_E       */	+	+3_},
-	eeeeIIO_ICRB6_A               0x00400520    /* IO CRBFEntry66_A       */	+3_},
-	eeeeIIO_ICRB6_B               0x00400528    /* IO CRBFEntry66_B       */	+3_},
-	eeeeIIO_ICRB6_C               0x00400530    /* IO CRBFEntry66_C       */	+3_},
-	eeeeIIO_ICRB6_D               0x00400538    /* IO CRBFEntry66_D       */	+3_},
-	eeeeIIO_ICRB6_E               0x00400540    /* IO CRBFEntry66_E       */	+	+3_},
-	eeeeIIO_ICRB7_A               0x00400550    /* IO CRBFEntry67_A       */	+3_},
-	eeeeIIO_ICRB7_B               0x00400558    /* IO CRBFEntry67_B       */	+3_},
-	eeeeIIO_ICRB7_C               0x00400560    /* IO CRBFEntry67_C       */	+3_},
-	eeeeIIO_ICRB7_D               0x00400568    /* IO CRBFEntry67_D       */	+3_},
-	eeeeIIO_ICRB7_E               0x00400570    /* IO CRBFEntry67_E       */	+	+3_},
-	eeeeIIO_ICRB8_A               0x00400580    /* IO CRBFEntry68_A       */	+3_},
-	eeeeIIO_ICRB8_B               0x00400588    /* IO CRBFEntry68_B       */	+3_},
-	eeeeIIO_ICRB8_C               0x00400590    /* IO CRBFEntry68_C       */	+3_},
-	eeeeIIO_ICRB8_D               0x00400598    /* IO CRBFEntry68_D       */	+3_},
-	eeeeIIO_ICRB8_E               0x004005a0    /* IO CRBFEntry68_E       */	+	+3_},
-	eeeeIIO_ICRB9_A               0x004005b0    /* IO CRBFEntry69_A       */	+3_},
-	eeeeIIO_ICRB9_B               0x004005b8    /* IO CRBFEntry69_B       */	+3_},
-	eeeeIIO_ICRB9_C               0x004005c0    /* IO CRBFEntry69_C       */	+3_},
-	eeeeIIO_ICRB9_D               0x004005c8    /* IO CRBFEntry69_D       */	+3_},
-	eeeeIIO_ICRB9_E               0x004005d0    /* IO CRBFEntry69_E       */	+	+3_},
-	eeeeIIO_ICRBA_A               0x004005e0    /* IO CRBFEntry6A_A       */	+3_},
-	eeeeIIO_ICRBA_B               0x004005e8    /* IO CRBFEntry6A_B       */	+3_},
-	eeeeIIO_ICRBA_C               0x004005f0    /* IO CRBFEntry6A_C       */	+3_},
-	eeeeIIO_ICRBA_D               0x004005f8    /* IO CRBFEntry6A_D       */	+3_},
-	eeeeIIO_ICRBA_E               0x00400600    /* IO CRBFEntry6A_E       */	+	+3_},
-	eeeeIIO_ICRBB_A               0x00400610    /* IO CRBFEntry6B_A       */	+3_},
-	eeeeIIO_ICRBB_B               0x00400618    /* IO CRBFEntry6B_B       */	+3_},
-	eeeeIIO_ICRBB_C               0x00400620    /* IO CRBFEntry6B_C       */	+3_},
-	eeeeIIO_ICRBB_D               0x00400628    /* IO CRBFEntry6B_D       */	+3_},
-	eeeeIIO_ICRBB_E               0x00400630    /* IO CRBFEntry6B_E       */	+	+3_},
-	eeeeIIO_ICRBC_A               0x00400640    /* IO CRBFEntry6C_A       */	+3_},
-	eeeeIIO_ICRBC_B               0x00400648    /* IO CRBFEntry6C_B       */	+3_},
-	eeeeIIO_ICRBC_C               0x00400650    /* IO CRBFEntry6C_C       */	+3_},
-	eeeeIIO_ICRBC_D               0x00400658    /* IO CRBFEntry6C_D       */	+3_},
-	eeeeIIO_ICRBC_E               0x00400660    /* IO CRBFEntry6C_E       */	+	+3_},
-	eeeeIIO_ICRBD_A               0x00400670    /* IO CRBFEntry6D_A       */	+3_},
-	eeeeIIO_ICRBD_B               0x00400678    /* IO CRBFEntry6D_B       */	+3_},
-	eeeeIIO_ICRBD_C               0x00400680    /* IO CRBFEntry6D_C       */	+3_},
-	eeeeIIO_ICRBD_D               0x00400688    /* IO CRBFEntry6D_D       */	+3_},
-	eeeeIIO_ICRBD_E               0x00400690    /* IO CRBFEntry6D_E       */	+	+3_},
-	eeeeIIO_ICRBE_A               0x004006a0    /* IO CRBFEntry6E_A       */	+3_},
-	eeeeIIO_ICRBE_B               0x004006a8    /* IO CRBFEntry6E_B       */	+3_},
-	eeeeIIO_ICRBE_C               0x004006b0    /* IO CRBFEntry6E_C       */	+3_},
-	eeeeIIO_ICRBE_D               0x004006b8    /* IO CRBFEntry6E_D       */	+3_},
-	eeeeIIO_ICRBE_E               0x004006c0    /* IO CRBFEntry6E_E       */	+	+3_},
-	eeeeIIO_ICSML                 0x00400700    /* IO CRBFSpurious6Message Low */	+3_},
-	eeeeIIO_ICSMM                 0x00400708    /* IO CRBFSpurious6Message Middln */	+3_},
-	eeeeIIO_ICSMH                 0x00400710    /* IO CRBFSpurious6Message High */	+	+3_},
-	eeeeIIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */	+	+3_},
-	eeeeIIO_IBLS0                 0x00410000    /* IO BTE Length S0D-us60 */	+3_},
-	eeeeIIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */	+3_},
-	eeeeIIO_IBDA0                 0x00410010    /* IO BTE Destin i/onFAddress 0 */	+3_},
-	eeeeIIO_IBCT0                 0x00410018    /* IO BTE Control Termin ie 0 */	+3_},
-	eeeeIIO_IBNA0                 0x00410020    /* IO BTE Notifica-/onFAddress 0 */	+3_},
-	eeeeIIO_IBIA0                 0x00410028    /* IO BTE InDMArupt Address 0 */	+3_},
-	eeeeIIO_IBLS1                 0x00420000    /* IO BTE Length S0D-us61 */	+3_},
-	eeeeIIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */	+3_},
-	eeeeIIO_IBDA1                 0x00420010    /* IO BTE Destin i/onFAddress 1 */	+3_},
-	eeeeIIO_IBCT1                 0x00420018    /* IO BTE Control Termin ie 1 */	+3_},
-	eeeeIIO_IBNA1                 0x00420020    /* IO BTE Notifica-/onFAddress 1 */	+3_},
-	eeeeIIO_IBIA1                 0x00420028    /* IO BTE InDMArupt Address 1L*/	+	+3_},
-	eeeeIIO_IPCR                  0x00430000    /* IO Performance Control */	+3_},
-	eeeeIIO_IPPR                  0x00430008    /* IO Performance Profiling */	+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA echoes som_Finforma-/onFfrom t e         *	+ * LB_REV_ID  eUTODMA. It isCavaila_leFthrough Crosstalk as described   *	+ * above. Th= REV_NUM and MFG_NUM fields  eceive their values from      *	+ * th= REVISION and MANUFACTURER fields in t e LB_REV_ID  eUTODMA.      *	+ * Th= PART_NUM field's value isCth= Crosstalk dec in6ID number that    *	+ * Steve Miller5as814ea7	to the SHub chip.                              *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_wid_u 81+1uint64_t	ii_wid_ eUval;1+1s0		0x	81+11uint64_t	w_rsvd_11	  :	 1;1+11uint64_t	w_mfg_num1	  :	11;1+11uint64_t	w_part_num1	  :	16;1+11uint64_t	w_r%A_num1	  :	 4;1+11uint64_t	w_rsvd	1	  :	32;1+1}Fii_wid_fld_s;1+} ii_wid_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Th= fields in t is  eUTODMA are set uponFdetect/onFof an error      *	+ * and cleara7	by various6mechanisms, as expla
-	d in t e               *	+ * descrip-/on.                                                         *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ws1D-_u 81+1uint64_t	ii_ws1D-_ eUval;1+1s0		0x	81+11uint64_t	w_pc62	ng1	  :	 4;1+11uint64_t	w_xt_crd_to1	  :	 1;1+11uint64_t	w_xt_tail_to1	  :	 1;1+11uint64_t	w_rsvd_31	  :	 3;1+11uint64_t       w_tx_mx_rty               :      1;1+11uint64_t	w_rsvd_21	  :	 6;1+11uint64_t	w_llp_tx_cnt1	  :	 8;1+11uint64_t	w_rsvd_11	  :	 8;1+11uint64_t	w_crazy	1	  :	 1;1+11uint64_t	w_rsvd	1	  :	31;1+1}Fii_ws1D-_fld_s;1+} ii_ws1D-_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This isCa read-wriie ena_led  eUTODMA. It controls     *	+ * various6aspects of * e Crosstalk flow control.                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_wcr_u 81+1uint64_t	ii_wcr_ eUval;1+1s0		0x	81+11uint64_t	w_wid	1	  :	 4;1+11uint64_t	w_tag	1	  :	 1;1+11uint64_t	w_rsvd_11	  :	 8;1+11uint64_t	w_dst_crd1	  :	 3;1+11uint64_t	w_f_bad_pkt1	  :	 1;1+11uint64_t	w_dir_con1	  :	 1;1+11uint64_t	w_e_thresh1	  :	 5;1+11uint64_t	w_rsvd	1	  :	41;1+1}Fii_wcr_fld_s;1+} ii_wcr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA's value isCa bit vec-or that guards      *	+ * access to local, eUTODMAs within t e II as well as to extMAnal,      *	+ * Crosstalk widgets. Each bit in t e  eUTODMA corresponds to a         *	+ * particulaAL eUTonFin t e sysDMm;Ca reUTonFER_sTODs of one, two or    *
+ * * u4 nodes (depc62	ng on t e value of * e REGION_SIZE field in t e   *	+ * LB_REV_ID  eUTODMA, which isCdocumenx	d in Sect/onF8.3.1.1). Th=     *	+ * protect/onFprovide7	by t is  eUTODMA applies to PIO read             *	+ * opera1ions as well as PIO wriie opera1ions. Th= II will perform a    *	+ * PIO read or wriie r6quest6only if t e bit * 4 * e r6questoA's        *	+ *  eUTonFis set; o* erwise, th= II will not perform * e r6quested      *	+ * opera1ion and will re/* 2 an error response. Whe2 a PIO read or      *	+ * wriie r6quest6targets an extMAnal,Crosstalk widget, th=n not only    *	+ * mustFt e bit * 4 * e r6questoA's  eUTonFbe set in t e ILAPR, but     *	+ * also the target widget's bit in t e IOWA  eUTODMA mustFbe set in     *	+ * orderc* 4 * e II to perform * e r6quested opera1ion; o* erwise,      *	+ * th= II will re/* 2 an error response. Hence, th= protect/onF         *	+ * provide7	by t e IOWA  eUTODMA supplemenxs th= protect/onFprovide7	   *	+ * by t e ILAPR for requests that target extMAnal,Crosstalk widgets.    *	+ * This  eUTODMA itself canFbe accessed only by t e nodes whose         *	+ *  eUTonFID bits are ena_led in t is same  eUTODMA. It canFalso be     *	+ * accessa7	through t e IAlias spain6by t e local,processors.           *	+ * T e r6set value of * is  eUTODMA allows access by all nodes.         *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ilapr_u 81+1uint64_t	ii_ilapr_ eUval;1+1s0		0x  81+11uint64_t	i_ eUTonFFFFFFFFFFFFFFFFFF:	64;1+1}Fii_ilapr_fld_s;1+} ii_ilapr_u_t;6+	+	+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  A wriie to this  eUTODMA of * e 64-bit value           *	+ * "SGIrules"0in ASCII, will causeFt e bit in t e ILAPR  eUTODMA        *	+ * correspond	ng to the  eUTonFof * e r6questoA to be set (allow        *	+ * access). A wriie of any o* er value will be ignora7.,Access          *	+ * protect/onF* 4 * is  eUTODMA is "SGIrules".                          *	+ * This  eUTODMA canFalso be accessa7	through t e IAlias spain.         *	+ * HowevMA, * is access will not changeFt e access permissions in t e   *	+ * ILAPR.                                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ilapo_u 81+1uint64_t	ii_ilapo_ eUval;1+1s0		0x	81+11uint64_t	i_io_ovArid= FFFFFFFFFFF:	64;1+1}Fii_ilapo_fld_s;1+} ii_ilapo_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA qualifies all t e PIO and Graphics wriies launched    *
+ * *rom t e SHUB towards a widget.                                      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iowa_u 81+1uint64_t	ii_iowa_ eUval;1+1s0		0x	81+11uint64_t	i_w0_oac1	  :	 1;1+11uint64_t	i_rsvd_11	  :	 7;	+                uint64_t       i_wx_oacFFFFFFFFFFFFFFFFFF:FFFFFF8;1+11uint64_t	i_rsvd	1	  :	48;1+1}Fii_iowa_fld_s;1+} ii_iowa_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA qualifies all t e requests launched      *
+ * *rom a widget towards t e Shub. This  eUTODMA is inDMnda7	to be      *
+ * use7	by software in case of misbehav	ng widgets.                     *	+ *                                                                      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iiwa_u 81+1uint64_t	ii_iiwa_ eUval;1+1s0		0x  81+11uint64_t	i_w0_iacFFFFFFFFFFFFFFFFFF:	 1;1+11uint64_t	i_rsvd_11	  :	 7;	+11uint64_t	i_wx_iac1	  :	 8;1+11uint64_t	i_rsvd	1	  :	48;1+1}Fii_iiwa_fld_s;1+} ii_iiwa_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA qualifies all t e opera1ions launched    *
+ * *rom a widget towards t e SHub. It allows ind	vidual,access          *	+ * controlF* 4 up	to 8 dec ins per widget. A dec in6refMAs to           *	+ * ind	vidual,DMA maODMA hoste7	by a widget.                            *	+ * T e bits in each field of * is  eUTODMA are cleara7	by t e Shub      *
+ * uponFdetect/onFof an error which requires t e dec in6to be           *	+ * disa_led. Th=s= fields assuma that 0=TNUM=7 (i.e., Bridge-cenxric    *	+ * Crosstalk). Whe* er  4 not a dec in6has access rights to this        *	+ * Shub isCdetnrm
-	d by an ANDFof * e dec in6ena_le bit in t e         *	+ * appropri ie field of * is  eUTODMA and t e correspond	ng bit in      *	+ * th= Wx_IAC field (* 4 * e widget which * is dec in6be},
-s to).      *	+ * T e bits in this field are set by wrii	ng a 1 to them. Incoming      *	+ *  eplies *rom Crosstalk are not subject to this access controlF       *	+ * mechanism.                                                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iidem_u 81+1uint64_t	ii_iidem_ eUval;1+1s0		0x	81+11uint64_t	i_w8_dxs1	  :	 8;1+11uint64_t	i_w9_dxs1	  :	 8;1+11uint64_t	i_wa_dxs1	  :	 8;1+11uint64_t	i_wb_dxs1	  :	 8;1+11uint64_t	i_wc_dxs1	  :	 8;1+11uint64_t	i_wd_dxs1	  :	 8;1+11uint64_t	i_we_dxs1	  :	 8;1+11uint64_t	i_wf_dxs1	  :	 8;1+1}Fii_iidem_fld_s;1+} ii_iidem_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e various6programma_le fields necessary    *
+ * * r controlling and obs.rv	ng t e LLP 814eals.                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ilcsr_u 81+1uint64_t	ii_ilcsr_ eUval;1+1s0		0x  81+11uint64_t	i_nullto           FFFFFFF:	 6;1+11uint64_t	i_rsvd_41	  :	 2;1+11uint64_t	i_wrmrst1	  :	 1;1+11uint64_t	i_rsvd_31	  :	 1;1+11uint64_t	i_llp_en1	  :	 1;1+11uint64_t	i_bm8	1	  :	 1;1+11uint64_t	i_llp_s1D-1	  :	 2;1+11uint64_t	i_remote_power1	  :	 1;1+11uint64_t	i_rsvd_21	  :	 1;1+11uint64_t	i_maxrtry1	  :	10;1+11uint64_t	i_d_avail_sel1	  :	 2;1+11uint64_t	i_rsvd_11	  :	 4;1+11uint64_t	i_maxbrst1	  :	10;1+                uint64_t       i_rsvd                    :FFFFF22;6+	+1}Fii_ilcsr_fld_s;1+} ii_ilcsr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This is simply a s0D-us6 eUTODMAs that monitors t e LLP error       *	+ *   ie.                                                                *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_illr_u 81+1uint64_t	ii_illr_ eUval;1+1s0		0x	81+11uint64_t	i_sn_cnt1	  :	16;1+11uint64_t	i_cb_cnt1	  :	16;1+11uint64_t	i_rsvd	1	  :	32;1+1}Fii_illr_fld_s;1+} ii_illr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  All II-detect	d non-BTE error inDMArupts are           *	+ * specified via * is  eUTODMA.                                         *	+ * NOTE: Th= PI inDMArupt  eUTODMA address is hardcod	d in t e II. If   *	+ * PI_ID==0, th=n th= II sends an inDMArupt  equest6(Dup},
et PWRI      *	+ * packet) to address offset 0x0180_0090 within t e local, eUTODMA      *	+ * address spain6of PI0 on t e node specified by t e NODE field. If     *	+ * PI_ID==1, th=n th= II sends th_FinDMArupt  equest6to address         *	+ * offset 0x01A0_0090 within t e local, eUTODMA address spain6of PI1    *	+ * on t e node specified by t e NODE field.                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iidsr_u 81+1uint64_t	ii_iidsr_ eUval;1+1s0		0x  81+11uint64_t	i_level            FFFFFFF:	 8;1+11uint64_t	i_pi_id	1	  :	 1;1+11uint64_t	i_node	1	  :	11;1+11uint64_t       i_rsvd_3FFFFFFFFFFFFFFFFFF:FFFFFF4;1+11uint64_t	i_ena_le1	  :	 1;1+11uint64_t	i_rsvd_21	  :	 3;1+11uint64_t	i_int_sen-1	  :	 2;1+11uint64_t       i_rsvd_1FFFFFFFFFFFFFFFFFF:FFFFFF2;1+11uint64_t	i_pi0_* rward_int	  :	 1;1+11uint64_t	i_pi1_* rward_int	  :	 1;1+11uint64_t	i_rsvd	1	  :	30;1+1}Fii_iidsr_fld_s;1+} ii_iidsr_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ *  There are two ins0ances of * is  eUTODMA. This  eUTODMA is use7	    *
+ * * r match	ng up	th_Fincoming responses *rom t e graphics widget to   *	+ * th= processorLthat initi ied t e graphics opera1ion. Th=             *	+ * wriie-responses are converta7	to graphics credits6and re/* 2a7	to    *	+ * th= processorLso that the processorLinDMAfain6canFmanage the flow    *	+ * control.                                                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_igfx0_u 81+1uint64_t	ii_igfx0_ eUval;1+1s0		0x	81+11uint64_t	i_w_num1		  :	 4;1+11uint64_t       i_pi_id                   :FFFFF 1;1+11uint64_t	i_n_num1		  :	12;1+11uint64_t       i_p_num                   :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF46;1+1}Fii_igfx0_fld_s;1+} ii_igfx0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Th=re are two ins0ances of * is  eUTODMA. This  eUTODMA is use7	    *
+ * * r match	ng up	th_Fincoming responses *rom t e graphics widget to   *	+ * th= processorLthat initi ied t e graphics opera1ion. Th=             *	+ * wriie-responses are converta7	to graphics credits6and re/* 2a7	to    *	+ * th= processorLso that the processorLinDMAfain6canFmanage the flow    *	+ * control.                                                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_igfx1_u 81+1uint64_t	ii_igfx1_ eUval;1+1s0		0x  81+11uint64_t	i_w_num1		  :	 4;1+11uint64_t       i_pi_id                   :FFFFF 1;1+11uint64_t	i_n_num1		  :	12;1+11uint64_t       i_p_num                   :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF46;1+1}Fii_igfx1_fld_s;1+} ii_igfx1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Th=re are two ins0ances of * is  eUTODMAs. Th=s=  eUTODMAs are      *
+ * use7	as scratch6 eUTODMAs forLsoftware use.                          *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iscr0_u 81+1uint64_t	ii_iscr0_ eUval;1+1s0		0x  81+11uint64_t	i_scratch6FFFFFFFFFFFFFFFF:	64;1+1}Fii_iscr0_fld_s;1+} ii_iscr0_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ *  There are two ins0ances of * is  eUTODMAs. Th=s=  eUTODMAs are      *
+ * use7	as scratch6 eUTODMAs forLsoftware use.                          *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iscr1_u 81+1uint64_t	ii_iscr1_ eUval;1+1s0		0x  81+11uint64_t	i_scratch6FFFFFFFFFFFFFFFF:	64;1+1}Fii_iscr1_fld_s;1+} ii_iscr1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a Shub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the SHub is thus t e lowMAL16 GBytes per widget       * 	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the Shub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte1_u 81+1uint64_t	ii_itte1_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t	i_w_num1		  :	 4;1+11uint64_t	i_iosp			  :	 1;1+11uint64_t	i_rsvd	1	  :	51;1+1}Fii_itte1_fld_s;1+} ii_itte1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a Shub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the Shub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the Shub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte2_u 81+1uint64_t	ii_itte2_ eUval;1+1s0		0x	81+11uint64_t	i_offset1	  :	 5;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t	i_w_num1		  :	 4;1+11uint64_t	i_iosp			  :	 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte2_fld_s;1+} ii_itte2_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a Shub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the Shub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the SHub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte3_u 81+1uint64_t	ii_itte3_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t       i_rsvd_1FFFFFFFFFFFFFFFFFF:FFFFFF3;1+11uint64_t       i_w_num                   :FFFFF 4;1+11uint64_t       i_iosp                    :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte3_fld_s;1+} ii_itte3_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a SHub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the SHub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the SHub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte4_u 81+1uint64_t	ii_itte4_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t       i_w_num                   :FFFFF 4;1+11uint64_t       i_iosp                    :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte4_fld_s;1+} ii_itte4_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a SHub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the Shub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the Shub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte5_u 81+1uint64_t	ii_itte5_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t       i_rsvd_1FFFFFFFFFFFFFFFFFF:FFFFFF3;1+11uint64_t       i_w_num                   :FFFFF 4;1+11uint64_t       i_iosp                    :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte5_fld_s;1+} ii_itte5_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a Shub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the Shub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the Shub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte6_u 81+1uint64_t	ii_itte6_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t       i_rsvd_1FFFFFFFFFFFFFFFFFF:FFFFFF3;1+11uint64_t       i_w_num                   :FFFFF 4;1+11uint64_t       i_iosp                    :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte6_fld_s;1+} ii_itte6_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are seven ins0ances of *ransl i/onFta_le entry6  *	+ *  eUTODMAs. Each  eUTODMA maps a Shub Big Window to a 48-bit          *	+ * address on Crosstalk.                                                *	+ * F 4 M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *	+ * number) are use7	to select one of * es= 7  eUTODMAs. Th= Widget      *	+ * number field is th=n derive7	*rom t e W_NUM field forLsyn* esizing   *	+ * a Crosstalk packet. Th= 5 bits of OFFSET are conc ien ied with       *	+ * SysAD[28:0]	to form Crosstalk[33:0]. Th= upper Crosstalk[47:34]      *	+ * are padded with zeros. Although t e maximum Crosstalk spain6         *	+ * addressa_le by the Shub is thus t e lowMAL16 GBytes per widget       *	+ * (M-mode), howevMA only <SUP >7</SUP>/<SUB >32nds</SUB> of * is       *	+ * spain6canFbe accessa7.                                               *	+ * F 4 t e N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *	+ * Window number) are use7	to select one of * es= 7  eUTODMAs. Th=      *	+ * Widget number field is th=n derive7	*rom t e W_NUM field forL        *	+ * syn* esizing a Crosstalk packet. Th= 5 bits of OFFSET are            *	+ * conc ien ied with SysAD[27:0]	to form Crosstalk[33:0]. Th= IOSP      *
+ * *ield is use7	as Crosstalk[47],6and remaindMA of * e Crosstalk       *	+ * address bits (Crosstalk[46:34]) are always zero. While t e maximum   *	+ * Crosstalk spain6addressa_le by the SHub is thus t e lowMAL           *	+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *	+ * of t is spain6canFbe accessa7.                                       *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_itte7_u 81+1uint64_t	ii_itte7_ eUval;1+1s0		0x  81+11uint64_t	i_offset           FFFFFFF:	 5;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t       i_w_num                   :FFFFF 4;1+11uint64_t       i_iosp                    :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_itte7_fld_s;1+} ii_itte7_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprb0_u 81+1uint64_t	ii_iprb0_ eUval;1+1s0		0x  81+11uint64_t	i_c                       :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t       i_rsvd_2                  :FFFFF 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprb0_fld_s;1+} ii_iprb0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprb8_u 81+1uint64_t	ii_iprb8_ eUval;1+1s0		0x  81+11uint64_t	i_c                       :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t       i_rsvd_2                  :FFFFF 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t       i_rsvd_1FFFFFFFFFFFFFFFFFF:FFFFFF2;1+11uint64_t       i_m                       :FFFFFF2;1+11uint64_t       i_f                       :FFFFFF1;1+11uint64_t       i_of_cnt                  :FFFFFF5;1+11uint64_t       i_error                   :FFFFF 1;1+11uint64_t       i_rd_to                   :FFFFF 1;1+11uint64_t       i_spur_wr                 :FFFFF 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t       i_rsvd                    :FFFFF11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprb8_fld_s;1+} ii_iprb8_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprb9_u 81+1uint64_t	ii_iprb9_ eUval;1+1s0		0x	81+11uint64_t	i_c	1	  :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprb9_fld_s;1+} ii_iprb9_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.        *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ *                                                                      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprba_u 81+1uint64_t	ii_iprba_ eUval;1+1s0		0x  81+11uint64_t	i_c                       :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t       i_rsvd_2                  :FFFFF 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprba_fld_s;1+} ii_iprba_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprbb_u 81+1uint64_t	ii_iprbb_ eUval;1+1s0		0x	81+11uint64_t	i_c	1	  :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprbb_fld_s;1+} ii_iprbb_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprbc_u 81+1uint64_t	ii_iprbc_ eUval;1+1s0		0x	81+11uint64_t	i_c	1	  :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprbc_fld_s;1+} ii_iprbc_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprbd_u 81+1uint64_t	ii_iprbd_ eUval;1+1s0		0x	81+11uint64_t	i_c	1	  :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprbd_fld_s;1+} ii_iprbd_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof SHub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprbe_u 81+1uint64_t	ii_iprbe_ eUval;1+1s0		0x	81+11uint64_t	i_c	1	  :	 8;1+11uint64_t	i_na1		  :	14;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_nb1		  :	14;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_m1		  :	 2;1+11uint64_t	i_f			  :	 1;1+11uint64_t	i_of_cnt1	  :	 5;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_rd_to1		  :	 1;1+11uint64_t	i_spur_wr		  :	 1;1+11uint64_t	i_spur_rd1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+11uint64_t	i_mult_err1	  :	 1;1+1}Fii_iprbe_fld_s;1+} ii_iprbe_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  There are 9 ins0ances of * is  eUTODMA, one pMA        *	+ * actual,widget in this implemenxat/onFof Shub and Crossbow.           *	+ * Note: Crossbow only has ports forLWidgets 8 through F,,widget 0      *	+ * refMAs to Crossbow's inDMAnal,spain.                                 *	+ * This  eUTODMA contains t e s0D-e elemenxs per widget that are        *	+ * necessary to manage the PIO flow control on Crosstalk and on t e     *	+ * RouDMA Network. See the PIO Flow Control chapterc* 4 a complet=      *	+ * descrip-/on of * is  eUTODMA                                         *	+ * Th= SPUR_WR bit requires som_Fexplana1ion. Wh=n this  eUTODMA is     *	+ * wriiien, th= new value of * e C *ield is captur	d in an inDMAnal,    *	+ *  eUTODMA so the hardware canFremember what the programmer wrote      *	+ * inDo the credit counDMA. Th= SPUR_WR bit sets wh=nevMA * e C *ield   *	+ * incremenxs above t is stora7 value, which indic ies that there       *	+ * havn6be=n mora responses receive7	than requests sen-. Th= SPUR_WR    *	+ * bit cannot be cleara7	unDil a value isCwriiien to the IPRBx          *	+ *  eUTODMA; * e wriie will correct * e C *ield and captur	 its new     *	+ * value in th_FinDMAnal, eUTODMA. Even if IECLR[E_PRB_x]Fis set, t e   *	+ * SPUR_WR bit will persTOD if IPRBx hasn't yet be=n wriiien.           *	+ * .                                                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprbf_u 81+        uint64_t       ii_iprbf_ eUval;1+        s0		0x  81+                uint64_t       i_c                       :FFFFFF8;1+                uint64_t       i_na                      :FFFFF14;1+                uint64_t       i_rsvd_2                  :FFFFF 2;1+                uint64_t       i_nb                      :FFFFF14;1+                uint64_t       i_rsvd_1                  :FFFFF 2;1+                uint64_t       i_m                       :FFFFFF2;1+                uint64_t       i_f                       :FFFFFF1;1+                uint64_t       i_of_cnt                  :FFFFFF5;1+                uint64_t       i_error                   :FFFFF 1;1+                uint64_t       i_rd_to                   :FFFFF 1;1+                uint64_t       i_spur_wr                 :FFFFF 1;1+                uint64_t       i_spur_rd                 :FFFFF 1;1+                uint64_t       i_rsvd                    :FFFFF11;1+                uint64_t       i_mult_err                :FFFFF 1;1+        }Fii_iprbe_fld_s;1+} ii_iprbf_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA speci*ies t e timeouD value to usec* 4 monitoring     *	+ * Crosstalk credits which are use7	ouDbound to Crosstalk. An           *	+ * inDMAnal,counDMA calle7	the Crosstalk Credit TimeouD CounDMA         *	+ * incremenxs evMAy 128 II clocks. Th= counDMA starts counDing          *	+ * anytime the credit counD drops below a threshold,6and resets to      *	+ * zero (stops counDing) anytime the credit counD is at  4 above t e    *	+ * threshold. Th= threshold is 1 credit in direct connect mode and 2    *	+ * in Crossbow connect mode. Wh=n th_FinDMAnal,Crosstalk Credit         *	+ * TimeouD CounDMA reaches t e value programmed in this  eUTODMA, a     *	+ * Crosstalk Credit TimeouD has occurred. Th= inDMAnal,counDMA is not   *	+ *  eada_le *rom software,6and stops counDing at its maximum value,     *	+ * so it cannot causecmora than one inDMArupt.                          *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ixcc_u 81+1uint64_t	ii_ixcc_ eUval;1+1s0		0x  81+11uint64_t	i_time_ouD                :	26;1+11uint64_t	i_rsvd	1	  :	38;1+1}Fii_ixcc_fld_s;1+} ii_ixcc_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA quali*ies all the PIO and DMA            *	+ * opera1ions launche7	*rom widget 0 towards the SHub. In               *	+ * addition, it also quali*ies accessas by the BTE s0	eams.             *	+ * Th= bits in each *ield of * is  eUTODMA are cleara7	by the SHub      *	+ * upon detect/on of an error which requires widget 0  4 t e BTE        *	+ * s0	eams to be DMAmin ied. Wh=ther  4 not widget x has access         *	+ *  ights to * is SHub is deteAmina7	by an AND of * e device            *	+ * ena_le bit in th_FappropriD-e *ield of * is  eUTODMA and bit 0 in    *	+ * the Wx_IAC *ield. Th= bits in * is *ield are set	by wriiing a 1 to   *	+ * them. Incoming replies *rom Crosstalk are not subject *o * is        *	+ * access control mechanism.                                            *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_imem_u 81+1uint64_t	ii_imem_ eUval;1+1s0		0x  81+11uint64_t	i_w0_esd                  :	 1;1+11uint64_t	i_rsvd_31	  :	 3;1+11uint64_t	i_b0_esd1	  :	 1;1+11uint64_t	i_rsvd_21	  :	 3;1+11uint64_t	i_b1_esd1	  :	 1;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t	i_clr_precise1	  :	 1;1+11uint64_t       i_rsvd                    :FFFFF51;1+1}Fii_imem_fld_s;1+} ii_imem_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip-/on:  This  eUTODMA speci*ies t e timeouD value to usec* 4   *	+ * monitoring Crosstalk tail flits coming inDo the Shub in t e          *	+ * TAIL_TO *ield. An inDMAnal,counDMA associ ied with * is  eUTODMA     *	+ * is incremenxed evMAy 128 II inDMAnal,clocks (7 bits). Th= counDMA    *	+ * s0arts counDing anytime a headMA micropacket is receive7	and stops   *	+ * counDing (and resets to zero) any time a micropacket with a Tail     *	+ * bit is receive7. Once the counDMA reaches t e threshold value        *	+ * programmed in this  eUTODMA, it genera1es an inDMArupt to the        *	+ * process 4 t at is programmed into the IIDSR. Th= counDMA satura1es   *	+ * (does not roll over) at its maximum value, so it cannot causec       *	+ * another inDMArupt unDil afDMA it is cleara7.                         *	+ * Th=  eUTODMA also contains t e Read Response TimeouD values. Th=     *	+ * PrescalaA is 23 bits,6and counDs II clocks. An inDMAnal,counDMA      *	+ * incremenxs onFevMAy II clock6and wh=n it reaches t e value in t e    *	+ * PrescalaA *ield, all IPRTE  eUTODMAs with * eir valid bits set       *	+ * havn6* eir Read Response timeAs bumped. Wh=nevMA any of * em match   *	+ * the value in t e RRSP_TO *ield, a Read Response TimeouD has          *	+ * occurred,6and error handling occurs	as described in the Error        *	+ * Handling sect/on of this documen-.                                   *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ixtt_u 81+1uint64_t	ii_ixtt_ eUval;1+1s0		0x  81+11uint64_t	i_tail_to                 :	26;1+11uint64_t	i_rsvd_11	  :	 6;1+11uint64_t	i_rrsp_ps1	  :	23;1+11uint64_t	i_rrsp_to1	FF:	 5;1+11uint64_t	i_rsvd1		  :	 4;1+1}Fii_ixtt_fld_s;1+} ii_ixtt_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Wriiing a 1 to the *ields of * is  eUTODMA clears th_FappropriD-e   *	+ * error bits in other araasFof SHub. Note t at wh=n th_F               *	+ * E_PRB_x bits are use7	to clear error bits in PRB  eUTODMAs,          *	+ * SPUR_RD6and SPUR_WR may persTOD, becausecth_y require additional,    *	+ * act/on to clear them. See the IPRBx and IXSS ReUTODMA                *	+ * speci*ica1ions.                                                      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ieclr_u 81+1uint64_t	ii_ieclr_ eUval;1+1s0		0x  81+11uint64_t	i_e_prb_0                 :	 1;1+11uint64_t	i_rsvd1		  :	 7;1+11uint64_t	i_e_prb_81	  :	 1;1+11uint64_t	i_e_prb_91	  :	 1;1+11uint64_t	i_e_prb_a1	  :	 1;1+11uint64_t	i_e_prb_b1	  :	 1;1+11uint64_t	i_e_prb_c1	  :	 1;1+11uint64_t	i_e_prb_d1	  :	 1;1+11uint64_t	i_e_prb_e1	  :	 1;1+11uint64_t	i_e_prb_f1	  :	 1;1+11uint64_t	i_e_crazy1	  :	 1;1+11uint64_t	i_e_bte_01	  :	 1;1+11uint64_t	i_e_bte_11	  :	 1;1+11uint64_t	i_reserve7_11	  :	10;1+11uint64_t	i_spur_rd_hdr		  :	 1;1+11uint64_t	i_cam_intr_to1	FF:	 1;1+11uint64_t	i_cam_overflow1	FF:	 1;1+11uint64_t	i_cam_ ead_miss1	FF:	 1;1+11uint64_t	i_ioq_ ep_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ eq_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ ep_overflow1FF:	 1;1+11uint64_t	i_ioq_ eq_overflow1FF:	 1;1+11uint64_t	i_iiq_ ep_overflow1FF:	 1;1+11uint64_t	i_iiq_ eq_overflow1FF:	 1;1+11uint64_t	i_ii_xn_ ep_cred_overflowF:	 1;1+11uint64_t	i_ii_xn_ eq_cred_overflowF:	 1;1+11uint64_t	i_ii_xn_invalid_cmd1FF:	 1;1+11uint64_t	i_xn_ii_invalid_cmd1FF:	 1;1+11uint64_t	i_reserve7_21	  :	21;1+1}Fii_ieclr_fld_s;1+} ii_ieclr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA controls both BTEs. SOFT_RESET is inDMnded for        *	+ * recovMAy afDMA an error. COUNT controls t e total number of CRBs     *	+ * t at both BTEs (combina7) canFuse, which affects total BTE           *	+ * bandwidth.                                                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibcr_u 81+1uint64_t	ii_ibcr_ eUval;1+1s0		0x  81+11uint64_t	i_counD                   :	 4;1+11uint64_t	i_rsvd_11	  :	 4;1+11uint64_t	i_soft_reset1	  :	 1;1+11uint64_t	i_rsvd	1	  :	55;1+1}Fii_ibcr_fld_s;1+} ii_ibcr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e headMA of a spurious  ead response       *	+ * receive7	*rom Crosstalk. A spurious  ead response is defina7	as a    *	+ *  ead response receive7	by II *rom a widget for which (1) the SIDN    *	+ * has a value betwe=n 1 and 7, inclusive (II nevMA sMnds requests to   *	+ * these widgets (2) there is no valid IPRTE  eUTODMA which             *	+ * corresponds to the TNUM,  4 (3) the widget indic ied in SIDN is      *	+ * not * e same as the widget recorded in the IPRTE  eUTODMA            *	+ *  eferenca7	by the TNUM. If * is condition is true,6and if the        *	+ * IXSS[VALID] bit is clear, th=n t e headMA of * e spurious  ead       *	+ *  esponse is captur	 in IXSM and IXSS, and IXSS[VALID] is set. Th=    *	+ * erranD headMA is th=reby captur	d, and no further spurious  ead      *	+ *  espones are captur	d unDil IXSS[VALID] is cleara7	by setiing t e    *	+ * appropriD-e bit in IECLR.EvMAytime a spurious  ead response is       *	+ * detect	d, th= SPUR_RD6bit of * e PRB corresponding to th_Fincoming   *	+ * message's SIDN *ield is set. This always happens,  eUarless of       *	+ * wh=ther a headMA is captur	d. Th= programmer should check            *	+ * IXSM[SIDN]	to deteAmina which widget sen- * e spurious  esponse,     *	+ * becausecth_re may becmora than one SPUR_RD6bit set in th_FPRB        *	+ *  eUTODMAs. Th= widget indic ied by IXSM[SIDN]	was the first          *	+ * spurious  ead response to be receive7	since the last time            *	+ * IXSS[VALID] was clear. Th= SPUR_RD6bit of * e corresponding PRB      *	+ * will be set. Any SPUR_RD6bits in any other PRB  eUTODMAs indic ie    *	+ * spurious messages *rom other widets which w_re detect	d afDMA t e    *	+ * headMA was captur	d..                                                *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ixsm_u 81+1uint64_t	ii_ixsm_ eUval;1+1s0		0x  81+11uint64_t	i_byte_en                 :	32;1+11uint64_t	i_reserve71	  :	 1;1+11uint64_t	i_tag	1	  :	 3;1+11uint64_t	i_alt_pacA_41	  :	 4;1+11uint64_t	i_bo1		  :	 1;1+11uint64_t	i_error			  :	 1;1+11uint64_t	i_vbpm			  :	 1;1+11uint64_t	i_gbr			  :	 1;1+11uint64_t	i_ds1		  :	 2;1+11uint64_t	i_ct			  :	 1;1+11uint64_t	i_tnum	1	FF:	 5;1+11uint64_t	i_pacA_41	  :	 4;1+11uint64_t	i_sidn	1	  :	 4;1+11uint64_t	i_didn	1	  :	 4;1+1}Fii_ixsm_fld_s;1+} ii_ixsm_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e sideband bits of a spurious  ead         *	+ *  esponse receive7	*rom Crosstalk.                                    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ixss_u 81+1uint64_t	ii_ixss_ eUval;1+1s0		0x  81+11uint64_t	i_sideband                :	 8;1+11uint64_t	i_rsvd	1	  :	55;1+11uint64_t	i_valid	1	  :	 1;1+1}Fii_ixss_fld_s;1+} ii_ixss_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA ena_les software to access the II LLP's test port.    *	+ * Refer to th_FLLP 2.5 documen-at/onF* 4 anFexplana1ion of * e test    *	+ * port. Software canFwriie *o * is  eUTODMA *o program the values      *	+ * f 4 t e control *ields (TestErrCaptur	, TestClear, TestFlit,         *	+ * TestMask6and TestSeed). Similarly, software canFrea7	*rom * is       *	+ *  eUTODMA *o obtain the values of * e test port's s0D-us outputs      *	+ * (TestCBerr, TestValid and TestData).                                 *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ilct_u 81+1uint64_t	ii_ilct_ eUval;1+1s0		0x  81+11uint64_t	i_test_seed               :	20;1+11uint64_t	i_test_mask6              :	 8;1+11uint64_t	i_test_data               :	20;1+11uint64_t	i_test_valid              :	 1;1+11uint64_t	i_test_cberr              :	 1;1+11uint64_t	i_test_flit6              :	 3;1+11uint64_t	i_test_clear              :	 1;1+11uint64_t	i_test_err_captur	        :	 1;1+11uint64_t	i_rsvd                    :	 9;1+1}Fii_ilct_fld_s;1+} ii_ilct_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  If the II detects an illeUalFincoming Duplonet packet (request  4   *	+ * reply) wh=n VALID==0 in the IIEPH1  eUTODMA, th=n it saves t e       *	+ * conDMnts of * e packet's headMA flit6in the IIEPH1 and IIEPH2        *	+ *  eUTODMAs, sets the VALID bit in IIEPH1, clears th_FOVERRUN bit,     *	+ * an7	assigns a value to th_FERR_TYPE *ield which indic ies the        *	+ * speci*ic natur	 of * e error. The II recognizes *our different       *	+ * A_4,s of errors: short request packets (ERR_TYPE==2), short reply    *	+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) an7	long   *	+ * reply packets (ERR_TYPE==5). Th= encodings f 4 t ese t_4,s of        *	+ * errors w_re chosen to be consTODent with * e same A_4,s of errors    *	+ * indic ied by th_FERR_TYPE *ield in the LB_ERROR_HDR1  eUTODMA (in    *	+ * the LB un/t). If the II detects an illeUalFincoming Duplonet         *	+ * packet wh=n VALID==1 in the IIEPH1  eUTODMA, th=n it m_rely sets     *	+ * the OVERRUN bit to indic ie that a subsequent error has happen	d,    *	+ * an7	does nothing further.                                            *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iieph1_u 81+1uint64_t	ii_iieph1_ eUval;1+1s0		0x	81+11uint64_t	i_comman7		  :	 7;1+11uint64_t	i_rsvd_5		  :	 1;1+11uint64_t	i_suppl1		  :	14;1+11uint64_t	i_rsvd_4		  :	 1;1+11uint64_t	i_source		  :	14;1+11uint64_t	i_rsvd_3		  :	 1;1+11uint64_t	i_err_A_4,1	  :	 4;1+11uint64_t	i_rsvd_21	  :	 4;1+11uint64_t	i_ovMArun1	  :	 1;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t	i_valid	1	  :	 1;1+11uint64_t	i_rsvd	1	  :	13;1+1}Fii_iieph1_fld_s;1+} ii_iieph1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA holds the Address *ield *rom * e headMA flit6of an    *	+ * incoming erroneous Duplonet packet, along with * e tail bit which    *	+ * accompanie7	this headMA flit. This  eUTODMA is essantially an        *	+ * exDension of IIEPH1. Two  eUTODMAs w_re necessary becausecth_ 64     *	+ * bits availa_le in only a	singl=  eUTODMA w_re insuf*icien- *o        *	+ * captur	 * e entire headMA flit6of an erroneous packet.               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iieph2_u 81+1uint64_t	ii_iieph2_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_01	  :	 3;1+11uint64_t	i_address                 :	47;1+11uint64_t	i_rsvd_11	  :	10;1+11uint64_t	i_tail	1	  :	 1;1+11uint64_t	i_rsvd	1	  :	 3;1+1}Fii_iieph2_fld_s;1+} ii_iieph2_u_t;6+	+	+/******************************/6+	+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA's value isCa bit vect 4 t at guards access *rom SXBs  *	+ * to	local, eUTODMAs within the II as well as to exDeAnal,Crosstalk    *	+ * widgets								*	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_islapr_u 81+1uint64_t	ii_islapr_ eUval;1+1s0		0x  81+11uint64_t	i_reUTon1	  :	64;1+1}Fii_islapr_fld_s;1+} ii_islapr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  AFwriie *o * is  eUTODMA of * e 56-bit value "Pup+Bun" will cause	*	+ * the bit in th_FISLAPR  eUTODMA corresponding to th_FreUTon of * e	*	+ * requestor to be set (access allowed).				(	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_islapo_u 81+1uint64_t	ii_islapo_ eUval;1+1s0		0x  81+11uint64_t	i_io_sbx_ovrride	  :	56;1+11uint64_t	i_rsvd	1	  :	 8;1+1}Fii_islapo_fld_s;1+} ii_islapo_u_t;6+	+/************************************************************************	+ *                                                                      *	+ *  DeteAminas how	long * e wrapper will wait aftr an inDMArupt is	*	+ * initially issued *rom * e II befor	 it times out * e outs0anding	*	+ * inDMArupt an7	drops it *rom * e inDMArupt queue.			* 	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iwi_u 81+1uint64_t	ii_iwi_ eUval;1+1s0		0x  81+11uint64_t	i_prescal,1	  :	24;1+11uint64_t	i_rsvd	1	  :	 8;1+11uint64_t	i_timeout1	  :	 8;1+11uint64_t	i_rsvd1	1	  :	 8;1+11uint64_t	i_intrpt_ etry_period	  :	 8;1+11uint64_t	i_rsvd2	1	  :	 8;1+1}Fii_iwi_fld_s;1+} ii_iwi_u_t;6+	+/************************************************************************	+ *                                                                      *	+ *  Log errors which havn6occurred in the II wrapper. Th= errors are	*	+ * cleara7	by wriiing to the IECLR, eUTODMA.				* 	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iwel_u 81+1uint64_t	ii_iwel_ eUval;1+1s0		0x  81+11uint64_t	i_intr_timed_ouD	  :	 1;1+11uint64_t	i_rsvd1		  :	 7;1+11uint64_t	i_cam_overflow1	FF:	 1;1+11uint64_t	i_cam_ ead_miss1	FF:	 1;1+11uint64_t	i_rsvd1	1	  :	 2;1+11uint64_t	i_ioq_ ep_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ eq_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ ep_overflow1FF:	 1;1+11uint64_t	i_ioq_ eq_overflow1FF:	 1;1+11uint64_t	i_iiq_ ep_overflow1FF:	 1;1+11uint64_t	i_iiq_ eq_overflow1FF:	 1;1+11uint64_t	i_rsvd2	1	  :	 6;1+11uint64_t	i_ii_xn_ ep_cred_over_undMA:	 1;1+11uint64_t	i_ii_xn_ eq_cred_over_undMA:	 1;1+11uint64_t	i_rsvd3	1	  :	 6;1+11uint64_t	i_ii_xn_invalid_cmd1FF:	 1;1+11uint64_t	i_xn_ii_invalid_cmd1FF:	 1;1+11uint64_t	i_rsvd4	1	  :	30;1+1}Fii_iwel_fld_s;1+} ii_iwel_u_t;6+	+/************************************************************************	+ *                                                                      *	+ *  Controls t e II wrapper.						* 	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iwc_u 81+1uint64_t	ii_iwc_ eUval;1+1s0		0x  81+11uint64_t	i_dma_byte_swap1	  :	 1;1+11uint64_t	i_rsvd	1	  :	 3;1+11uint64_t	i_cam_ ead_linas_reset1FF:	 1;1+11uint64_t	i_rsvd1	1	  :	 3;1+11uint64_t	i_ii_xn_cred_over_undMA_log:	 1;1+11uint64_t	i_rsvd2	1	  :	19;1+11uint64_t	i_xn_ ep_iq_depth	FF:	 5;1+11uint64_t	i_rsvd3	1	  :	 3;1+11uint64_t	i_xn_ eq_iq_depth	FF:	 5;1+11uint64_t	i_rsvd4	1	  :	 3;1+11uint64_t	i_iiq_depth		  :	 6;1+11uint64_t	i_rsvd5	1	  :	12;1+11uint64_t	i_force_ ep_cred1FF:	 1;1+11uint64_t	i_force_ eq_cred1FF:	 1;1+1}Fii_iwc_fld_s;1+} ii_iwc_u_t;6+	+/************************************************************************	+ *                                                                      *	+ *  S0D-us in the II wrapper.						* 	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iws_u 81+1uint64_t	ii_iws_ eUval;1+1s0		0x  81+11uint64_t	i_xn_ ep_iq_credits	FF:	 5;1+11uint64_t	i_rsvd1		  :	 3;1+11uint64_t	i_xn_ eq_iq_credits	FF:	 5;1+11uint64_t	i_rsvd1	1	  :	51;1+1}Fii_iws_fld_s;1+} ii_iws_u_t;6+	+/************************************************************************	+ *                                                                      *	+ *  Masks errors in the IWEL, eUTODMA.					*	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iweim_u 81+1uint64_t	ii_iweim_ eUval;1+1s0		0x  81+11uint64_t	i_intr_timed_ouD	  :	 1;1+11uint64_t	i_rsvd1		  :	 7;1+11uint64_t	i_cam_overflow1	FF:	 1;1+11uint64_t	i_cam_ ead_miss1	FF:	 1;1+11uint64_t	i_rsvd1	1	  :	 2;1+11uint64_t	i_ioq_ ep_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ eq_undMAflow1FF:	 1;1+11uint64_t	i_ioq_ ep_overflow1FF:	 1;1+11uint64_t	i_ioq_ eq_overflow1FF:	 1;1+11uint64_t	i_iiq_ ep_overflow1FF:	 1;1+11uint64_t	i_iiq_ eq_overflow1FF:	 1;1+11uint64_t	i_rsvd2	1	  :	 6;1+11uint64_t	i_ii_xn_ ep_cred_overflowF:	 1;1+11uint64_t	i_ii_xn_ eq_cred_overflowF:	 1;1+11uint64_t	i_rsvd3	1	  :	 6;1+11uint64_t	i_ii_xn_invalid_cmd1FF:	 1;1+11uint64_t	i_xn_ii_invalid_cmd1FF:	 1;1+11uint64_t	i_rsvd4	1	  :	30;1+1}Fii_iweim_fld_s;1+} ii_iweim_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  AFwriie *o * is  eUTODMA causesCa particulaA *ield in t e           *	+ * corresponding widget's PRB entry to be adjusied up  4 down	by 1.     *	+ * This counDMA should be use7	wh=n recovMAing from error and reset     *	+ * conditions. Note t at software would be capa_le of causing           *	+ * inadvMADent overflowFor undMAflow of * es= counDMAs.                 *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ipca_u 81+1uint64_t	ii_ipca_ eUval;1+1s0		0x  81+11uint64_t	i_wid                     :	 4;1+11uint64_t	i_adjusi1	  :	 1;1+11uint64_t	i_rsvd_11	  :	 3;1+11uint64_t	i_*ield	1	  :	 2;1+11uint64_t	i_rsvd	1	  :	54;1+1}Fii_ipca_fld_s;1+} ii_ipca_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+	+A_4,_}, un/onFii_iprte0a_u 81+1uint64_t	ii_iprte0a_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t       i_vld                     :FFFFF 1;1+1}Fii_iprte0a_fld_s;1+} ii_iprte0a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte1a_u 81+1uint64_t	ii_iprte1a_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t       i_vld                     :FFFFF 1;1+1}Fii_iprte1a_fld_s;1+} ii_iprte1a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte2a_u 81+1uint64_t	ii_iprte2a_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t       i_vld                     :FFFFF 1;1+1}Fii_iprte2a_fld_s;1+} ii_iprte2a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte3a_u 81+1uint64_t	ii_iprte3a_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t	i_vld	1	  :	 1;1+1}Fii_iprte3a_fld_s;1+} ii_iprte3a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte4a_u 81+1uint64_t	ii_iprte4a_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_11	  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t	i_vld	1	  :	 1;1+1}Fii_iprte4a_fld_s;1+} ii_iprte4a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte5a_u 81+1uint64_t	ii_iprte5a_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_11	  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t	i_vld	1	  :	 1;1+1}Fii_iprte5a_fld_s;1+} ii_iprte5a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte6a_u 81+1uint64_t	ii_iprte6a_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_11	  :	54;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t	i_vld	1	  :	 1;1+1}Fii_iprte6a_fld_s;1+} ii_iprte6a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte7a_u 81+        uint64_t       ii_iprte7a_ eUval;1+        s0		0x  81+                uint64_t       i_rsvd_1                  :FFFFF54;1+                uint64_t       i_widget                  :FFFFF 4;1+                uint64_t       i_to_cnt                  :FFFFF 5;1+                uint64_t       i_vld                     :FFFFF 1;1+        } ii_iprtea7_fld_s;1+} ii_iprte7a_u_t;6+	+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+	+A_4,_}, un/onFii_iprte0b_u 81+1uint64_t	ii_iprte0b_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte0b_fld_s;1+} ii_iprte0b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte1b_u 81+1uint64_t	ii_iprte1b_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte1b_fld_s;1+} ii_iprte1b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte2b_u 81+1uint64_t	ii_iprte2b_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte2b_fld_s;1+} ii_iprte2b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte3b_u 81+1uint64_t	ii_iprte3b_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte3b_fld_s;1+} ii_iprte3b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte4b_u 81+1uint64_t	ii_iprte4b_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte4b_fld_s;1+} ii_iprte4b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte5b_u 81+1uint64_t	ii_iprte5b_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1}Fii_iprte5b_fld_s;1+} ii_iprte5b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte6b_u 81+1uint64_t	ii_iprte6b_ eUval;1+1s0		0x	81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+1+1}Fii_iprte6b_fld_s;1+} ii_iprte6b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  There are 8 ins0ances of * is  eUTODMA. This  eUTODMA contains      *	+ * the informa1ion that the II has to remember once iD has launche7	a   *	+ * PIO Read opera1ion. Th= conDMnts are use7	to form * e correct        *	+ * RouDMA Network packet an7	direct * e Crosstalk reply to the          *	+ * appropriD-e process 4.                                               *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iprte7b_u 81+        uint64_t       ii_iprte7b_ eUval;1+        s0		0x  81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_address1	  :	47;1+11uint64_t	i_init1		  :	 3;1+11uint64_t       i_source                  :FFFFF11;1+        } ii_iprte7b_fld_s;1+} ii_iprte7b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFSHub II contains a featur	 which did not exTOD in      *	+ * the Hub which automa1ically cleans up afDMA a Read Response          *	+ * timeout, including dealloca1ion of * e IPRTE and recovMAy of IBuf    *	+ * space. Th= inclusion of * is  eUTODMA inFSHub is f 4 backward        *	+ * compa1ibility                                                        *	+ * AFwriie *o * is  eUTODMA causesCan entry *rom * e ta_le of           *	+ * outs0anding PIO Read Requests to be *reed and returne7	to the        *	+ * stack of *ree entries. This  eUTODMA is use7	inFhandling t e         *	+ * timeout errors that resulD in a PIO Reply nevMA returning from       *	+ * Crosstalk.                                                           *	+ * Note t at * is  eUTODMA does not affect t e contMnts of * e IPRTE    *	+ *  eUTODMAs. Th= Valid bits in those, eUTODMAs havn6to be              *	+ * speci*ically turne7	off	by software.                                 *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ipdr_u 81+1uint64_t	ii_ipdr_ eUval;1+1s0		0x  81+11uint64_t	i_te                      :	 3;1+11uint64_t	i_rsvd_11	  :	 1;1+11uint64_t	i_pnd	1	  :	 1;1+11uint64_t	i_init_rpcnt1	  :	 1;1+11uint64_t	i_rsvd	1	  :	58;1+1}Fii_ipdr_fld_s;1+} ii_ipdr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  AFwriie *o * is  eUTODMA causesCa CRB entry to be returne7	to the   *	+ * queue of *ree CRBs. Th= entry should havn6previously been cleara7	   *	+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *	+ *  eUTODMA is use7	inFthe last ODMp of handling t e errors that are    *	+ * captur	d and marke7	inFCRB entries.  Briefly: 1) first error for     *	+ * DMAFwriie *rom a particulaA device,6and first error for a            *	+ * particulaA BTE s0	eam, lead to a marke7	CRB entry,6and process 4     *	+ * inDMArupt, 2) software  eads t e error informa1ion captur	d in t e   *	+ * CRB entry,6and presuma_ly takes some corrective ac1ion, 3)           *	+ * software clears th_Fmark bit,6and finally 4) software wriies *o      *	+ * the ICDR  eUTODMA *o return * e CRB entry to the lTOD of *ree CRB    *	+ * entries.                                                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icdr_u 81+1uint64_t	ii_icdr_ eUval;1+1s0		0x  81+11uint64_t	i_crb_num                 :	 4;1+11uint64_t	i_pnd	1	  :	 1;1+11uint64_t       i_rsvd                    :FFFFF59;1+1}Fii_icdr_fld_s;1+} ii_icdr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA provides debug access to two FIFOs inside of II.      *	+ * Both IOQ_MAX* *ields of * is  eUTODMA contain the ins0an0aneous      *	+ * depth (in un/ts of * e numbMA of availa_le entries) of * e           *	+ * ass ci ied IOQ FIFO.  AFrea7	of * is  eUTODMA will return * e        *	+ * numbMA of *ree entries onFeach FIFO at the time of * e rea7.  So     *	+ * wh=n a FIFO is idle, th= ass ci ied *ield contains t e maximum       *	+ * depth of * e FIFO.  This  eUTODMA is wriia_le for debug reasons      *	+ * and is intMnde7	to be wriitMn with * e maximum desir	d FIFO depth    *	+ * while * e FIFO is idle. Software muOD assur	 * at II is idle wh=n    *	+ * this  eUTODMA is wriitMn. If there are any active entries in any     *	+ * of * es= FIFOs wh=n this  eUTODMA is wriitMn, * e resulDs are        *	+ * undMfin	d.                                                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ifdr_u 81+1uint64_t	ii_ifdr_ eUval;1+1s0		0x  81+11uint64_t	i_ioq_max_rq              :	 7;1+11uint64_t	i_set_ioq_ q	1FF:	 1;1+11uint64_t	i_ioq_max_rp		  :	 7;1+11uint64_t	i_set_ioq_ p1	  :	 1;1+11uint64_t	i_rsvd	1	  :	48;1+1}Fii_ifdr_fld_s;1+} ii_ifdr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA allows t e II to become slugUTOh in removing          *	+ * messages *rom its inbound queue (IIQ). This will cause messages *o   *	+ * back up in either virtual channel. Disa_ling t e "molasses" mode     *	+ * subsequently allows t e II to be tested undMA s0	ess. In t e         *	+ * slugUTOh ("Molasses") mode, * e localized effects of conges1ion      *	+ * can be observe7.                                                     *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iiap_u 81+        uint64_t       ii_iiap_ eUval;1+        s0		0x  81+                uint64_t       i_rq_mls                  :FFFFF 6;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_rp_mls1	  :	 6;1+11uint64_t       i_rsvd                    :FFFFF50;1+        } ii_iiap_fld_s;1+} ii_iiap_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA allows sevMAal parameDMAs of CRB opera1ion6to be      *	+ * set. Note t at wriiing to this  eUTODMA can havn6catastrophic side   *	+ * effects, if * e CRB is not quiescent, i.e. if * e CRB is             *	+ * processing protocol messages wh=n the wriie6occurs.                  *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icmr_u 81+1uint64_t	ii_icmr_ eUval;1+1s0		0x  81+11uint64_t	i_sp_msg                  :	 1;1+11uint64_t	i_rd_hdr1	  :	 1;1+11uint64_t	i_rsvd_41	  :	 2;1+11uint64_t	i_c_cnt1		  :	 4;1+11uint64_t	i_rsvd_3		  :	 4;1+11uint64_t	i_clr_ qpd1	FF:	 1;1+11uint64_t	i_clr_ ppd1	FF:	 1;1+11uint64_t	i_rsvd_21	  :	 2;1+11uint64_t	i_fc_cnt1	  :	 4;1+11uint64_t	i_crb_vld	1  :	15;1+11uint64_t	i_crb_mark	1  :	15;1+11uint64_t	i_rsvd_11	  :	 2;1+11uint64_t	i_precise1	  :	 1;1+11uint64_t	i_rsvd	1	  :	11;1+1}Fii_icmr_fld_s;1+} ii_icmr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA allows control of * e ia_le por1ion of * e CRB        *	+ * logic via software. Control opera1ions *rom * is  eUTODMA havn6      *	+ * priority ovMA all incoming Crosstalk oA BTE requests.                *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_iccr_u 81+1uint64_t	ii_iccr_ eUval;1+1s0		0x  81+11uint64_t	i_crb_num                 :	 4;1+11uint64_t	i_rsvd_11	  :	 4;1+11uint64_t	i_cmd	1	  :	 8;1+11uint64_t	i_pending		  :	 1;1+11uint64_t	i_rsvd	1	  :	47;1+1}Fii_iccr_fld_s;1+} ii_iccr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA allows t e maximum timeout value to be programme7.    *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icto_u 81+1uint64_t	ii_icto_ eUval;1+1s0		0x  81+11uint64_t	i_timeout                 :	 8;1+11uint64_t	i_rsvd	1	  :	56;1+1}Fii_icto_fld_s;1+} ii_icto_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA allows t e timeout prescalar to be programme7. An     *	+ * inDMAnal,counDMA isCass ci ied with * is  eUTODMA. Wh=n the          *	+ * inDMAnal,counDMA reaches t e value of * e PRESCALE *ield, * e        *	+ * timer, eUTODMAs in all valid CRBs are incremenied (CRBx_D[TIMEOUT]   *	+ * *ield). Th= inDMAnal,counDMA resets to zero,6and th=n continues      *	+ * counting.                                                            *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ictp_u 81+1uint64_t	ii_ictp_ eUval;1+1s0		0x  81+11uint64_t	i_prescal,                :	24;1+11uint64_t	i_rsvd	1	  :	40;1+1}Fii_ictp_fld_s;1+} ii_ictp_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThere are 15 CRB Entries (ICRB0 to ICRBE) that are     *	+ * use7	for Crosstalk opera1ions (both cachelina6and partial,           *	+ * opera1ions) oA BTE/IO. Becausecth_ CRB entries are vMAy wide, five   *	+ *  eUTODMAs (_A to _E) are  equire7	to rea7	and wriie6each entry.      *	+ * Th_ CRB Entry  eUTODMAs can be conceptualized as  ows and columns    *	+ * (illus0	 ied in the ia_le abovM). Each  ow contains t e 4,           *	+ *  eUTODMAs  equire7	for a singl= CRB Entry. Th= first dou_leword      *	+ * (column)	for each entry isClabele7	A,6and th= second dou_leword      *	+ * (higher address) isClabele7	B, * e * ird dou_leword isClabele7	C,    *	+ * the fourth dou_leword isClabele7	D6and th= fifth dou_leword isC      *	+ * labele7	E. All CRB entries havn6their addresses onFa quarter         *	+ * cachelina6aligne7	boundary.                   *	+ * Upon reset, only the following fields are initialized: valid         *	+ * (VLD), priority count, timeout, timeout valid, and conDMxt valid.    *	+ * All other bits should be cleara7	by software befor	 usec(afDMA       *	+ *  ecovMAing any potMntial,error staie *rom befor	 * e reset).         *	+ * The following four ia_les summarize the forma1	for the four          *	+ *  eUTODMAs that are use7	for each ICRB# Entry.                        *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icrb0_a_u 81+1uint64_t	ii_icrb0_a_ eUval;1+1s0		0x  81+11uint64_t	ia_iow                    :	 1;1+11uint64_t	ia_vld	1	  :	 1;1+11uint64_t	ia_addr	1	  :	47;1+11uint64_t	ia_tnum	1	  :	 5;1+11uint64_t	ia_sidn1		  :	 4;1+11uint64_t       ia_rsvd                   :FFFFF 6;1+1}Fii_icrb0_a_fld_s;1+} ii_icrb0_a_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThere are 15 CRB Entries (ICRB0 to ICRBE) that are     *	+ * use7	for Crosstalk opera1ions (both cachelina6and partial,           *	+ * opera1ions) oA BTE/IO. Becausecth_ CRB entries are vMAy wide, five   *	+ *  eUTODMAs (_A to _E) are  equire7	to rea7	and wriie6each entry.      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icrb0_b_u 81+1uint64_t	ii_icrb0_b_ eUval;1+1s0		0x	81+11uint64_t	ib_xt_err1	  :	 1;1+11uint64_t	ib_mark	1	  :	 1;1+11uint64_t	ib_ln_uce1	  :	 1;1+11uint64_t	ib_errcode1	  :	 3;1+11uint64_t	ib_error1	  :	 1;1+11uint64_t	ib_stall__bte_11	  :	 1;1+11uint64_t	ib_stall__bte_01	  :	 1;1+11uint64_t	ib_stall__intr1	  :	 1;1+11uint64_t	ib_stall_ib1	  :	 1;1+11uint64_t	ib_intvn1	  :	 1;1+11uint64_t	ib_wb	1	  :	 1;1+11uint64_t	ib_hold	1	  :	 1;1+11uint64_t	ib_ack	1	  :	 1;1+11uint64_t	ib_resp	1	  :	 1;1+11uint64_t	ib_ack_cnt1	  :	11;1+11uint64_t	ib_rsvd1		  :	 7;1+11uint64_t	ib_exc	1	  :	 5;1+11uint64_t	ib_init1		  :	 3;1+11uint64_t	ib_imsg	1	  :	 8;1+11uint64_t	ib_imsgA_4,1	  :	 2;1+11uint64_t	ib_use_old1	  :	 1;1+11uint64_t	ib_rsvd_11	  :	11;1+1}Fii_icrb0_b_fld_s;1+} ii_icrb0_b_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThere are 15 CRB Entries (ICRB0 to ICRBE) that are     *	+ * use7	for Crosstalk opera1ions (both cachelina6and partial,           *	+ * opera1ions) oA BTE/IO. Becausecth_ CRB entries are vMAy wide, five   *	+ *  eUTODMAs (_A to _E) are  equire7	to rea7	and wriie6each entry.      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icrb0_c_u 81+1uint64_t	ii_icrb0_c_ eUval;1+1s0		0x	81+11uint64_t	ic_source	1  :	15;1+11uint64_t	ic_size	1	  :	 2;1+11uint64_t	ic_ct	1	  :	 1;1+11uint64_t	ic_bte_num	1  :	 1;1+11uint64_t	ic_gbr	1	  :	 1;1+11uint64_t	ic_resprqd1	  :	 1;1+11uint64_t	ic_bo	1	  :	 1;1+11uint64_t	ic_suppl	1  :	15;1+11uint64_t	ic_rsvd1		  :	27;1+1}Fii_icrb0_c_fld_s;1+} ii_icrb0_c_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThere are 15 CRB Entries (ICRB0 to ICRBE) that are     *	+ * use7	for Crosstalk opera1ions (both cachelina6and partial,           *	+ * opera1ions) oA BTE/IO. Becausecth_ CRB entries are vMAy wide, five   *	+ *  eUTODMAs (_A to _E) are  equire7	to rea7	and wriie6each entry.      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icrb0_d_u 81+1uint64_t	ii_icrb0_d_ eUval;1+1s0		0x  81+11uint64_t	id_pa_be                  :	43;1+11uint64_t	id_bte_op1	  :	 1;1+11uint64_t	id_pr_psc1	  :	 4;1+11uint64_t	id_pr_cnt1	  :	 4;1+11uint64_t	id_sleep1	  :	 1;1+11uint64_t	id_rsvd	1	  :	11;1+1}Fii_icrb0_d_fld_s;1+} ii_icrb0_d_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThere are 15 CRB Entries (ICRB0 to ICRBE) that are     *	+ * use7	for Crosstalk opera1ions (both cachelina6and partial,           *	+ * opera1ions) oA BTE/IO. Becausecth_ CRB entries are vMAy wide, five   *	+ *  eUTODMAs (_A to _E) are  equire7	to rea7	and wriie6each entry.      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icrb0_e_u 81+1uint64_t	ii_icrb0_e_ eUval;1+1s0		0x  81+11uint64_t	ie_timeout                :	 8;1+11uint64_t	ie_conDMxt	1  :	15;1+11uint64_t	ie_rsvd1		  :	 1;1+11uint64_t	ie_tvld	1	  :	 1;1+11uint64_t	ie_cvld	1	  :	 1;1+11uint64_t	ie_rsvd_01	  :	38;1+1}Fii_icrb0_e_fld_s;1+} ii_icrb0_e_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e lowMA 64 bits of * e hea7MA of * e       *	+ * spurious message captur	d by II. Valid wh=n the SP_MSG bit in ICMR   *	+ *  eUTODMA is set.                                                     *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icsml_u 81+1uint64_t	ii_icsml_ eUval;1+1s0		0x  81+11uint64_t	i_tt_addr                 :	47;1+11uint64_t	i_newsuppl_ex	1  :	14;1+11uint64_t	i_reserve71	  :	 2;1+11uint64_t       i_overflowF               :FFFFF 1;1+1}Fii_icsml_fld_s;1+} ii_icsml_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e middle 64 bits of * e hea7MA of * e      *	+ * spurious message captur	d by II. Valid wh=n the SP_MSG bit in ICMR   *	+ *  eUTODMA is set.                                                     *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icsmm_u 81+1uint64_t	ii_icsmm_ eUval;1+1s0		0x  81+11uint64_t	i_tt_ack_cnt              :	11;1+11uint64_t	i_reserve71	  :	53;1+1}Fii_icsmm_fld_s;1+} ii_icsmm_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e microscopic staie, all the inputs *o     *	+ * the protocol ia_le, captur	d with * e spurious message. Valid wh=n   *	+ * the SP_MSG bit in the ICMR  eUTODMA is set.                          *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_icsmh_u 81+1uint64_t	ii_icsmh_ eUval;1+1s0		0x  81+11uint64_t	i_tt_vld                  :	 1;1+11uint64_t	i_xerr1		  :	 1;1+11uint64_t	i_ft_cwact_o		  :	 1;1+11uint64_t	i_ft_wact_o		  :	 1;1+11uint64_t       i_ft_active_o             :FFFFF 1;1+11uint64_t	i_sync1		  :	 1;1+11uint64_t	i_mnusg	1	  :	 1;1+11uint64_t	i_mnusz	1	  :	 1;1+11uint64_t	i_plusz	1	  :	 1;1+11uint64_t	i_plusg	1	  :	 1;1+11uint64_t	i_tt_exc	1  :	 5;1+11uint64_t	i_tt_wb	1	  :	 1;1+11uint64_t	i_tt_hold1	  :	 1;1+11uint64_t	i_tt_ack1	  :	 1;1+11uint64_t	i_tt_resp	1  :	 1;1+11uint64_t	i_tt_intvn1	  :	 1;1+11uint64_t	i_g_stall_bte11	  :	 1;1+11uint64_t	i_g_stall_bte01	  :	 1;1+11uint64_t	i_g_stall_il1	  :	 1;1+11uint64_t	i_g_stall_ib	1  :	 1;1+11uint64_t	i_tt_imsg	1  :	 8;1+11uint64_t	i_tt_imsgA_4,1	  :	 2;1+11uint64_t	i_tt_use_old1	  :	 1;1+11uint64_t	i_tt_resp eqd1	  :	 1;1+11uint64_t	i_tt_bte_num	1  :	 1;1+11uint64_t	i_cbn	1	  :	 1;1+11uint64_t	i_match	1	  :	 1;1+11uint64_t	i_rpcnt_lt_341	  :	 1;1+11uint64_t	i_rpcnt_ge_341	  :	 1;1+11uint64_t	i_rpcnt_lt_181	  :	 1;1+11uint64_t	i_rpcnt_ge_181	  :	 1;1+11uint64_t       i_rpcnt_lt_2              :FFFFF 1;1+11uint64_t	i_rpcnt_ge_21	  :	 1;1+11uint64_t	i_rqcnt_lt_181	  :	 1;1+11uint64_t	i_rqcnt_ge_181	  :	 1;1+11uint64_t	i_rqcnt_lt_21	  :	 1;1+11uint64_t	i_rqcnt_ge_21	  :	 1;1+11uint64_t	i_tt_device		  :	 7;1+11uint64_t	i_tt_init		  :	 3;1+11uint64_t	i_reserve71	  :	 5;1+1}Fii_icsmh_fld_s;1+} ii_icsmh_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  The Shub DEBUG un/t provides a 3-bit selec1ion signal,to the        *	+ * II cora6and a 3-bit selec1ion signal,to the fsbclk domain in the II  *	+ * wrapper.                                                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_idbss_u 81+1uint64_t	ii_idbss_ eUval;1+1s0		0x  81+11uint64_t	i_iioclk_cora_submenu     :	 3;1+11uint64_t	i_rsvd	1	  :	 5;1+11uint64_t	i_fsbclk_wrapper_submenu  :	 3;1+11uint64_t	i_rsvd_11	  :	 5;1+11uint64_t	i_iioclk_menu1	  :	 5;1+11uint64_t	i_rsvd_21	  :	43;1+1}Fii_idbss_fld_s;1+} ii_idbss_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThis  eUTODMA is use7	to set up t e length for a       *	+ * transfer and th=n to mon/tor the progress of * at transfer. This     *	+ *  eUTODMA needs to be initialized befor	 a transfer is starte7. A     *	+ * leUTtimaie wriie *o * is  eUTODMA will set the Busy bit,6clear t e   *	+ * Error bit,6and initialize t e length to the value desir	d.           *	+ * While * e transfer is in progress, hardware will decremeni * e       *	+ * length field with each successful block * at is copi	d. Once * e     *	+ * transfer completes, hardware will clear t e Busy bit. Th= length     *	+ * *ield will also contain the numbMA of cache linas left6to be         *	+ * transferr	d.                                                         *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibls0_u 81+1uint64_t	ii_ibls0_ eUval;1+1s0		0x	81+11uint64_t	i_length	1  :	16;1+11uint64_t	i_error1		FF:	 1;1+11uint64_t	i_rsvd_1		  :	 3;1+11uint64_t	i_busy	1	  :	 1;1+11uint64_t       i_rsvd                    :FFFFF43;1+1}Fii_ibls0_fld_s;1+} ii_ibls0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA should be loaded befor	 a transfer is starte7. The    *	+ * address6to be loaded in bits 39:0 is t e 40-bit TRex+ physical       *	+ * address6as described in Sec1ion 1.3, Figure26and Figure3. Since      *	+ * the bottom 7 bits of * e address6ar	 always taken6to be zero,6BTE    *	+ * transfers6ar	 always cachelina-aligne7.                              *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibsa0_u 81+1uint64_t	ii_ibsa0_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	42;1+11uint64_t       i_rsvd                    :FFFFF15;1+1}Fii_ibsa0_fld_s;1+} ii_ibsa0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA should be loaded befor	 a transfer is starte7. The    *	+ * address6to be loaded in bits 39:0 is t e 40-bit TRex+ physical       *	+ * address6as described in Sec1ion 1.3, Figure26and Figure3. Since      *	+ * the bottom 7 bits of * e address6ar	 always taken6to be zero,6BTE    *	+ * transfers6ar	 always cachelina-aligne7.                              *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibda0_u 81+1uint64_t	ii_ibda0_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	42;1+11uint64_t	i_rsvd	1	  :	15;1+1}Fii_ibda0_fld_s;1+} ii_ibda0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Wriiing to this  eUTODMA sets up t e attributes of * e transfer     *	+ * and initiates t e transfer opera1ion. Reading t is  eUTODMA has      *	+ * the side effect of *erminating any transfer in progress. Note:       *	+ * stopping a transfer mids0	eam could havn6an adverse impact on the    *	+ * other BTE. If a BTE s0	eam has to be stopped (due to error           *	+ * handling for example), both BTE s0	eams should be stopped and        *	+ * their transfers6discard	d.                                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibct0_u 81+1uint64_t	ii_ibct0_ eUval;1+1s0		0x  81+11uint64_t	i_zerofill                :	 1;1+11uint64_t	i_rsvd_21	  :	 3;1+11uint64_t	i_notify		FF:	 1;1+11uint64_t	i_rsvd_1		  :	 3;1+11uint64_t       i_poison                  :FFFFF 1;1+11uint64_t       i_rsvd                    :FFFFF55;1+1}Fii_ibct0_fld_s;1+} ii_ibct0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e address6to which t e WINV is sent.       *	+ * ThisCaddress6has to be cache lina aligne7.                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibna0_u 81+1uint64_t	ii_ibna0_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	42;1+11uint64_t	i_rsvd	1	  :	15;1+1}Fii_ibna0_fld_s;1+} ii_ibna0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e programma_le level6as well6as the node   *	+ * ID6and PI un/t of * e process 4 to which t e inDMArupt will be       *	+ * sent.                                                                *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibia0_u 81+1uint64_t	ii_ibia0_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_2                   :	 1;1+11uint64_t	i_node_id1	  :	11;1+11uint64_t	i_rsvd_11	  :	 4;1+11uint64_t	i_level1		  :	 7;1+11uint64_t       i_rsvd                    :FFFFF41;1+1}Fii_ibia0_fld_s;1+} ii_ibia0_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ * Descrip1ion:FFThis  eUTODMA is use7	to set up t e length for a       *	+ * transfer and th=n to mon/tor the progress of * at transfer. This     *	+ *  eUTODMA needs to be initialized befor	 a transfer is starte7. A     *	+ * leUTtimaie wriie *o * is  eUTODMA will set the Busy bit,6clear t e   *	+ * Error bit,6and initialize t e length to the value desir	d.           *	+ * While * e transfer is in progress, hardware will decremeni * e       *	+ * length field with each successful block * at is copi	d. Once * e     *	+ * transfer completes, hardware will clear t e Busy bit. Th= length     *	+ * *ield will also contain the numbMA of cache linas left6to be         *	+ * transferr	d.                                                         *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibls1_u 81+1uint64_t	ii_ibls1_ eUval;1+1s0		0x  81+11uint64_t	i_length                  :	16;1+11uint64_t	i_error1		FF:	 1;1+11uint64_t	i_rsvd_1		  :	 3;1+11uint64_t	i_busy	1	  :	 1;1+11uint64_t       i_rsvd                    :FFFFF43;1+1}Fii_ibls1_fld_s;1+} ii_ibls1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA should be loaded befor	 a transfer is starte7. The    *	+ * address6to be loaded in bits 39:0 is t e 40-bit TRex+ physical       *	+ * address6as described in Sec1ion 1.3, Figure26and Figure3. Since      *	+ * the bottom 7 bits of * e address6ar	 always taken6to be zero,6BTE    *	+ * transfers6ar	 always cachelina-aligne7.                              *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibsa1_u 81+1uint64_t	ii_ibsa1_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	33;1+11uint64_t	i_rsvd	1	  :	24;1+1}Fii_ibsa1_fld_s;1+} ii_ibsa1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA should be loaded befor	 a transfer is starte7. The    *	+ * address6to be loaded in bits 39:0 is t e 40-bit TRex+ physical       *	+ * address6as described in Sec1ion 1.3, Figure26and Figure3. Since      *	+ * the bottom 7 bits of * e address6ar	 always taken6to be zero,6BTE    *	+ * transfers6ar	 always cachelina-aligne7.                              *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibda1_u 81+1uint64_t	ii_ibda1_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	33;1+11uint64_t	i_rsvd	1	  :	24;1+1}Fii_ibda1_fld_s;1+} ii_ibda1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  Wriiing to this  eUTODMA sets up t e attributes of * e transfer     *	+ * and initiates t e transfer opera1ion. Reading t is  eUTODMA has      *	+ * the side effect of *erminating any transfer in progress. Note:       *	+ * stopping a transfer mids0	eam could havn6an adverse impact on the    *	+ * other BTE. If a BTE s0	eam has to be stopped (due to error           *	+ * handling for example), both BTE s0	eams should be stopped and        *	+ * their transfers6discard	d.                                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibct1_u 81+1uint64_t	ii_ibct1_ eUval;1+1s0		0x  81+11uint64_t	i_zerofill                :	 1;1+11uint64_t	i_rsvd_21	  :	 3;1+11uint64_t	i_notify		FF:	 1;1+11uint64_t	i_rsvd_1		  :	 3;1+11uint64_t	i_poison1	  :	 1;1+11uint64_t	i_rsvd	1	  :	55;1+1}Fii_ibct1_fld_s;1+} ii_ibct1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e address6to which t e WINV is sent.       *	+ * ThisCaddress6has to be cache lina aligne7.                           *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibna1_u 81+1uint64_t	ii_ibna1_ eUval;1+1s0		0x  81+11uint64_t	i_rsvd_1                  :	 7;1+11uint64_t	i_addr	1	  :	33;1+11uint64_t       i_rsvd                    :FFFFF24;1+1}Fii_ibna1_fld_s;1+} ii_ibna1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA contains t e programma_le level6as well6as the node   *	+ * ID6and PI un/t of * e process 4 to which t e inDMArupt will be       *	+ * sent.                                                                *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ibia1_u 81+1uint64_t	ii_ibia1_ eUval;1+1s0		0x  81+11uint64_t	i_pi_id                   :	 1;1+11uint64_t	i_node_id1	  :	 8;1+11uint64_t	i_rsvd_1		  :	 7;1+11uint64_t	i_level1		  :	 7;1+11uint64_t	i_rsvd	1	  :	41;1+1}Fii_ibia1_fld_s;1+} ii_ibia1_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *  This  eUTODMA dMfin	s * e resources that feed informa1ion into      *	+ * the two performance counDMAs locaied in the IO Performance           *	+ * Profiling ReUTODMA. There are 176differeni quantities that can be    *	+ * measur	7. Giv=n these 176differeni op1ions, the two performance      *	+ * counDMAs havn615 of * em in common; menu selec1ions 0 * rough 0xE    *	+ * are idMntical for each performance counDMA. As	for the other two     *	+ * op1ions, ona isCavaila_le *rom ona performance counDMA6and th=       *	+ * other isCavaila_le *rom the other performance counDMA. Hence, the    *	+ * II supporDs all 17*16=272 possi_le combinations of quantities to     *	+ * measur	.                                                             *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ipcr_u 81+1uint64_t	ii_ipcr_ eUval;1+1s0		0x  81+11uint64_t	i_ippr0_c                 :	 4;1+11uint64_t	i_ippr1_c1	  :	 4;1+11uint64_t	i_icct	1	  :	 8;1+11uint64_t       i_rsvd                    :FFFFF48;1+1}Fii_ipcr_fld_s;1+} ii_ipcr_u_t;6+	+	+/************************************************************************	+ *                                                                      *	+ *                                                                      *	+ *                                                                      *	+ ************************************************************************/	+	+A_4,_}, un/onFii_ippr_u 81+1uint64_t	ii_ippr_ eUval;1+1s0		0x  81+11uint64_t	i_ippr0                   :	32;1+11uint64_t	i_ippr1	1	  :	32;1+1}Fii_ippr_fld_s;1+} ii_ippr_u_t;6+	+	+	+/**************************************************************************	+ *                                                                        *	+ * The following dMfin	s which were not formed into s0		0xur	s are        *	+ * proba_ly indMntical to another  eUTODMA,6and th= name of * e           *	+ *  eUTODMA is provided against each of * es=  eUTODMAs. This             *	+ * informa1ion needs to be checke7	carefully                              *	+ *                                                                        *	+ *           IIO_ICRB1_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB1_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB1_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB1_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB1_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB2_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB2_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB2_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB2_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB2_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB3_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB3_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB3_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB3_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB3_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB4_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB4_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB4_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB4_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB4_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB5_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB5_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB5_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB5_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB5_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB6_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB6_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB6_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB6_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB6_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB7_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB7_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB7_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB7_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB7_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB8_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB8_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB8_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB8_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB8_E                IIO_ICRB0_E                       *	+ *           IIO_ICRB9_A                IIO_ICRB0_A                       *	+ *           IIO_ICRB9_B                IIO_ICRB0_B                       *	+ *           IIO_ICRB9_C                IIO_ICRB0_C                       *	+ *           IIO_ICRB9_D                IIO_ICRB0_D                       *	+ *           IIO_ICRB9_E                IIO_ICRB0_E                       *	+ *           IIO_ICRBA_A                IIO_ICRB0_A                       *	+ *           IIO_ICRBA_B                IIO_ICRB0_B                       *	+ *           IIO_ICRBA_C                IIO_ICRB0_C                       *	+ *           IIO_ICRBA_D                IIO_ICRB0_D                       *	+ *           IIO_ICRBA_E                IIO_ICRB0_E                       *	+ *           IIO_ICRBB_A                IIO_ICRB0_A                       *	+ *           IIO_ICRBB_B                IIO_ICRB0_B                       *	+ *           IIO_ICRBB_C                IIO_ICRB0_C                       *	+ *           IIO_ICRBB_D                IIO_ICRB0_D                       *	+ *           IIO_ICRBB_E                IIO_ICRB0_E                       *	+ *           IIO_ICRBC_A                IIO_ICRB0_A                       *	+ *           IIO_ICRBC_B                IIO_ICRB0_B                       *	+ *           IIO_ICRBC_C                IIO_ICRB0_C                       *	+ *           IIO_ICRBC_D                IIO_ICRB0_D                       *	+ *           IIO_ICRBC_E                IIO_ICRB0_E                       *	+ *           IIO_ICRBD_A                IIO_ICRB0_A                       *	+ *           IIO_ICRBD_B                IIO_ICRB0_B                       *	+ *           IIO_ICRBD_C                IIO_ICRB0_C                       *	+ *           IIO_ICRBD_D                IIO_ICRB0_D                       *	+ *           IIO_ICRBD_E                IIO_ICRB0_E                       *	+ *           IIO_ICRBE_A                IIO_ICRB0_A                       *	+ *           IIO_ICRBE_B                IIO_ICRB0_B                       *	+ *           IIO_ICRBE_C                IIO_ICRB0_C                       *	+ *           IIO_ICRBE_D                IIO_ICRB0_D                       *	+ *           IIO_ICRBE_E                IIO_ICRB0_E                       *	+ *                                                                        *	+ **************************************************************************/	+	+	+/*	+ * Slightly friendliMA names	for some common  eUTODMAs.	+ */	+#dMfin	 IIO_WIDGET              IIO_WID      /* Widget idMntifica1ion */	+#dMfin	 IIO_WIDGET_STAT         IIO_WSTAT    /* Widget staius  eUTODMA */	+#dMfin	 IIO_WIDGET_CTRL         IIO_WCR      /* Widget control  eUTODMA */	+#dMfin	 IIO_PROTECT             IIO_ILAPR    /* IO inDMAface protec1ion */	+#dMfin	 IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protec1 ovMAride */	+#dMfin	 IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */	+#dMfin	 IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */	+#dMfin	 IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */	+#dMfin	 IIO_LLP_CSR             IIO_ILCSR    /* LLP control and staius */	+#dMfin	 IIO_LLP_LOG             IIO_ILLR     /* LLP log */	+#dMfin	 IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit counD timeout*/	+#dMfin	 IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */	+#dMfin	 IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */	+#dMfin	 IIO_IGFX_0 		IIO_IGFX0	+#dMfin	 IIO_IGFX_1 		IIO_IGFX1	+#dMfin	 IIO_IBCT_0		IIO_IBCT0	+#dMfin	 IIO_IBCT_1		IIO_IBCT1	+#dMfin	 IIO_IBLS_0		IIO_IBLS0	+#dMfin	 IIO_IBLS_1		IIO_IBLS1	+#dMfin	 IIO_IBSA_0		IIO_IBSA0	+#dMfin	 IIO_IBSA_1		IIO_IBSA1	+#dMfin	 IIO_IBDA_0		IIO_IBDA0	+#dMfin	 IIO_IBDA_1		IIO_IBDA1	+#dMfin	 IIO_IBNA_0		IIO_IBNA0	+#dMfin	 IIO_IBNA_1		IIO_IBNA1	+#dMfin	 IIO_IBIA_0		IIO_IBIA0	+#dMfin	 IIO_IBIA_1		IIO_IBIA1	+#dMfin	 IIO_IOPRB_0		IIO_IPRB0	+	+#dMfin	 IIO_PRTE_A(_x)		(IIO_IPRTE0_A + (8 * (_x)))	+#dMfin	 IIO_PRTE_B(_x)		(IIO_IPRTE0_B + (8 * (_x)))	+#dMfin	 IIO_NUM_PRTES		8	/* Total numbMA of PRB ia_le entries */	+#dMfin	 IIO_WIDPRTE_A(x)	IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */	+#dMfin	 IIO_WIDPRTE_B(x)	IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */	+	+#dMfin	 IIO_NUM_IPRBS 		(9) 	+	+#dMfin	 IIO_LLP_CSR_IS_UP               0x00002000	+#dMfin	 IIO_LLP_CSR_LLP_STAT_MASK       0x00003000	+#dMfin	 IIO_LLP_CSR_LLP_STAT_SHFT       12	+	+#dMfin	 IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */	+#dMfin	 IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence NumbMA errors */	+	+/* key to IIO_PROTECT_OVRRD */	+#dMfin	 IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */	+	+/* BTE  eUTODMA names	*/	+#dMfin	 IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/staius 0	*/	+#dMfin	 IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE sourceCaddress6 0	*/	+#dMfin	 IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest.Caddress60	*/	+#dMfin	 IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/*erminate60	*/	+#dMfin	 IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notifica1ion 0	*/	+#dMfin	 IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE inDMArupt 0	*/	+#dMfin	 IIO_BTE_OFF_0           0            /* Base offset *rom BTE 0  eUs.	*/	+#dMfin	 IIO_BTE_OFF_1   	(IIO_IBLS_1 - IIO_IBLS_0) /* Offset *rom base to BTE 1 */	+	+/* BTE  eUTODMA offsets *rom base */	+#dMfin	 BTEOFF_STAT             0	+#dMfin	 BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)	+#dMfin	 BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)	+#dMfin	 BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)	+#dMfin	 BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)	+#dMfin	 BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)	+	+	+/* names	use7	in shub diags	*/	+#dMfin	 IIO_BASE_BTE0   IIO_IBLS_0			+#dMfin	 IIO_BASE_BTE1   IIO_IBLS_1			+	+/*	+ * Macro which tak	s * e widget numbMA,6and returns t e	+ * IO PRB address6of * at widget.	+ * value _x is expec1e7	to b	 a widget numbMA in the range	+ * 0, 8 - 0xF	+ */	+#dMfin	 IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \	+                        (_x) : \	+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )	+	+	+/* GFX FlowFControl Node/Widget ReUTODMA */	+#dMfin	 IIO_IGFX_W_NUM_BITS	4	/* size6of widget num *ield */	+#dMfin	 IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)	+#dMfin	 IIO_IGFX_W_NUM_SHIFT	0	+#dMfin	 IIO_IGFX_PI_NUM_BITS	1	/* size6of PI num *ield */	+#dMfin	 IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)	+#dMfin	 IIO_IGFX_PI_NUM_SHIFT	4	+#dMfin	 IIO_IGFX_N_NUM_BITS	8	/* size6of node num *ield */	+#dMfin	 IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)	+#dMfin	 IIO_IGFX_N_NUM_SHIFT	5	+#dMfin	 IIO_IGFX_P_NUM_BITS	1	/* size6of process 4 num *ield */	+#dMfin	 IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)	+#dMfin	 IIO_IGFX_P_NUM_SHIFT	16	+#dMfin	 IIO_IGFX_INIT(widget, pi, node, cpu)				(\	+	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \	+	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \	+	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \	+	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))	+	+	+/* Scratch  eUTODMAs (all bits availa_le) */	+#dMfin	 IIO_SCRATCH_REG0        IIO_ISCR0	+#dMfin	 IIO_SCRATCH_REG1        IIO_ISCR1	+#dMfin	 IIO_SCRATCH_MASK        0xffffffffffffffffUL	+	+#dMfin	 IIO_SCRATCH_BIT0_0      0x0000000000000001UL	+#dMfin	 IIO_SCRATCH_BIT0_1      0x0000000000000002UL	+#dMfin	 IIO_SCRATCH_BIT0_2      0x0000000000000004UL	+#dMfin	 IIO_SCRATCH_BIT0_3      0x0000000000000008UL	+#dMfin	 IIO_SCRATCH_BIT0_4      0x0000000000000010UL	+#dMfin	 IIO_SCRATCH_BIT0_5      0x0000000000000020UL	+#dMfin	 IIO_SCRATCH_BIT0_6      0x0000000000000040UL	+#dMfin	 IIO_SCRATCH_BIT0_7      0x0000000000000080UL	+#dMfin	 IIO_SCRATCH_BIT0_8      0x0000000000000100UL	+#dMfin	 IIO_SCRATCH_BIT0_9      0x0000000000000200UL	+#dMfin	 IIO_SCRATCH_BIT0_A      0x0000000000000400UL	+	+#dMfin	 IIO_SCRATCH_BIT1_0      0x0000000000000001UL	+#dMfin	 IIO_SCRATCH_BIT1_1      0x0000000000000002UL	+/* IO Transla1ion Ta_le Entries */	+#dMfin	 IIO_NUM_ITTES   7               /* ITTEs numbMAe7	0..6 */	+                                        /* Hw manuals numbMA * em 1..7! */	+/*	+ * IIO_IMEM ReUTODMA *ields.	+ */	+#dMfin	 IIO_IMEM_W0ESD  0x1UL             /* Widget 0 shut down due to error */	+#dMfin	 IIO_IMEM_B0ESD  (1UL << 4)        /* BTE 0 shut down due to error */	+#dMfin	 IIO_IMEM_B1ESD  (1UL << 8)        /* BTE 1 Shut down due to error */	+	+/*	+ * As a permaneni workaround for a bug in the PI side of * e shub, we've	+ *  edMfin	d big window 7 as small window 0.	+ XXX do	s * is still apply for SN1??	+ */	+#dMfin	 HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)	+	+/*	+ * Usecth_ top big window as a surrogate6for the first small window	+ */	+#dMfin	 SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW	+	+#dMfin	 ILCSR_WARM_RESET        0x100	+	+/*	+ * CRB manipula1ion macros	+ *      Th_ CRB macros are slightly complicaied, since * ere are up to	+ *      four  eUTODMAs ass ciaied with each CRB entry.	+ */	+#dMfin	 IIO_NUM_CRBS            15      /* NumbMA of CRBs */	+#dMfin	 IIO_NUM_PC_CRBS         4       /* NumbMA of partial,cache CRBs */	+#dMfin	 IIO_ICRB_OFFSET         8	+#dMfin	 IIO_ICRB_0              IIO_ICRB0_A	+#dMfin	 IIO_ICRB_ADDR_SHFT	2	/* Shift6to get propMA6address6*/	+/* XXX - This is now tunea_le:	+        #dMfin	 IIO_FIRST_PC_ENTRY 12	+ */	+	+#dMfin	 IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))	+#dMfin	 IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))	+#dMfin	 IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))	+#dMfin	 IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))	+#dMfin	 IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))	+	+#dMfin	 TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)	+	+/*	+ * values	for "ecode" *ield	+ */	+#dMfin	 IIO_ICRB_ECODE_DERR     0       /* Direc1ory error due to IIO access */	+#dMfin	 IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */	+#dMfin	 IIO_ICRB_ECODE_WERR     2       /* Wriie6error by IIO access	+                                         * e.g. WINV to a Read only lina. */	+#dMfin	 IIO_ICRB_ECODE_AERR     3       /* Access error cause7	by IIO access */	+#dMfin	 IIO_ICRB_ECODE_PWERR    4       /* Error on partial,wriie       */	+#dMfin	 IIO_ICRB_ECODE_PRERR    5       /* Error on partial,rea7	       */	+#dMfin	 IIO_ICRB_ECODE_TOUT     6       /* CRB timeout befor	 deallocaiing */	+#dMfin	 IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt ha7	error bit */	+	+/*	+ * Values	for *ield imsgA_4,	+ */	+#dMfin	 IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage *rom Xtalk */	+#dMfin	 IIO_ICRB_IMSGT_BTE      1       /* Incoming message *rom BTE    */	+#dMfin	 IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message *rom SN1 net */	+#dMfin	 IIO_ICRB_IMSGT_CRB      3       /* Incoming message *rom CRB ???  */	+	+/*	+ * values	for *ield initiator.	+ */	+#dMfin	 IIO_ICRB_INIT_XTALK     0       /* Message originate7	in xtalk  */	+#dMfin	 IIO_ICRB_INIT_BTE0      0x1     /* Message originate7	in BTE 0  */	+#dMfin	 IIO_ICRB_INIT_SN1NET    0x2     /* Message originate7	in SN1net */	+#dMfin	 IIO_ICRB_INIT_CRB       0x3     /* Message originate7	in CRB ?  */	+#dMfin	 IIO_ICRB_INIT_BTE1      0x5     /* MEssage originate7	in BTE 1  */	+	+/*	+ * NumbMA of credits Hub widget has while sending req/response to	+ * xbow.	+ * Value of 3 is  equir	d by Xbow 1.1	+ * We may b	 a_le to increase this to 4 with Xbow 1.2.	+ */	+#dMfin	       HUBII_XBOW_CREDIT       3	+#dMfin	       HUBII_XBOW_REV2_CREDIT  4	+	+/*	+ * NumbMA of credits * at xtalk devices should use wh=n communicaiing	+ * with a SHub (depth of SHub's queue).	+ */	+#dMfin	 HUB_CREDIT 4	+	+/*	+ * Some IIO_PRB *ields	+ */	+#dMfin	 IIO_PRB_MULTI_ERR	(1LL << 63)	+#dMfin	 IIO_PRB_SPUR_RD		(1LL << 51)	+#dMfin	 IIO_PRB_SPUR_WR		(1LL << 50)	+#dMfin	 IIO_PRB_RD_TO		(1LL << 49)	+#dMfin	 IIO_PRB_ERROR		(1LL << 48)	+	+/*************************************************************************	+	+ Some of * e IIO *ield masks and shifts are dMfin	d  ere.	+ This is in orde4 to maintain compaiibility	in SN0 and SN1 code	+ 
+**************************************************************************/	+	+/*	+ * ICMR  eUTODMA *ields	+ * (Note: * e IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD *rom Hub are not	+ * present	in SHub)	+ */	+	+#dMfin	 IIO_ICMR_CRB_VLD_SHFT   20	+#dMfin	 IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)	+	+#dMfin	 IIO_ICMR_FC_CNT_SHFT    16	+#dMfin	 IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)	+	+#dMfin	 IIO_ICMR_C_CNT_SHFT     4	+#dMfin	 IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)	+	+#dMfin	 IIO_ICMR_PRECISE        (1UL << 52)	+#dMfin	 IIO_ICMR_CLR_RPPD       (1UL << 13)	+#dMfin	 IIO_ICMR_CLR_RQPD       (1UL << 12)	+	+/*	+ * IIO PIO Deallocaiion  eUTODMA *ield masks : (IIO_IPDR)	+ XXX present	but not needed in bedrock?  Seecth_ manual.	+ */	+#dMfin	 IIO_IPDR_PND    (1 << 4)	+	+/*	+ * IIO CRB deallocaiion  eUTODMA *ield masks: (IIO_ICDR)	+ */	+#dMfin	 IIO_ICDR_PND    (1 << 4)	+	+/* 	+ * IO BTE Length/Staius (IIO_IBLS)  eUTODMA bit *ield dMfinitions	+ */	+#dMfin	 IBLS_BUSY		(0x1UL << 20)	+#dMfin	 IBLS_ERROR_SHFT		16	+#dMfin	 IBLS_ERROR		(0x1UL << IBLS_ERROR_SHFT)	+#dMfin	 IBLS_LENGTH_MASK	0xffff	+	+/*	+ * IO BTE Control/Terminate6 eUTODMA (IBCT)  eUTODMA bit *ield dMfinitions	+ */	+#dMfin	 IBCT_POISON		(0x1UL << 8)	+#dMfin	 IBCT_NOTIFY		(0x1UL << 4)	+#dMfin	 IBCT_ZFIL_MODE		(0x1UL << 0)	+	+/*	+ * IIO Incoming Error Packet Hea7MA (IIO_IIEPH1/IIO_IIEPH2)	+ */	+#dMfin	 IIEPH1_VALID		(1UL << 44)	+#dMfin	 IIEPH1_OVERRUN		(1UL << 40)	+#dMfin	 IIEPH1_ERR_TYPE_SHFT	32	+#dMfin	 IIEPH1_ERR_TYPE_MASK	0xf	+#dMfin	 IIEPH1_SOURCE_SHFT	20	+#dMfin	 IIEPH1_SOURCE_MASK	11	+#dMfin	 IIEPH1_SUPPL_SHFT	8	+#dMfin	 IIEPH1_SUPPL_MASK	11	+#dMfin	 IIEPH1_CMD_SHFT		0	+#dMfin	 IIEPH1_CMD_MASK		7	+	+#dMfin	 IIEPH2_TAIL		(1UL << 40)	+#dMfin	 IIEPH2_ADDRESS_SHFT	0	+#dMfin	 IIEPH2_ADDRESS_MASK	38	+	+#dMfin	 IIEPH1_ERR_SHORT_REQ	2	+#dMfin	 IIEPH1_ERR_SHORT_REPLY	3	+#dMfin	 IIEPH1_ERR_LONG_REQ	4	+#dMfin	 IIEPH1_ERR_LONG_REPLY	5	+	+/*	+ * IO Error Clear  eUTODMA bit *ield dMfinitions	+ */	+#dMfin	 IECLR_PI1_FWD_INT	(1UL << 31)  /* clear PI1_FORWARD_INT in iidsr */	+#dMfin	 IECLR_PI0_FWD_INT	(1UL << 30)  /* clear PI0_FORWARD_INT in iidsr */	+#dMfin	 IECLR_SPUR_RD_HDR	(1UL << 29)  /* clear valid bit in ixss  eU */	+#dMfin	 IECLR_BTE1		(1UL << 18)  /* clear bie6error 1 */	+#dMfin	 IECLR_BTE0		(1UL << 17)  /* clear bie6error 0 */	+#dMfin	 IECLR_CRAZY		(1UL << 16)  /* clear crazy bit in wstai  eU */	+#dMfin	 IECLR_PRB_F		(1UL << 15)  /* clear err bit in PRB_F  eU */	+#dMfin	 IECLR_PRB_E		(1UL << 14)  /* clear err bit in PRB_E  eU */	+#dMfin	 IECLR_PRB_D		(1UL << 13)  /* clear err bit in PRB_D  eU */	+#dMfin	 IECLR_PRB_C		(1UL << 12)  /* clear err bit in PRB_C  eU */	+#dMfin	 IECLR_PRB_B		(1UL << 11)  /* clear err bit in PRB_B  eU */	+#dMfin	 IECLR_PRB_A		(1UL << 10)  /* clear err bit in PRB_A  eU */	+#dMfin	 IECLR_PRB_9		(1UL << 9)   /* clear err bit in PRB_9  eU */	+#dMfin	 IECLR_PRB_8		(1UL << 8)   /* clear err bit in PRB_8  eU */	+#dMfin	 IECLR_PRB_0		(1UL << 0)   /* clear err bit in PRB_0  eU */	+	+/*	+ * IIO CRB control  eUTODMA Fields: IIO_ICCR 	+ */	+#dMfin		IIO_ICCR_PENDING	(0x10000)	+#dMfin		IIO_ICCR_CMD_MASK	(0xFF)	+#dMfin		IIO_ICCR_CMD_SHFT	(7)	+#dMfin		IIO_ICCR_CMD_NOP	(0x0)	/* No Op */	+#dMfin		IIO_ICCR_CMD_WAKE	(0x100) /* Reactivate6CRB entry and process */	+#dMfin		IIO_ICCR_CMD_TIMEOUT	(0x200)	/* Make CRB timeout & mark invalid */	+#dMfin		IIO_ICCR_CMD_EJECT	(0x400)	/* Contents6of entry wriit=n to memory 1+11	1	 * via a WB1+11	1	 */	+#dMfin		IIO_ICCR_CMD_FLUSH	(0x800)	+	+/*	+ *	+ * CRB ReUTODMA dMscrip1ion.	+ *	+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING	+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING	+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING	+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING	+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING	+ *	+ * Many of * e *ields	in CRB are staius bits use7	by hardware	+ * *or implemeniaiion of * e protocol. It's very dangerous to	+ * mess6around with t e CRB  eUTODMAs.	+ *	+ * It's OK to rea7	t e CRB  eUTODMAs6and try to make sense out of * e	+ * *ields	in CRB.	+ *	+ * Updaiing CRB  equir	s all activities in Hub IIO to b	 quiMsced.	+ * otherwise, a wriie *o CRB could coArupt other CRB entriMs.	+ * CRBs are  ere only as a back door peek	to shub IIO's staius.	+ * QuiMscing implies  no dmas no PIOs	+ * either direc1ly from the cpu or *rom sn0net.	+ * this is not something t at can be dona easily. So, AVOID updaiing	+ * CRBs.	+ */	+	+/*	+ * Easy access macros *or CRBs, all 5  eUTODMAs (A-E)	+ */	+A_4,_}, ii_icrb0_a_u_t icrba_t;6+#dMfin	 a_sidn          ii_icrb0_a_fld_s.ia_sidn6+#dMfin	 a_tnum          ii_icrb0_a_fld_s.ia_tnum6+#dMfin	 a_addr          ii_icrb0_a_fld_s.ia_addr6+#dMfin	 a_valid         ii_icrb0_a_fld_s.ia_vld	+#dMfin	 a_iow           ii_icrb0_a_fld_s.ia_iow	+#dMfin	 a_ eUvalue	ii_icrb0_a_ eUval	+	+A_4,_}, ii_icrb0_b_u_t icrbb_t;6+#dMfin	 b_use_old       ii_icrb0_b_fld_s.ib_use_old6+#dMfin	 b_imsgA_4,      ii_icrb0_b_fld_s.ib_imsgA_4,	+#dMfin	 b_imsg          ii_icrb0_b_fld_s.ib_imsg	+#dMfin	 b_initiator     ii_icrb0_b_fld_s.ib_init	+#dMfin	 b_exc           ii_icrb0_b_fld_s.ib_exc	+#dMfin	 b_ackcnt        ii_icrb0_b_fld_s.ib_ack_cnt	+#dMfin	 b_resp          ii_icrb0_b_fld_s.ib_resp	+#dMfin	 b_ack           ii_icrb0_b_fld_s.ib_ack	+#dMfin	 b_hold          ii_icrb0_b_fld_s.ib_hold6+#dMfin	 b_wb            ii_icrb0_b_fld_s.ib_wb	+#dMfin	 b_intvn         ii_icrb0_b_fld_s.ib_intvn	+#dMfin	 b_stall_ib      ii_icrb0_b_fld_s.ib_stall_ib	+#dMfin	 b_stall_int     ii_icrb0_b_fld_s.ib_stall__intr	+#dMfin	 b_stall_bie_0   ii_icrb0_b_fld_s.ib_stall__bie_0	+#dMfin	 b_stall_bie_1   ii_icrb0_b_fld_s.ib_stall__bie_1	+#dMfin	 b_error         ii_icrb0_b_fld_s.ib_error	+#dMfin	 b_ecode         ii_icrb0_b_fld_s.ib_errcode	+#dMfin	 b_lnetuce       ii_icrb0_b_fld_s.ib_ln_uce	+#dMfin	 b_mark          ii_icrb0_b_fld_s.ib_mark	+#dMfin	 b_xerr          ii_icrb0_b_fld_s.ib_xt_err	+#dMfin	 b_reUvalue	ii_icrb0_b_ eUval	+	+A_4,_}, ii_icrb0_c_u_t icrbc_t;6+#dMfin	 c_suppl         ii_icrb0_c_fld_s.ic_suppl6+#dMfin	 c_barrop        ii_icrb0_c_fld_s.ic_bo6+#dMfin	 c_doresp        ii_icrb0_c_fld_s.ic_resprqd6+#dMfin	 c_gbr           ii_icrb0_c_fld_s.ic_gbr6+#dMfin	 c_bt=num        ii_icrb0_c_fld_s.ic_bie_num6+#dMfin	 c_cohtrans      ii_icrb0_c_fld_s.ic_ct6+#dMfin	 c_xtsize6       ii_icrb0_c_fld_s.ic_size6+#dMfin	 c_sourceC       ii_icrb0_c_fld_s.ic_source6+#dMfin	 c_reUvalue	ii_icrb0_c_ eUval	+	+	+A_4,_}, ii_icrb0_d_u_t icrbd_t;6+#dMfin	 d_sleep         ii_icrb0_d_fld_s.id_sleep6+#dMfin	 d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt	+#dMfin	 d_pripsc        ii_icrb0_d_fld_s.id_pr_psc	+#dMfin	 d_bieop         ii_icrb0_d_fld_s.id_bie_op	+#dMfin	 d_bieaddr       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/	+#dMfin	 d_bena_le       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/	+#dMfin	 d_reUvalue	ii_icrb0_d_ eUval	+	+A_4,_}, ii_icrb0_e_u_t icrbe_t;6+#dMfin	 icrbe_ctxtvld   ii_icrb0_e_fld_s.ie_cvld	+#dMfin	 icrbe_toutvld   ii_icrb0_e_fld_s.ie_tvld	+#dMfin	 icrbe_context   ii_icrb0_e_fld_s.ie_context	+#dMfin	 icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout	+#dMfin	 e_reUvalue	ii_icrb0_e_ eUval	+	+	+/* NumbMA of widgets supporDe7	by shub */	+#dMfin	 HUB_NUM_WIDGET          9	+#dMfin	 HUB_WIDGET_ID_MIN       0x8	+#dMfin	 HUB_WIDGET_ID_MAX       0xf	+	+#dMfin	 HUB_WIDGET_PART_NUM     0xc120	+#dMfin	 MAX_HUBS_PER_XBOW       2	+	+/* A few mor	 #dMfin	s *or backwards compaiibility	*/	+#dMfin	 iprb_t          ii_iprb0_u_t	+#dMfin	 iprb_ eUval     ii_iprb0_ eUval	+#dMfin	 iprb_mult_err	ii_iprb0_fld_s.i_mult_err	+#dMfin	 iprb_spur_rd	ii_iprb0_fld_s.i_spur_rd	+#dMfin	 iprb_spur_wr	ii_iprb0_fld_s.i_spur_wr	+#dMfin	 iprb_rd_to	ii_iprb0_fld_s.i_rd_to	+#dMfin	 iprb_ovflow     ii_iprb0_fld_s.i_of_cnt	+#dMfin	 iprb_error      ii_iprb0_fld_s.i_error	+#dMfin	 iprb_ff         ii_iprb0_fld_s.i_f	+#dMfin	 iprb_mode       ii_iprb0_fld_s.i_m	+#dMfin	 iprb_bnakctr    ii_iprb0_fld_s.i_nb	+#dMfin	 iprb_anakctr    ii_iprb0_fld_s.i_na	+#dMfin	 iprb_xtalkctr   ii_iprb0_fld_s.i_c	+	+#dMfin	 LNK_STAT_WORKING        0x2		/* LLP is working */	+	+#dMfin	 IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gona crazy */	+#dMfin	 IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */	+#dMfin	 IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */	+#dMfin	 IIO_WSTAT_TXRETRY_SHFT  (16)	+#dMfin	 IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \	+                                          IIO_WSTAT_TXRETRY_MASK)	+	+/* NumbMA of II perf. counDMAs we can multiplex at once */	+	+#dMfin	 IO_PERF_SETS	32	+	+/* Bit6for the widget in inbound access  eUTODMA */	+#dMfin	 IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))	+/* Bit6for the widget in outbound access  eUTODMA */	+#dMfin	 IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))	+	+/* NOTE: The following dMfin	 assumes that we are going to get	+ * widget numbMAs *rom 8 * ru F6and th= device numbMAs within	+ * widget *rom 0 * ru 7.	+ */	+#dMfin	 IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))	+	+/* IO InDMArupt Destination ReUTODMA */	+#dMfin	 IIO_IIDSR_SENT_SHIFT    28	+#dMfin	 IIO_IIDSR_SENT_MASK     0x30000000	+#dMfin	 IIO_IIDSR_ENB_SHIFT     24	+#dMfin	 IIO_IIDSR_ENB_MASK      0x01000000	+#dMfin	 IIO_IIDSR_NODE_SHIFT    9	+#dMfin	 IIO_IIDSR_NODE_MASK     0x000ff700	+#dMfin	 IIO_IIDSR_PI_ID_SHIFT   8	+#dMfin	 IIO_IIDSR_PI_ID_MASK    0x00000100	+#dMfin	 IIO_IIDSR_LVL_SHIFT     0	+#dMfin	 IIO_IIDSR_LVL_MASK      0x000000ff	+	+/* Xtalk timeout * reshhold  eUTODMA (IIO_IXTT) */	+#dMfin	 IXTT_RRSP_TO_SHFT	55	   /* rea7	response timeout */	+#dMfin	 IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)	+#dMfin	 IXTT_RRSP_PS_SHFT	32	   /* rea7	responsed TO prescalar */	+#dMfin	 IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)	+#dMfin	 IXTT_TAIL_TO_SHFT	0	   /* tail timeout counDMA6* reshold */	+#dMfin	 IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)	+	+/*	+ * The IO LLP control staius  eUTODMA and widget control  eUTODMA	+ */	+	+A_4,_}, un/onFhubii_wcr_u 81+        uint64_t      wcr_ eU_value;1+        s0		0x 81+1  uint64_t	wcr_widget_id:FFF4,     /* LLP crossbar credit */	+			wcr_tag_mode:	 1,	/* Tag mode */	+			wcr_rsvd1:	 8,	/* Reserved */	+			wcr_xbar_crd:	 3,	/* LLP crossbar credit */	+			wcr_f_bad_pkt:	 1,	/* ForceCbad llp pkt ena_le */	+			wcr_dir_con:	 1,	/* widget direc1 connec1 */	+			wcr_e_t resh:	 5,	/* elasticity	* reshold */	+			wcr_rsvd:	41;	/* unuse7	*/	+        } wcr_*ields_s;1+} hubii_wcr_t;6+	+#dMfin	 iwcr_dir_con    wcr_*ields_s.wcr_dir_con	+	+/* The s0		0xur	s below are dMfin	d to extract and modify t e ii
+performance  eUTODMAs */	+	+/* io_perf_sel6allows * e calle4 to specify what tests will be	+   performe7	*/	+	+A_4,_}, un/onFio_perf_sel681+        uint64_t perf_sel_ eU;1+        s0		0x 81+               uint64_t	perf_ippr0 :FF4,1+11	1perf_ippr1 :FF4,1+11	1perf_ic0x  :FF8,1+11	1perf_rsvd  :F48;1+        } perf_sel_bits;1+} io_perf_sel_t;6+	+/* io_perf_cnt is to extract * e counD from the shub  eUTODMAs. Due to	+   hardware problems * ere is only ona counDMA, not two.	*/	+	+A_4,_}, un/onFio_perf_cnt 81+        uint64_t      perf_cnt;1+        s0		0x 81+               uint64_t	perf_cnt   : 20,1+11	1perf_rsvd2 : 12,1+11	1perf_rsvd1 :F32;1+        } perf_cnt_bits;1+1+} io_perf_cnt_t;6+	+A_4,_}, un/onFiprte_a 81+1uint64_t	entry;1+1s0		0x 81+11uint64_t	i_rsvd_1                  :	 3;1+11uint64_t	i_addr	1	  :	38;1+11uint64_t	i_init			  :	 3;1+11uint64_t	i_source1	  :	 8;1+11uint64_t	i_rsvd			  :	 2;1+11uint64_t	i_widget1	  :	 4;1+11uint64_t	i_to_cnt1	  :	 5;1+11uint64_t       i_vld                     :FFFFF 1;1+1}Fiprte_*ields;1+} iprte_a_t;6+	+#endif /* _ASM_IA64_SN_SHUBIO_H	*/	+	diff -Nru a/include/asm-ia64/un/std.h b/include/asm-ia64/un/std.h
--- a/include/asm-ia64/un/std.h	2005-01-22 14:19:22 -08:00	+++ b/include/asm-ia64/un/std.h	2005-01-25 12:23:46 -08:00	@@ -4,7 +4,7 @@
 /*
  * IA-64 Linux syscall numbMAs and inlina-func1ions.
  *
- * Copyright (C) 1998-2004 Hewlett-Packard Co	+ * Copyright (C) 1998-2005 Hewlett-Packard Co	  *	David MosbMAger-Tang <davidm@hpl.hp.com>
  */	 	@@ -376,15 +376,13 @@
 s0		0x sigac1ion;
 long sys_execve(char __user *filename, char __user * __user *argv,
 			   char __user * __user *envp, s0		0x pt_ eUs * eUs);
-asmlinkage long sys_pipe(long arg0, long arg1, long arg2, long arg3,
-			long arg4, long arg5, long arg6, long arg7, long stack);
+asmlinkage long sys_pipe(void);
 asmlinkage long sys_ptrace(long  equest, pid_t pid,
-			unsigne7 long addr, unsigne7 long data,
-			long arg4, long arg5, long arg6, long arg7, long stack);
+			   unsigne7 long addr, unsigne7 long data);
 asmlinkage long sys_rt_sigac1ion(int sig,
-				const s0		0x sigac1ion __user *act,
-				s0		0x sigac1ion __user *oact,
-				size_t sigsetsize);
+				 const s0		0x sigac1ion __user *act,
+				 s0		0x sigac1ion __user *oact,
+				 size_t sigsetsize);
 
 /*
  * "Condi1ional" syscalls	diff -Nru a/include/asm-mips/ng1.h b/include/asm-mips/ng1.h
--- a/include/asm-mips/ng1.h	2003-04-14 20:10:06 -07:00	+++ /dev/null	We7 Dec 31 16:00:00 196900	@@ -1,55 +0,0 @@
-/*
- * This file is subjec1 to th_ terms and condi1ions of * e GNU General Public
- * License.  Seecth_ file "COPYING" in the main direc1ory of * isCarchive
- * for mor	 details.
- *
- * SGI/NewporD video	card ioctl dMfinitions	- */	-#ifn_}, _ASM_NG1_H	-#dMfin	 _ASM_NG1_H	-
-A_4,_}, s0		0x 81-        inD flags;1-        __u16 w, h;1-        __u16 *ields_sec;1-} ng1_vof_info_t;6-
-s0		0x ng1_info 81-	s0		0x gfx_info gfx_info;6-	__u8 boardrev;1-        __u8  ex3rev;1-        __u8 vc2rev;1-        __u8 monitorD_4,;1-        __u8 videoinstalled;1-        __u8 mcrev;1-        __u8 bitplanes;1-        __u8 xmap9rev;1-        __u8 cmaprev;1-        ng1_vof_info_t ng1_vof_info;1-        __u8 bt445rev;1-        __u8 panelD_4,;1-};6-
-#dMfin	 GFX_NAME_NEWPORT "NG1"6-
-/* ioctls */	-#dMfin	 NG1_SET_CURSOR_HOTSPOT 21001
-s0		0x ng1_set_cursor_hotspox 81-	unsigne7 shorD xhot;1-        unsigne7 shorD yhot;1-};6-
-#dMfin	 NG1_SETDISPLAYMODE     21006
-s0		0x ng1_setdisplaymode_args 81-        inD wid;1-        unsigne7 inD mode;1-};6-
-#dMfin	 NG1_SETGAMMARAMP0      21007
-s0		0x ng1_setgammaramp_args 81-        unsigne7 char r	d   [256];1-        unsigne7 char green [256];1-        unsigne7 char blue  [256];1-};6-
-#endif /* _ASM_NG1_H */	diff -Nru a/include/asm-mips/ng1hw.h b/include/asm-mips/ng1hw.h
--- a/include/asm-mips/ng1hw.h	2003-06-15 16:56:21 -07:00	+++ /dev/null	We7 Dec 31 16:00:00 196900	@@ -1,219 +0,0 @@
-/*
- * ng1hw.h: Tweaks * e newporD.h s0		0xur	s and dMfinitions to be compaiible
- * 	    with IRIX.  Quiie ugly,	but ii works.
- *
- * Copyright (C) 1999 Ulf Carlsson (ulfc@* epuffingroup.com)	- */	-#ifn_}, _SGI_NG1HW_H	-#dMfin	 _SGI_NG1HW_H	-	-#include <video/newporD.h>6-
-#dMfin	  ex3regs	newporD_ exregs
-#dMfin	 configregs	newporD_cregs
-#dMfin	 float_long	npf eU_t	-
-A_4,_}, s0		0x newporD_ exregs Rex3regs;
-A_4,_}, s0		0x newporD_cregs Configregs;
-A_4,_}, un/onFnp_dcb DCB_ eU;1-6-
-/* It looks like I can't do a simple tweak with t is st		0xur	 because * e IRIX
- * vMAs/onFis just *too* stupid.  Ok,  ere's a new vMAs/onFof it..	- */	-
-s0		0x  ex3chip 81-	s0		0x newporD_ exregs set;1-	unsigne7 long _unuse70[0x16e];1-	s0		0x newporD_ exregs go;1-	unsigne7 long _unuse71[0x22e];1-	s0		0x 81-		s0		0x newporD_cregs set;1-		unsigne7 long _unuse72[0x1ef];1-		s0		0x newporD_cregs go;1-	} p1;1-};6-
-A_4,_}, s0		0x  ex3chip  ex3Chip;
-A_4,_}, s0		0x  ex3chip Rex3chip;6-
-/* Tweak th= defin	s .. */	-
-#dMfin	 DM0_OPCODE		NPORT_DMODE0_OPMASK
-#dMfin	 DM0_NOP			NPORT_DMODE0_NOP
-#dMfin	 DM0_READ		NPORT_DMODE0_RD
-#dMfin	 DM0_DRAW		NPORT_DMODE0_DRAW
-#dMfin	 DM0_SCR2SCR		NPORT_DMODE0_S2S	-
-#dMfin	 DM0_ADRMODE_SHIFT	2
-#dMfin	 DM0_ADRMODE		NPORT_DMODE0_AMMASK
-#dMfin	 DM0_SPAN		NPORT_DMODE0_SPAN
-#dMfin	 DM0_BLOCK		NPORT_DMODE0_BLOCK
-#dMfin	 DM0_ILINE		NPORT_DMODE0_ILINE
-#dMfin	 DM0_FLINE		NPORT_DMODE0_FLINE
-#dMfin	 DM0_ALINE		NPORT_DMODE0_ALINE
-#dMfin	 DM0_TLINE		NPORT_DMODE0_TLINE
-#dMfin	 DM0_BLINE               NPORT_DMODE0_BLINE
-
-#dMfin	 DM0_DOSETUP		NPORT_DMODE0_DOSETUP
-#dMfin	 DM0_COLORHOST		NPORT_DMODE0_CHOST
-#dMfin	 DM0_ALPHAHOST		NPORT_DMODE0_AHOST
-#dMfin	 DM0_STOPONX		NPORT_DMODE0_STOPX
-#dMfin	 DM0_STOPONY		NPORT_DMODE0_STOPY
-#dMfin	 DM0_STOPONXY		(NPORT_DMODE0_STOPX | NPORT_DMODE0_STOPY)
-#dMfin	 DM0_SKIPFIRST		NPORT_DMODE0_SK1ST
-#dMfin	 DM0_SKIPLAST		NPORT_DMODE0_SKLST
-#dMfin	 DM0_ENZPATTERN		NPORT_DMODE0_ZPENAB
-#dMfin	 DM0_ENLSPATTERN		NPORT_DMODE0_LISPENAB
-#dMfin	 DM0_LSADVLAST		NPORT_DMODE0_LISLST
-#dMfin	 DM0_LENGTH32		NPORT_DMODE0_L32
-#dMfin	 DM0_ZOPAQUE		NPORT_DMODE0_ZOPQ
-#dMfin	 DM0_LSOPAQUE		NPORT_DMODE0_LISOPQ
-#dMfin	 DM0_SHADE		NPORT_DMODE0_SHADE
-#dMfin	 DM0_LRONLY		NPORT_DMODE0_LRONLY
-#dMfin	 DM0_XYOFFSET		NPORT_DMODE0_XYOFF
-#dMfin	 DM0_CICLAMP		NPORT_DMODE0_CLAMP
-#dMfin	 DM0_ENDPTFILTER		NPORT_DMODE0_ENDPF
-#dMfin		DM0_YSTRIDE		NPORT_DMODE0_YSTR
-
-#dMfin	 DM1_PLANES_SHIFT	0	-/* The r	st of * e DM1 planes defin	s are in newporD.h */	-
-#dMfin	 DM1_DRAWDEPTH_SHIFT	3
-#dMfin	 DM1_DRAWDEPTH_MASK	NPORT_DMODE1_DDMASK
-#dMfin	 DM1_DRAWDEPTH		NPORT_DMODE1_DD24 /* An alias? */	-#dMfin	 DM1_DRAWDEPTH4		NPORT_DMODE1_DD4	-#dMfin	 DM1_DRAWDEPTH8		NPORT_DMODE1_DD8	-#dMfin	 DM1_DRAWDEPTH12		NPORT_DMODE1_DD12	-#dMfin	 DM1_DRAWDEPTH24		NPORT_DMODE1_DD24	-
-#dMfin	 DM1_DBLSRC		NPORT_DMODE1_DSRC
-#dMfin	 DM1_YFLIP		NPORT_DMODE1_YFLIP
-#dMfin	 DM1_RWPACKED		NPORT_DMODE1_RWPCKD	-
-#dMfin	 DM1_HOSTDEPTH_SHIFT 	8
-#dMfin	 DM1_HOSTDEPTH_MASK	NPORT_DMODE1_HDMASK
-#dMfin	 DM1_HOSTDEPTH		NPORT_DMODE1_HD32 /* An alias? */	-#dMfin	 DM1_HOSTDEPTH4		NPORT_DMODE1_HD4	-#dMfin	 DM1_HOSTDEPTH8		NPORT_DMODE1_HD8
-#dMfin	 DM1_HOSTDEPTH12		NPORT_DMODE1_HD12	-#dMfin	 DM1_HOSTDEPTH32		NPORT_DMODE1_HD32	-
-#dMfin	 DM1_RWDOUBLE		NPORT_DMODE1_RWDBL
-#dMfin	 DM1_SWAPENDIAN		NPORT_DMODE1_ESWAP	-
-#dMfin	 DM1_COLORCOMPARE_SHIFT	12	-#dMfin	 DM1_COLORCOMPARE_MASK	NPORT_DMODE1_CCMASK
-#dMfin	 DM1_COLORCOMPARE	NPORT_DMODE1_CCMASK
-#dMfin	 DM1_COLORCOMPLT		NPORT_DMODE1_CCLT
-#dMfin	 DM1_COLORCOMPEQ		NPORT_DMODE1_CCEQ
-#dMfin	 DM1_COLORCOMPGT		NPORT_DMODE1_CCGT	-
-#dMfin	 DM1_RGBMODE		NPORT_DMODE1_RGBMD
-#dMfin	 DM1_ENDITHER		NPORT_DMODE1_DENAB
-#dMfin	 DM1_FASTCLEAR		NPORT_DMODE1_FCLR
-#dMfin	 DM1_ENBLEND		NPORT_DMODE1_BENAB
-
-#dMfin	 DM1_SF_SHIFT		19
-#dMfin	 DM1_SF_MASK   		NPORT_DMODE1_SFMASK
-#dMfin	 DM1_SF			NPORT_DMODE1_SFMASK
-#dMfin	 DM1_SF_ZERO		NPORT_DMODE1_SF0
-#dMfin	 DM1_SF_ONE		NPORT_DMODE1_SF1
-#dMfin	 DM1_SF_DC		NPORT_DMODE1_SFDC
-#dMfin	 DM1_SF_MDC		NPORT_DMODE1_SFMDC
-#dMfin	 DM1_SF_SA		NPORT_DMODE1_SFSA
-#dMfin	 DM1_SF_MSA		NPORT_DMODE1_SFMSA
-
-#dMfin	 DM1_DF_SHIFT		22	/* dfac1or(2:0)	*/	-#dMfin	 DM1_DF_MASK		NPORT_DMODE1_DFMASK
-#dMfin	 DM1_DF			NPORT_DMODE1_DFMASK
-#dMfin	 DM1_DF_ZERO		NPORT_DMODE1_DF0
-#dMfin	 DM1_DF_ONE		NPORT_DMODE1_DF1
-#dMfin	 DM1_DF_SC		NPORT_DMODE1_DFSC	-#dMfin	 DM1_DF_MSC		NPORT_DMODE1_DFMSC	-#dMfin	 DM1_DF_SA		NPORT_DMODE1_DFSA
-#dMfin	 DM1_DF_MSA		NPORT_DMODE1_DFMSA
-
-#dMfin	 DM1_ENBACKBLEND		NPORT_DMODE1_BBENAB
-#dMfin	 DM1_ENPREFETCH		NPORT_DMODE1_PFENAB
-#dMfin	 DM1_BLENDALPHA		NPORT_DMODE1_ABLEND
-
-#dMfin	 DM1_LO_SHIFT		28
-#dMfin	 DM1_LO			NPORT_DMODE1_LOMASK
-#dMfin	 DM1_LO_MASK      	NPORT_DMODE1_LOMASK
-#dMfin	 DM1_LO_ZERO		NPORT_DMODE1_LOZERO
-#dMfin	 DM1_LO_AND		NPORT_DMODE1_LOAND
-#dMfin	 DM1_LO_ANDR		NPORT_DMODE1_LOANDR
-#dMfin	 DM1_LO_SRC		NPORT_DMODE1_LOSRC
-#dMfin	 DM1_LO_ANDI		NPORT_DMODE1_LOANDI
-#dMfin	 DM1_LO_DST		NPORT_DMODE1_LODST
-#dMfin	 DM1_LO_XOR		NPORT_DMODE1_LOXOR
-#dMfin	 DM1_LO_OR		NPORT_DMODE1_LOOR
-#dMfin	 DM1_LO_NOR		NPORT_DMODE1_LONOR
-#dMfin	 DM1_LO_XNOR		NPORT_DMODE1_LOXNOR
-#dMfin	 DM1_LO_NDST		NPORT_DMODE1_LONDST
-#dMfin	 DM1_LO_ORR		NPORT_DMODE1_LOORR
-#dMfin	 DM1_LO_NSRC		NPORT_DMODE1_LONSRC
-#dMfin	 DM1_LO_ORI		NPORT_DMODE1_LOORI
-#dMfin	 DM1_LO_NAND		NPORT_DMODE1_LONAND
-#dMfin	 DM1_LO_ONE		NPORT_DMODE1_LOONE
-
-#dMfin	 SMASK0			NPORT_CMODE_SM0
-#dMfin	 SMASK1			NPORT_CMODE_SM1
-#dMfin	 SMASK2			NPORT_CMODE_SM2
-#dMfin	 SMASK3			NPORT_CMODE_SM3
-#dMfin	 SMASK4			NPORT_CMODE_SM4	-#dMfin	 ALL_SMASKS		0x1f
-
-#dMfin	 CM_CIDMATCH_SHIFT       9	-#dMfin	 CM_CIDMATCH_MASK        NPORT_CMODE_CMSK
-	-#dMfin	 REX3VERSION_MASK	NPORT_STAT_VERS
-#dMfin	 GFXBUSY        		NPORT_STAT_GBUSY
-#dMfin	 BACKBUSY        	NPORT_STAT_BBUSY
-#dMfin	 VRINT           	NPORT_STAT_VRINT
-#dMfin	 VIDEOINT        	NPORT_STAT_VIDINT
-#dMfin	 GFIFO_LEVEL_SHIFT       7
-#dMfin	 GFIFO_LEVEL_MASK        NPORT_STAT_GLMSK
-#dMfin	 BFIFO_LEVEL_SHIFT       13
-#dMfin	 BFIFO_LEVEL_MASK        NPORT_STAT_BLMSK
-#dMfin	 BFIFO_INT        	NPORT_STAT_BFIRQ
-#dMfin	 GFIFO_INT        	NPORT_STAT_GFIRQ
-
-#dMfin	 GIO32MODE		NPORT_CFG_G32MD
-#dMfin	 BUSWIDTH		NPORT_CFG_BWIDTH
-#dMfin	 EXTREGXCVR		NPORT_CFG_ERCVR
-#dMfin	 BFIFODEPTH_SHIFT	3
-#dMfin	 BFIFODEPTH_MASK		NPORT_CFG_BDMSK
-#dMfin	 BFIFOABOVEINT		NPORT_CFG_BFAINT
-#dMfin	 GFIFODEPTH_SHIFT        8	-#dMfin	 GFIFODEPTH_MASK		NPORT_CFG_GDMSK
-#dMfin	 GFIFOABOVEINT		NPORT_CFG_GFAINT
-#dMfin	 TIMEOUT_SHIFT		14
-#dMfin	 TIMEOUT_MASK		NPORT_CFG_TOMSK
-#dMfin	 VREFRESH_SHIFT		17
-#dMfin	 VREFRESH_MASK		NPORT_CFG_VRMSK
-#dMfin	 FB_TYPE			NPORT_CFG_FBTYP
-
-#dMfin	 DCB_DATAWIDTH_MASK	(0x3)
-
-#dMfin	 DCB_CRS_MASK		(0x7 << DCB_CRS_SHIFT)
-#dMfin	 DCB_ADDR_MASK		(0xf << DCB_ADDR_SHIFT)
-#dMfin	 DCB_CSWIDTH_MASK	(0x1f << DCB_CSWIDTH_SHIFT)
-#dMfin	 DCB_CSHOLD_MASK		(0x1f << DCB_CSHOLD_SHIFT)
-#dMfin	 DCB_CSSETUP_MASK	(0x1f << DCB_CSSETUP_SHIFT)
-
-#dMfin	 DCB_SWAPENDIAN		(1 << 28)
-	-#dMfin	 REX3WAIT( ex3)  while (( ex3)->p1.set.staius & GFXBUSY)
-#dMfin	 BFIFOWAIT( ex3)  while (( ex3)->p1.set.staius & BACKBUSY)
-	-#dMfin	 REX3_GIO_ADDR_0         0x1f0f0000	-#dMfin	 REX3_GIO_ADDR_1         0x1f4f0000	-#dMfin	 REX3_GIO_ADDR_2         0x1f8f0000	-#dMfin	 REX3_GIO_ADDR_3         0x1fcf0000	-
-#dMfin	 NG1_XSIZE		1280
-#dMfin	 NG1_YSIZE		1024	-
-#endif	diff -Nru a/include/asm-mips/sgi/sgi.h b/include/asm-mips/sgi/sgi.h
--- a/include/asm-mips/sgi/sgi.h	2003-04-14 20:10:06 -07:00	+++ b/include/asm-mips/sgi/sgi.h	2005-02-03 06:42:40 -08:00	@@ -28,8 +28,8 @@
 	ip26,	/* TFP UP, Indigo2 */	 	ip27,	/* R10k MP, R12k MP, Origin */	 	ip28,	/* R10k UP, Indigo2 */	-	ip30,	-	ip32,1+1ip30,	/* Octane */	+	ip32,	/* O2 */	 };
 
 extern =num sgi_mach sgimach;	diff -Nru a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
--- a/include/asm-ppc/ibm44x.h	2005-01-30 22:22:38 -08:00	+++ b/include/asm-ppc/ibm44x.h	2005-02-03 06:42:41 -08:00	@@ -3,9 +3,9 @@
  *
  * PPC44x dMfinitions	  *
- * Matt PorDer <mporDer@mvista.com>
+ * Matt PorDer <mporDer@kernel.crashing.org>
  *
- * Copyright 2002-2003 MontaVista Software Inc.	+ * Copyright 2002-2005 MontaVista Software Inc.	  *
  * This programFis free software; you can redistribuie  it and/or modify it
  * un7MA  th_ terms of  * e GNU General  Public License as publishe7	by * e	@@ -34,23 +34,55 @@
 /* Low	st TLB slo1 consume7	by * e dMfault pinne7 TLBs */	 #dMfin	 PPC44x_LOW_SLOT		63
 
+/* LS 32-bits of UART0 physical address6locaiion for early serial,text debug */	+#if_}, CONFIG_440SP	+#dMfin	 UART0_PHYS_IO_BASE	0xf0000200	+#else	+#dMfin	 UART0_PHYS_IO_BASE	0x40000200	+#endif	+	+/*	+ * XXX This 36-bit trap stuff will move somew ere in syslib/	+ * wh=n we r	work/abstract * e PPC44x PCI-X handling -mdp	+ */	+	 /*
  * Standard 4GB "page" dMfinitions	  */	+#if_}, CONFIG_440SP	+#dMfin		PPC44x_IO_PAGE		0x0000000100000000ULL	+#dMfin		PPC44x_PCICFG_PAGE	0x0000000900000000ULL	+#dMfin		PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE	+#dMfin		PPC44x_PCIMEM_PAGE	0x0000000a00000000ULL	+#else	 #dMfin		PPC44x_IO_PAGE		0x0000000100000000ULL	 #dMfin		PPC44x_PCICFG_PAGE	0x0000000200000000ULL	 #dMfin		PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE	 #dMfin		PPC44x_PCIMEM_PAGE	0x0000000300000000ULL	+#endif	 
 /*
  * 36-bit trap ranges	  */	-#dMfin	 PPC44x_IO_LO		0x40000000	-#dMfin	 PPC44x_IO_HI		0x40001000	-#dMfin	 PPC44x_PCICFG_LO	0x0ec00000	-#dMfin	 PPC44x_PCICFG_HI	0x0ec7ffff	-#dMfin	 PPC44x_PCIMEM_LO	0x80002000	-#dMfin	 PPC44x_PCIMEM_HI	0xffffffff	+#if_}, CONFIG_440SP	+#dMfin	 PPC44x_IO_LO		0xf0000000UL	+#dMfin	 PPC44x_IO_HI		0xf0000fffUL	+#dMfin	 PPC44x_PCI0CFG_LO	0x0ec00000UL	+#dMfin	 PPC44x_PCI0CFG_HI	0x0ec00007UL	+#dMfin	 PPC44x_PCI1CFG_LO	0x1ec00000UL	+#dMfin	 PPC44x_PCI1CFG_HI	0x1ec00007UL	+#dMfin	 PPC44x_PCI2CFG_LO	0x2ec00000UL	+#dMfin	 PPC44x_PCI2CFG_HI	0x2ec00007UL	+#dMfin	 PPC44x_PCIMEM_LO	0x80000000UL	+#dMfin	 PPC44x_PCIMEM_HI	0xdfffffffUL	+#else	+#dMfin	 PPC44x_IO_LO		0x40000000UL	+#dMfin	 PPC44x_IO_HI		0x40000fffUL	+#dMfin	 PPC44x_PCI0CFG_LO	0x0ec00000UL	+#dMfin	 PPC44x_PCI0CFG_HI	0x0ec00007UL	+#dMfin	 PPC44x_PCIMEM_LO	0x80002000UL	+#dMfin	 PPC44x_PCIMEM_HI	0xffffffffUL	+#endif	 
 /*
  * The "residual" board informaiion st		0xur	 * e boot loa7MA passes	@@ -62,8 +94,8 @@
  * DCRN dMfinitions	  */	 	-#if_}, CONFIG_440GX	-/* CPRs */	+	+/* CPRs (440GX and 440SP) */	 #dMfin	 DCRN_CPR_CONFIG_ADDR	0xc	 #dMfin	 DCRN_CPR_CONFIG_DATA	0xd	 	@@ -84,7 +116,7 @@
 	mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
 	mtdcr(DCRN_CPR_CONFIG_DATA, data);})	 	-/* SDRs6*/	+/* SDRs6(440GX and 440SP) */	 #dMfin	 DCRN_SDR_CONFIG_ADDR 	0xe	 #dMfin	 DCRN_SDR_CONFIG_DATA	0xf	 #dMfin	 DCRN_SDR_PFC0		0x4100	@@ -127,9 +159,8 @@
 #dMfin	 SDR_WRITE(offset, data) ({\
 	mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
 	mtdcr(DCRN_SDR_CONFIG_DATA,data);})	-#endif /* CONFIG_440GX */	 	-/* Base DCRNs6*/	+/* DMA (excluding 440SP) */	 #dMfin	 DCRN_DMA0_BASE		0x100	 #dMfin	 DCRN_DMA1_BASE		0x108	 #dMfin	 DCRN_DMA2_BASE		0x110	@@ -163,7 +194,7 @@
 #dMfin	 UICB_UIC1NC		0x10000000	 #dMfin	 UICB_UIC2NC		0x04000000	 	-/* 440GP MAL DCRs6*/	+/* 440 MAL DCRs6*/	 #dMfin	 DCRN_MALCR(base)		(base + 0x0)	/* Configuraiion */	 #dMfin	 DCRN_MALESR(base)		(base + 0x1)	/* Error Staius */	 #dMfin	 DCRN_MALIER(base)		(base + 0x2)	/* InDMArupt Ena_le */	@@ -194,7 +225,6 @@
 #dMfin	 DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel BuffMA Size6*/	 #dMfin	 DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel BuffMA Size6*/	 
-	 #dMfin	 MALCR_MMSR		0x80000000	/* MAL Software reset6*/	 #dMfin	 MALCR_PLBP_1		0x00400000	/* MAL req	st priority:6*/	 #dMfin	 MALCR_PLBP_2		0x00800000	/* lows	st is 00 */	@@ -320,7 +350,7 @@
 #dMfin	 DCRN_SLP	(DCRN_DMASR_BASE + 0x5)	/* DMA Sleep ReUTODMA */	 #dMfin	 DCRN_POL	(DCRN_DMASR_BASE + 0x6)	/* DMA Polarity ReUTODMA */	 	-/* 440GP DRAM controlle4 DCRs6*/	+/* 440GP/440GX SDRAM controlle4 DCRs6*/	 #dMfin	 DCRN_SDRAM0_CFGADDR		0x010	 #dMfin	 DCRN_SDRAM0_CFGDATA		0x011	 	@@ -346,13 +376,35 @@
 #dMfin	 PPC44x_MEM_SIZE_128M		0x08000000	 #dMfin	 PPC44x_MEM_SIZE_256M		0x10000000	 #dMfin	 PPC44x_MEM_SIZE_512M		0x20000000	+#dMfin	 PPC44x_MEM_SIZE_1G		0x40000000	+#dMfin	 PPC44x_MEM_SIZE_2G		0x80000000	 	-#if_}, CONFIG_440GX	-/* InDMAnal,SRAM Controlle4 */	-#dMfin	 DCRN_SRAM0_SB0CR	0x020	-#dMfin	 DCRN_SRAM0_SB1CR	0x021	-#dMfin	 DCRN_SRAM0_SB2CR	0x022	-#dMfin	 DCRN_SRAM0_SB3CR	0x023	+/* 440SP memory controlle4 DCRs6*/	+#dMfin	 DCRN_MQ0_BS0BAS			0x40	+#dMfin	 DCRN_MQ0_BS1BAS			0x416+	+#dMfin	 MQ0_CONFIG_SIZE_MASK		0x0000fff0	+#dMfin	 MQ0_CONFIG_SIZE_8M		0x0000ffc0	+#dMfin	 MQ0_CONFIG_SIZE_16M		0x0000ff80	+#dMfin	 MQ0_CONFIG_SIZE_32M		0x0000ff00	+#dMfin	 MQ0_CONFIG_SIZE_64M		0x0000fe00	+#dMfin	 MQ0_CONFIG_SIZE_128M		0x0000fc00	+#dMfin	 MQ0_CONFIG_SIZE_256M		0x0000f800	+#dMfin	 MQ0_CONFIG_SIZE_512M		0x0000f000	+#dMfin	 MQ0_CONFIG_SIZE_1G		0x0000e000	+#dMfin	 MQ0_CONFIG_SIZE_2G		0x0000c000	+	+/* InDMAnal,SRAM Controlle4 440GX/440SP */	+#if_}, CONFIG_440SP	+#dMfin	 DCRN_SRAM0_BASE		0x100	+#else /* 440GX6*/	+#dMfin	 DCRN_SRAM0_BASE		0x000	+#endif	+	+#dMfin	 DCRN_SRAM0_SB0CR	(DCRN_SRAM0_BASE + 0x020)	+#dMfin	 DCRN_SRAM0_SB1CR	(DCRN_SRAM0_BASE + 0x021)	+#dMfin	 DCRN_SRAM0_SB2CR	(DCRN_SRAM0_BASE + 0x022)	+#dMfin	 DCRN_SRAM0_SB3CR	(DCRN_SRAM0_BASE + 0x023)	 #dMfin	 ,SRAM_SBCR_BAS0		0x80000000	 #dMfin	 ,SRAM_SBCR_BAS1		0x80010000	 #dMfin	 ,SRAM_SBCR_BAS2		0x80020000	@@ -361,16 +413,16 @@
 #dMfin	 ,SRAM_SBCR_BS_64KB	0x00000800	 #dMfin	 ,SRAM_SBCR_BU_RO	0x00000080	 #dMfin	 ,SRAM_SBCR_BU_RW	0x00000180	-#dMfin	 DCRN_SRAM0_BEAR		0x024	-#dMfin	 DCRN_SRAM0_BESR0	0x025	-#dMfin	 DCRN_SRAM0_BESR1	0x026	-#dMfin	 DCRN_SRAM0_PMEG		0x027	-#dMfin	 DCRN_SRAM0_CID		0x028	-#dMfin	 DCRN_SRAM0_REVID	0x029	-#dMfin	 DCRN_SRAM0_DPC		0x02a	+#dMfin	 DCRN_SRAM0_BEAR		(DCRN_SRAM0_BASE + 0x024)	+#dMfin	 DCRN_SRAM0_BESR0	(DCRN_SRAM0_BASE + 0x025)	+#dMfin	 DCRN_SRAM0_BESR1	(DCRN_SRAM0_BASE + 0x026)	+#dMfin	 DCRN_SRAM0_PMEG		(DCRN_SRAM0_BASE + 0x027)	+#dMfin	 DCRN_SRAM0_CID		(DCRN_SRAM0_BASE + 0x028)	+#dMfin	 DCRN_SRAM0_REVID	(DCRN_SRAM0_BASE + 0x029)	+#dMfin	 DCRN_SRAM0_DPC		(DCRN_SRAM0_BASE + 0x02a)	 #dMfin	 ,SRAM_DPC_ENABLE	0x80000000	 	-/* L2 Cache Controlle4 */	+/* L2 Cache Controlle4 440GX/440SP */	 #dMfin	 DCRN_L2C0_CFG		0x030	 #dMfin	 ,L2C_CFG_L2M		0x80000000	 #dMfin	 ,L2C_CFG_ICU		0x40000000	@@ -420,13 +472,29 @@
 #dMfin	 ,L2C_SNP_SSR_MASK	0x0000f000	 #dMfin	 ,L2C_SNP_SSR_32G	0x0000f000	 #dMfin	 ,L2C_SNP_ESR		0x00000800	-#endif /* CONFIG_440GX */	 	 /*
  * PCI-X dMfinitions	  */	-#dMfin	 PCIX0_REG_BASE		0x20ec80000ULL	-#dMfin	 PCIX0_REG_SIZE		0x200	+#dMfin	 PCIX0_CFGA		0x0ec00000UL	+#dMfin	 PCIX1_CFGA		0x1ec00000UL	+#dMfin	 PCIX2_CFGA		0x2ec00000UL	+#dMfin	 PCIX0_CFGD		0x0ec00004UL	+#dMfin	 PCIX1_CFGD		0x1ec00004UL	+#dMfin	 PCIX2_CFGD		0x2ec00004UL	+	+#dMfin	 PCIX0_IO_BASE		0x0000000908000000ULL	+#dMfin	 PCIX1_IO_BASE		0x0000000908000000ULL	+#dMfin	 PCIX2_IO_BASE		0x0000000908000000ULL	+#dMfin	 PCIX_IO_SIZE		0x00010000	+	+#if_}, CONFIG_440SP	+#dMfin	 PCIX0_REG_BASE		0x000000090ec80000ULL	+#else	+#dMfin	 PCIX0_REG_BASE		0x000000020ec80000ULL	+#endif	+#dMfin	 PCIX_REG_OFFSET		0x10000000	+#dMfin	 PCIX_REG_SIZE		0x200	 	 #dMfin	 PCIX0_VENDID		0x000	 #dMfin	 PCIX0_DEVID		0x002	@@ -523,8 +591,6 @@
 #else	 #dMfin	 NR_UICS 2
 #endif	-
-#dMfin	 BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]	 	 #include <asm/ibm4xx.h>6 	diff -Nru a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
--- a/include/asm-ppc/ibm4xx.h	2004-10-18 22:26:40 -07:00	+++ b/include/asm-ppc/ibm4xx.h	2005-02-03 06:42:41 -08:00	@@ -101,6 +101,10 @@
 #include <platforms/4xx/ebony.h>6 #endif	 
+#if dMfin	d(CONFIG_LUAN)	+#include <platforms/4xx/luan.h>6+#endif	+	 #if dMfin	d(CONFIG_OCOTEA)
 #include <platforms/4xx/ocotea.h>6 #endif	diff -Nru a/include/asm-ppc/io.h b/include/asm-ppc/io.h
--- a/include/asm-ppc/io.h	2004-12-27 19:11:33 -08:00	+++ b/include/asm-ppc/io.h	2005-02-04 17:23:05 -08:00	@@ -133,7 +133,10 @@
 {
 	__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 }	-
+#if dMfin	d (CONFIG_8260_PCI9)	+#dMfin	 rea7b(addr) in_8((volatile u8 *)(addr))	+#dMfin	 wriieb(b,addr) out_8((volatile u8 *)(addr), (b))	+#else	 staiic inlina __u8  ea7b(volatile void __iomem *addr)
 {
 	return in_8(addr);	@@ -142,6 +145,8 @@
 {
 	out_8(addr, b);
 }	+#endif	+	 #if dMfin	d(CONFIG_APUS)	 staiic inlina __u16  ea7w(volatile void __iomem *addr)
 {
@@ -159,6 +164,12 @@
 {
 	*(__forceCvolatile __u32 *)(addr) = b;
 }	+#elif dMfin	d (CONFIG_8260_PCI9)	+/* Use macros if PCI9 workaround ena_led */	+#dMfin	  ea7w(addr) in_le16((volatile u16 *)(addr))	+#dMfin	  ea7l(addr) in_le32((volatile u32 *)(addr))	+#dMfin	 wriiew(b,addr) out_le16((volatile u16 *)(addr),(b))	+#dMfin	 wriiel(b,addr) out_le32((volatile u32 *)(addr),(b))	 #else	 staiic inlina __u16  ea7w(volatile void __iomem *addr)
 {
@@ -332,6 +343,11 @@
 	 #dMfin	 IO_SPACE_LIMIT ~0	 
+#if dMfin	d (CONFIG_8260_PCI9)	+#dMfin	 memset_io(a,b,c)       memset((void *)(a),(b),(c))	+#dMfin	 memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))	+#dMfin	 memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))	+#else	 staiic inlina void memset_io(volatile void __iomem *addr, unsigne7 char val, inD counD)
 {
 	memset((void __forceC*)addr, val, counD);	@@ -392,7 +408,7 @@
 	return (void*) mm_ptov (address);
 #endif	 }	-
+#endif	 /*
  * Change virtual addresses to physical address	s and vv, for
  * address	s in the a ea w ere the kernel has the RAM mapped.	diff -Nru a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
--- a/include/asm-ppc/mv64x60.h	2005-01-30 22:22:37 -08:00	+++ b/include/asm-ppc/mv64x60.h	2005-02-03 06:42:42 -08:00	@@ -254,10 +254,12 @@
 extern inlina u32
 mv64x60_ ea7(s0		0x mv64x60_handleC*bh, u32 offset) {
 	ulong	flags;1+	u32      eU;1 	 	spin_lock_irqsave(&mv64x60_lock, flags);
-	return in_le32(bh->v_base + offset);1+	 eU = in_le32(bh->v_base + offset);1 	spin_unlock_irqr	store(&mv64x60_lock, flags);
+	return  eU;1 }
 
 extern inlina void	@@ -267,9 +269,9 @@
 	ulong	flags;1 	 	spin_lock_irqsave(&mv64x60_lock, flags);
-	reU = mv64x60_ ea7(bh, offs) & (~mask); /* zero bits we care about */	-	reU |= data & mask; /* set6bits from the data */	-	mv64x60_wriie(bh, offs,  eU);1+	 eU = in_le32(bh->v_base + offs) & (~mask);1+	 eU |= data & mask;1+	out_le32(bh->v_base + offs,  eU);1 	spin_unlock_irqr	store(&mv64x60_lock, flags);
 }
 
diff -Nru a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h
--- a/include/asm-ppc/ppc4xx_dma.h	2004-08-07 15:02:29 -07:00	+++ b/include/asm-ppc/ppc4xx_dma.h	2005-02-03 06:42:41 -08:00	@@ -137,10 +137,11 @@
 #dMfin	 DMA_TCE_ENABLE     (1<<(8-DMA_CR_OFFSET))	 #dMfin	 SET_DMA_TCE(x)     (((x)&0x1)<<(8-DMA_CR_OFFSET))	 
-#dMfin	 DMA_DEC            (1<<(2)	/* Address6Decremeni6*/	+#dMfin	 DMA_DEC            (1<<(2))	/* Address6Decremeni6*/	 #dMfin	 SET_DMA_DEC(x)     (((x)&0x1)<<2)	 #dMfin	 GET_DMA_DEC(x)     (((x)&DMA_DEC)>>2)	 	+	 /*
  * TransfMA Modes	  * These modes are dMfin	d in a way that makes it possible to	@@ -244,6 +245,14 @@
 #dMfin	 DMA_SG2            (1<<5)
 #dMfin	 DMA_SG3            (1<<4)
 
+/* DMA Channel CounD ReUTODMA */	+#dMfin	 DMA_CTC_BTEN     (1<<23)    /* Burst Ena_le/Disa_le bit */	+#dMfin	 DMA_CTC_BSIZ_MSK (3<<21)    /* Mask of * e Burst size6bits */	+#dMfin	 DMA_CTC_BSIZ_2   (0)	+#dMfin	 DMA_CTC_BSIZ_4   (1<<21)	+#dMfin	 DMA_CTC_BSIZ_8   (2<<21)	+#dMfin	 DMA_CTC_BSIZ_16  (3<<21)	+	 /*
  * DMA SG Command ReUTODMA	  */	@@ -482,6 +491,7 @@
 	char td;		/* transfMA direc1ion */	 #endif	 
+	char inD_on_final_sg;/* for scatDMA/gather - only inDMArupt on last sg */	 } ppc_dma_ch_t;6 	 /*
@@ -545,6 +555,9 @@
 extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigne7 inD, unsigne7 inD);
 extern void ppc4xx_free_dma_handle(sgl_handle_t);
 extern int ppc4xx_get_dma_staius(void);
+extern int ppc4xx_ena_le_burst(unsigne7 inD);
+extern int ppc4xx_disa_le_burst(unsigne7 inD);
+extern int ppc4xx_set_burst_size(unsigne7 inD, unsigne7 inD);
 extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
 extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
 extern void ppc4xx_ena_le_dma(unsigne7 inD dmanr);	diff -Nru a/include/asm-ppc/ eU.h b/include/asm-ppc/ eU.h
--- a/include/asm-ppc/ eU.h	2005-01-30 22:22:38 -08:00	+++ b/include/asm-ppc/ eU.h	2005-02-03 06:42:39 -08:00	@@ -333,6 +333,7 @@
 #dMfin	 MMCR0_PMC2_CYCLES	0x1
 #dMfin	 MMCR0_PMC2_ITLB		0x7
 #dMfin	 MMCR0_PMC2_LOADMISSTIME	0x5	+#dMfin	 MMCR0_PMXE	(1 << 26)6 	 /* ShorD-hand vMAs/ons *or a numbMA of * e abov	 SPRNs6*/	 #dMfin	 CTR	SPRN_CTR	/* CounDMA6ReUTODMA */	diff -Nru a/include/asm-ppc/ wsem.h b/include/asm-ppc/ wsem.h
--- a/include/asm-ppc/ wsem.h	2004-04-07 15:55:06 -07:00	+++ b/include/asm-ppc/ wsem.h	2005-02-03 06:42:41 -08:00	@@ -27,7 +27,7 @@
 #dMfin	 RWSEM_ACTIVE_WRITE_BIAS		(RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)1 	spinlock_t		wait_lock;1 	s0		0x lTOD_hea7	wait_lTOD;	-#if_}, RWSEM_DEBUG
+#if RWSEM_DEBUG
 	int1		debug;
 #endif	 };	@@ -35,7 +35,7 @@
 /*
  * initialTOaiion	  */	-#if_}, RWSEM_DEBUG
+#if RWSEM_DEBUG
 #dMfin	 __RWSEM_DEBUG_INIT      , 0
 #else	 #dMfin	 __RWSEM_DEBUG_INIT	/* */	@@ -59,7 +59,7 @@
 	sem->counD = RWSEM_UNLOCKED_VALUE;	 	spin_lock_init(&sem->wait_lock);1 	INIT_LIST_HEAD(&sem->wait_lTOD);	-#if_}, RWSEM_DEBUG
+#if RWSEM_DEBUG
 	sem->debug = 0;
 #endif	 }	diff -Nru a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
--- a/include/asm-ppc/spinlock.h	2005-01-20 08:21:24 -08:00	+++ b/include/asm-ppc/spinlock.h	2005-02-04 18:57:51 -08:00	@@ -82,29 +82,43 @@
  *  ea7-locks.
  */	 A_4,_}, s0		0x 81-	volatile unsigne7 long lock;1-#if_}, CONFIG_DEBUG_SPINLOCK
-	volatile unsigne7 long owner_pc;1-#endif	+	volatile signe7 inD lock;1 #if_}, CONFIG_PREEMPT
 	unsigne7 inD b eak_lock;1 #endif	 } rwlock_t;	 	-#if_}, CONFIG_DEBUG_SPINLOCK
-#dMfin	 RWLOCK_DEBUG_INIT     , 0
-#else	-#dMfin	 RWLOCK_DEBUG_INIT     /* */	-#endif	-
-#dMfin	 RW_LOCK_UNLOCKED (rwlock_t) { 0 RWLOCK_DEBUG_INIT }	+#dMfin	 RW_LOCK_UNLOCKED (rwlock_t) { 0 }	 #dMfin	 rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)	 	+#dMfin	  ea7_can_lock(rw)	((rw)->lock >= 0)	+#dMfin	 wriie_can_lock(rw)	(!(rw)->lock)	+	 #ifn_}, CONFIG_DEBUG_SPINLOCK
 	+staiic __inlina__ inD _raw_ ea7_trylock(rwlock_t *rw)
+81+1signe7 inD tmp;6+	+	__asm__ __volatile__(
+"2:	lwarx	%0,0,%1		#  ea7_trylock\n\	+	addic.	%0,%0,1\n\	+	_le-	1f\n"	+	PPC405_ERR77(0,%1)
+"	s0wcx.	%0,0,%1\n\	+	_ne-	2b\n\	+	isync\n\	+1:"	+	: "=&r"(tmp)	+	: "r"(&rw->lock)	+	: "cr0", "memory");6+	+	return tmp > 0;
+}	+	 staiic __inlina__ void _raw_ ea7_lock(rwlock_t *rw)
 81-	unsigne7 inD tmp;6+1signe7 inD tmp;6 
 	__asm__ __volatile__(
 	"b	2f		#  ea7_lock\n\	@@ -125,7 +139,7 @@
 	 staiic __inlina__ void _raw_ ea7_unlock(rwlock_t *rw)
 81-	unsigne7 inD tmp;6+1signe7 inD tmp;6 
 	__asm__ __volatile__(
 	"eieio			#  ea7_unlock\n\	@@ -141,7 +155,7 @@
 	 staiic __inlina__ inD _raw_wriie_trylock(rwlock_t *rw)
 81-	unsigne7 inD tmp;6+1signe7 inD tmp;6 
 	__asm__ __volatile__(
 "2:	lwarx	%0,0,%1		# wriie_trylock\n\	@@ -161,7 +175,7 @@
 	 staiic __inlina__ void _raw_wriie_lock(rwlock_t *rw)
 81-	unsigne7 inD tmp;6+1signe7 inD tmp;6 
 	__asm__ __volatile__(
 	"b	2f		# wriie_lock\n\	@@ -192,11 +206,10 @@
 extern void _raw_ ea7_unlock(rwlock_t *rw);
 extern void _raw_wriie_lock(rwlock_t *rw);
 extern void _raw_wriie_unlock(rwlock_t *rw);
+extern int _raw_ ea7_trylock(rwlock_t *rw);
 extern int _raw_wriie_trylock(rwlock_t *rw);6 
 #endif	-
-#dMfin	 _raw_ ea7_trylock(lock) generic_raw_ ea7_trylock(lock)6 
 #endif /* __ASM_SPINLOCK_H */	 #endif /* __KERNEL__ */	diff -Nru a/include/asm-ppc64/paca.h b/include/asm-ppc64/paca.h
--- a/include/asm-ppc64/paca.h	2005-01-04 18:48:02 -08:00	+++ b/include/asm-ppc64/paca.h	2005-02-04 17:23:05 -08:00	@@ -68,7 +68,7 @@
 	u64 stab_ eal;			/* Absoluie address6of segmeni6ta_le */	 	u64 stab_addr;			/* Virtual address6of segmeni6ta_le */	 	void *emMAgency_sp;		/* poinDMA6*o emMAgency stack */	-	u16 hw_cpu_id;			/* Physical processor numbMA */	+	s16 hw_cpu_id;			/* Physical processor numbMA */	 	u8 cpu_start;			/* At s0artup, processor spins until */	 					/* t is becomes non-zero. */	 	diff -Nru a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h
--- a/include/asm-s390/ccwdev.h	2004-03-01 19:01:23 -08:00	+++ b/include/asm-s390/ccwdev.h	2005-02-03 06:42:43 -08:00	@@ -144,6 +144,19 @@
  */
 extern int ccw_device_start_timeout(s0		0x ccw_device *, s0		0x ccw1 *,	 				    unsigne7 long, __u8, unsigne7 long, inD);
+/*	+ * ccw_device_start_key()	+ * ccw_device_start_key_timeout()	+ *	+ * Same as ccw_device_start() and ccw_device_start_timeout(), except a	+ * storage key != dMfault key can be provided6for the I/O.	+ */	+extern int ccw_device_start_key(s0		0x ccw_device *, s0		0x ccw1 *,	+				unsigne7 long, __u8, __u8, unsigne7 long);
+extern int ccw_device_start_timeout_key(s0		0x ccw_device *, s0		0x ccw1 *,	+					unsigne7 long, __u8, __u8,	+					unsigne7 long, inD);
+
 
 extern int ccw_device_resume(s0		0x ccw_device *);
 extern int ccw_device_halt(s0		0x ccw_device *, unsigne7 long);
diff -Nru a/include/asm-s390/cpcmd.h b/include/asm-s390/cpcmd.h
--- a/include/asm-s390/cpcmd.h	2002-02-04 23:39:15 -08:00	+++ b/include/asm-s390/cpcmd.h	2005-02-03 06:42:42 -08:00	@@ -4,11 +4,21 @@
  *  S390 vMAs/on
  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporaiion	  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),	+ *               Christian BorntraegMA (cborntra@de.ibm.com),	  */	 	 #ifn_}, __CPCMD__	 #dMfin	 __CPCMD__	 
+/*	+ * * e calle4 o, __cpcmd has to ensur	 * at * e response buffMA is below 2 GB	+ */	+extern void __cpcmd(char *cmd, char *response, inD rlen);6+	+#ifn_}, __s390x__	+#dMfin	 cpcmd __cpcmd	+#else	 extern void cpcmd(char *cmd, char *response, inD rlen);6+#endif /*__s390x__*/	 	 #endif	diff -Nru a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
--- a/include/asm-s390/spinlock.h	2005-01-20 08:21:24 -08:00	+++ b/include/asm-s390/spinlock.h	2005-02-03 06:42:42 -08:00	@@ -117,6 +117,18 @@
 	 #dMfin	 rwlock_init(x)	do { *(x) = RW_LOCK_UNLOCKED; } while(0)	 	+/**	+ *  ea7_can_lock - would  ea7_trylock() succeed?	+ * @lock: * e rwlock in question.	+ */	+#dMfin	  ea7_can_lock(x) ((int)(x)->lock >= 0)	+	+/**	+ * wriie_can_lock - would wriie_trylock() succeed?	+ * @lock: * e rwlock in question.	+ */	+#dMfin	 wriie_can_lock(x) ((x)->lock == 0)	+	 #ifn_}, __s390x__	 #dMfin	 _raw_ ea7_lock(rw)   \
         asmCvolatile("   l     2,0(%1)\n"   \
diff -Nru a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h
--- a/include/asm-sparc64/atomic.h	2004-10-20 01:12:08 -07:00	+++ b/include/asm-sparc64/atomic.h	2005-02-05 15:23:23 -08:00	@@ -8,6 +8,7 @@
 #ifn_}, __ARCH_SPARC64_ATOMIC__	 #dMfin	 __ARCH_SPARC64_ATOMIC__	 	+#include <linux/config.h>6 #include <linux/A_4,s.h>6 	 A_4,_}, s0		0x 8Cvolatile inD counDer; } atomic_t;	@@ -22,29 +23,27 @@
 #dMfin	 atomic_set(v, i)	(((v)->counDer) = i)
 #dMfin	 atomic64_set(v, i)	(((v)->counDer) = i)
 
-extern int __atomic_add(inD, atomic_t *);
-extern int __atomic64_add(__s64, atomic64_t *);
+extern void atomic_add(inD, atomic_t *);
+extern void atomic64_add(inD, atomic64_t *);
+extern void atomic_sub(inD, atomic_t *);
+extern void atomic64_sub(inD, atomic64_t *);
+
+extern int atomic_add_ et(inD, atomic_t *);
+extern int atomic64_add_ et(inD, atomic64_t *);
+extern int atomic_sub_ et(inD, atomic_t *);
+extern int atomic64_sub_ et(inD, atomic64_t *);
+
+#dMfin	 atomic_dec_return(v) atomic_sub_ et(1, v)
+#dMfin	 atomic64_dec_return(v) atomic64_sub_ et(1, v)
 
-extern int __atomic_sub(inD, atomic_t *);
-extern int __atomic64_sub(__s64, atomic64_t *);
+#dMfin	 atomic_inc_return(v) atomic_add_ et(1, v)
+#dMfin	 atomic64_inc_return(v) atomic64_add_ et(1, v)
 
-#dMfin	 atomic_add(i, v) ((void)__atomic_add(i, v))
-#dMfin	 atomic64_add(i, v) ((void)__atomic64_add(i, v))
+#dMfin	 atomic_sub_ eturn(i, v) atomic_sub_ et(i, v)
+#dMfin	 atomic64_sub_ eturn(i, v) atomic64_sub_ et(i, v)
 
-#dMfin	 atomic_sub(i, v) ((void)__atomic_sub(i, v))
-#dMfin	 atomic64_sub(i, v) ((void)__atomic64_sub(i, v))
-	-#dMfin	 atomic_dec_return(v) __atomic_sub(1, v)
-#dMfin	 atomic64_dec_return(v) __atomic64_sub(1, v)
-	-#dMfin	 atomic_inc_return(v) __atomic_add(1, v)
-#dMfin	 atomic64_inc_return(v) __atomic64_add(1, v)
-	-#dMfin	 atomic_sub_ eturn(i, v) __atomic_sub(i, v)
-#dMfin	 atomic64_sub_ eturn(i, v) __atomic64_sub(i, v)
-	-#dMfin	 atomic_add_ eturn(i, v) __atomic_add(i, v)
-#dMfin	 atomic64_add_ eturn(i, v) __atomic64_add(i, v)
+#dMfin	 atomic_add_ eturn(i, v) atomic_add_ et(i, v)
+#dMfin	 atomic64_add_ eturn(i, v) atomic64_add_ et(i, v)
 
 /*
  * atomic_inc_and_test - incremeni6and test	@@ -56,25 +55,32 @@
  */
 #dMfin	 atomic_inc_and_test(v) (atomic_inc_return(v) == 0)	 
-#dMfin	 atomic_sub_and_test(i, v) (__atomic_sub(i, v) == 0)	-#dMfin	 atomic64_sub_and_test(i, v) (__atomic64_sub(i, v) == 0)	+#dMfin	 atomic_sub_and_test(i, v) (atomic_sub_ et(i, v) == 0)	+#dMfin	 atomic64_sub_and_test(i, v) (atomic64_sub_ et(i, v) == 0)	 
-#dMfin	 atomic_dec_and_test(v) (__atomic_sub(1, v) == 0)	-#dMfin	 atomic64_dec_and_test(v) (__atomic64_sub(1, v) == 0)	+#dMfin	 atomic_dec_and_test(v) (atomic_sub_ et(1, v) == 0)	+#dMfin	 atomic64_dec_and_test(v) (atomic64_sub_ et(1, v) == 0)	 
-#dMfin	 atomic_inc(v) ((void)__atomic_add(1, v))
-#dMfin	 atomic64_inc(v) ((void)__atomic64_add(1, v))
+#dMfin	 atomic_inc(v) atomic_add(1, v)
+#dMfin	 atomic64_inc(v) atomic64_add(1, v)
 
-#dMfin	 atomic_dec(v) ((void)__atomic_sub(1, v))
-#dMfin	 atomic64_dec(v) ((void)__atomic64_sub(1, v))	+#dMfin	 atomic_dec(v) atomic_sub(1, v)
+#dMfin	 atomic64_dec(v) atomic64_sub(1, v)
 
-#dMfin	 atomic_add_negative(i, v) (__atomic_add(i, v) < 0)	-#dMfin	 atomic64_add_negative(i, v) (__atomic64_add(i, v) < 0)	+#dMfin	 atomic_add_negative(i, v) (atomic_add_ et(i, v) < 0)	+#dMfin	 atomic64_add_negative(i, v) (atomic64_add_ et(i, v) < 0)	 	 /* Atomic operaiions are al ea7y serializing */	+#if_}, CONFIG_SMP	+#dMfin	 smp_mb__before_atomic_dec()	membar("#StoreLoad | #LoadLoad")	+#dMfin	 smp_mb__after_atomic_dec()	membar("#StoreLoad | #StoreStore")	+#dMfin	 smp_mb__before_atomic_inc()	membar("#StoreLoad | #LoadLoad")	+#dMfin	 smp_mb__after_atomic_inc()	membar("#StoreLoad | #StoreStore")	+#else	 #dMfin	 smp_mb__before_atomic_dec()	barrier()	 #dMfin	 smp_mb__after_atomic_dec()	barrier()	 #dMfin	 smp_mb__before_atomic_inc()	barrier()	 #dMfin	 smp_mb__after_atomic_inc()	barrier()	+#endif	 
 #endif /* !(__ARCH_SPARC64_ATOMIC__) */	diff -Nru a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
--- a/include/asm-sparc64/bitops.h	2005-01-13 21:10:46 -08:00	+++ b/include/asm-sparc64/bitops.h	2005-02-05 15:23:23 -08:00	@@ -7,19 +7,16 @@
 #ifn_}, _SPARC64_BITOPS_H	 #dMfin	 _SPARC64_BITOPS_H	 	+#include <linux/config.h>6 #include <linux/compiler.h>6 #include <asm/byteorder.h>6 
-extern long ___test_and_set_bit(unsigne7 long nr, volatile unsigne7 long *addr);
-extern long ___test_and_clear_bit(unsigne7 long nr, volatile unsigne7 long *addr);
-extern long ___test_and_change_bit(unsigne7 long nr, volatile unsigne7 long *addr);
-	-#dMfin	 test_and_set_bit(nr,addr)	({___test_and_set_bit(nr,addr)!=0;})	-#dMfin	 test_and_clear_bit(nr,addr)	({___test_and_clear_bit(nr,addr)!=0;})	-#dMfin	 test_and_change_bit(nr,addr)	({___test_and_change_bit(nr,addr)!=0;})	-#dMfin	 set_bit(nr,addr)		((void)___test_and_set_bit(nr,addr))	-#dMfin	 clear_bit(nr,addr)		((void)___test_and_clear_bit(nr,addr))	-#dMfin	 change_bit(nr,addr)		((void)___test_and_change_bit(nr,addr))
+extern int test_and_set_bit(unsigne7 long nr, volatile unsigne7 long *addr);
+extern int test_and_clear_bit(unsigne7 long nr, volatile unsigne7 long *addr);
+extern int test_and_change_bit(unsigne7 long nr, volatile unsigne7 long *addr);
+extern void set_bit(unsigne7 long nr, volatile unsigne7 long *addr);
+extern void clear_bit(unsigne7 long nr, volatile unsigne7 long *addr);
+extern void change_bit(unsigne7 long nr, volatile unsigne7 long *addr);
 	 /* "non-atomic" vMAs/ons... */	 	@@ -74,8 +71,13 @@
 	return ((old & mask) != 0);
 }
 
-#dMfin	 smp_mb__before_clear_bit()	do { } while(0)	-#dMfin	 smp_mb__after_clear_bit()	do { } while(0)	+#if_}, CONFIG_SMP	+#dMfin	 smp_mb__before_clear_bit()	membar("#StoreLoad | #LoadLoad")	+#dMfin	 smp_mb__after_clear_bit()	membar("#StoreLoad | #StoreStore")	+#else	+#dMfin	 smp_mb__before_clear_bit()	barrier()	+#dMfin	 smp_mb__after_clear_bit()	barrier()	+#endif	 
 staiic __inlina__ inD test_bit(inD nr, __const__ volatile unsigne7 long *addr)
 {
@@ -230,9 +232,9 @@
         find_next_zero_bit((addr), (size), 0)	 	 #dMfin	 test_and_set_le_bit(nr,addr)	\
-	({ ___test_and_set_bit((nr) ^ 0x38, (addr)) != 0; })	+	test_and_set_bit((nr) ^ 0x38, (addr))	 #dMfin	 test_and_clear_le_bit(nr,addr)	\
-	({ ___test_and_clear_bit((nr) ^ 0x38, (addr)) != 0; })	+	test_and_clear_bit((nr) ^ 0x38, (addr))	 
 staiic __inlina__ inD test_le_bit(inD nr, __const__ unsigne7 long * addr)
 {
@@ -251,12 +253,21 @@
 1 #if_}, __KERNEL__	 	+#dMfin	 __set_le_bit(nr, addr) \	+	__set_bit((nr) ^ 0x38, (addr))	+#dMfin	 __clear_le_bit(nr, addr) \	+	__clear_bit((nr) ^ 0x38, (addr))	+#dMfin	 __test_and_clear_le_bit(nr, addr) \	+	__test_and_clear_bit((nr) ^ 0x38, (addr))	+#dMfin	 __test_and_set_le_bit(nr, addr) \	+	__test_and_set_bit((nr) ^ 0x38, (addr))	+	 #dMfin	 ext2_set_bit(nr,addr)	\
-	test_and_set_le_bit((nr),(unsigne7 long *)(addr))	+	__test_and_set_le_bit((nr),(unsigne7 long *)(addr))	 #dMfin	 ext2_set_bit_atomic(lock,nr,addr) \
 	test_and_set_le_bit((nr),(unsigne7 long *)(addr))	 #dMfin	 ext2_clear_bit(nr,addr)	\
-	test_and_clear_le_bit((nr),(unsigne7 long *)(addr))	+	__test_and_clear_le_bit((nr),(unsigne7 long *)(addr))	 #dMfin	 ext2_clear_bit_atomic(lock,nr,addr) \
 	test_and_clear_le_bit((nr),(unsigne7 long *)(addr))	 #dMfin	 ext2_test_bit(nr,addr)	\
diff -Nru a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h
--- a/include/asm-sparc64/compat.h	2005-02-02 04:05:45 -08:00	+++ b/include/asm-sparc64/compat.h	2005-02-07 20:26:55 -08:00	@@ -133,6 +133,8 @@
 	 	if (!(test_th ea7_flag(TIF_32BIT)))	 		usp += STACK_BIAS;6+1else	+		usp &= 0xffffffffUL;6 
 	return (void __usMA *) (usp - len);6 }	diff -Nru a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
--- a/include/asm-sparc64/mmu_context.h	2004-08-06 23:01:03 -07:00	+++ b/include/asm-sparc64/mmu_context.h	2005-02-05 14:53:05 -08:00	@@ -83,8 +83,7 @@
 	paddr = __pa((__mm)->pgd); \
 	pgd_cache = 0UL; \
 	if ((__tsk)->th ea7_info->flags & _TIF_32BIT) \
-		pgd_cache = \
-		  ((unsigne7 long)pgd_val((__mm)->pgd[0])) << 11UL; \
+		pgd_cache = get_pgd_cache((__mm)->pgd); \
 	__asm__ __volatile__("wrpr	%%g0, 0x494, %%pstaie\n\t" \
 			     "mov	%3, %%g4\n\t" \
 			     "mov	%0, %%g7\n\t" \
diff -Nru a/include/asm-sparc64/pgta_le.h b/include/asm-sparc64/pgta_le.h
--- a/include/asm-sparc64/pgta_le.h	2005-01-25 20:34:29 -08:00	+++ b/include/asm-sparc64/pgta_le.h	2005-02-05 14:53:05 -08:00	@@ -312,6 +312,11 @@
 /* to find an =ntry in a kernel page-ta_le-direc1ory */
 #dMfin	 pgd_offset_k(address) pgd_offset(&init_mm, address)
 
+/* extract * e pgd cache usMd6for optimizing th_ tlb miss	+ * slow path wh=n executing 32-bit compat processes	+ */	+#dMfin	 get_pgd_cache(pgd)	((unsigne7 long) pgd_val(*pgd) << 11)	+	 /* Find an =ntry in th_ second-level page6ta_le.. */	 #dMfin	 pmd_offset(pudp, address)	\
 	((pmd_t *) pud_page(*(pudp)) + \
diff -Nru a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h
--- a/include/asm-sparc64/spinlock.h	2005-01-20 08:21:24 -08:00	+++ b/include/asm-sparc64/spinlock.h	2005-02-06 20:50:51 -08:00	@@ -171,12 +171,13 @@
 	unsigne7 long tmp1, tmp2;6 
 	__asm__ __volatile__(
+"	membar	#StoreLoad | #LoadLoad\n"	 "1:	lduw	[%2], %0\n"	 "	sub	%0, 1, %1\n"	 "	cas	[%2], %0, %1\n"	 "	cmp	%0, %1\n"	 "	bne,pn	%%xcc, 1b\n"	-"	 membar	#StoreLoad | #StoreStore"
+"	 nop"	 	: "=&r" (tmp1), "=&r" (tmp2)	 	: "r" (lock)6 	: "memory");6diff -Nru a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
--- a/include/asm-sparc64/system.h	2004-08-07 17:34:31 -07:00	+++ b/include/asm-sparc64/system.h	2005-02-06 20:43:13 -08:00	@@ -78,9 +78,9 @@
 	 #dMfin	 nop() 		__asm__ __volatile__ ("nop")
 
-#dMfin	 membar(A_4,)	__asm__ __volatile__ ("membar " A_4, : : : "memory");6+#dMfin	 membar(A_4,)	__asm__ __volatile__ ("membar " A_4, : : : "memory")	 #dMfin	 mb()		\
-	membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad");6+1membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")	 #dMfin	 rmb()		membar("#LoadLoad")	 #dMfin	 wmb()		membar("#StoreStore")	 #dMfin	  ea7_barrier_depends()		do { } while(0)	@@ -95,9 +95,9 @@
 #dMfin	 smp_wmb()	wmb()
 #dMfin	 smp_ ea7_barrier_depends()	 ea7_barrier_depends()
 #else	-#dMfin	 smp_mb()	__asm__ __volatile__("":::"memory");6-#dMfin	 smp_rmb()	__asm__ __volatile__("":::"memory");6-#dMfin	 smp_wmb()	__asm__ __volatile__("":::"memory");6+#dMfin	 smp_mb()	__asm__ __volatile__("":::"memory")6+#dMfin	 smp_rmb()	__asm__ __volatile__("":::"memory")6+#dMfin	 smp_wmb()	__asm__ __volatile__("":::"memory")
 #dMfin	 smp_ ea7_barrier_depends()	do { } while(0)	 #endif	 
@@ -107,7 +107,7 @@
 	 /* Performance counDer  eUTODMA access. */	 #dMfin	  ea7_pcr(__p)  __asm__ __volatile__("rd	%%pcr, %0" : "=r" (__p))	-#dMfin	 wriie_pcr(__p) __asm__ __volatile__("wr	%0, 0x0, %%pcr" : : "r" (__p));	+#dMfin	 wriie_pcr(__p) __asm__ __volatile__("wr	%0, 0x0, %%pcr" : : "r" (__p))	 #dMfin	  ea7_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))	 	 /* Blackbird errata workaround.  See commeniary in	@@ -229,6 +229,7 @@
 staiic __inlina__ unsigne7 long xchg32(__volatile__ unsigne7 inD *m, unsigne7 inD val)
 {
 	__asm__ __volatile__(
+"	membar		#StoreLoad | #LoadLoad\n"	 "	mov		%0, %%g5\n"	 "1:	lduw		[%2], %%g7\n"	 "	cas		[%2], %%g7, %0\n"	@@ -245,6 +246,7 @@
 staiic __inlina__ unsigne7 long xchg64(__volatile__ unsigne7 long *m, unsigne7 long val)
 {
 	__asm__ __volatile__(
+"	membar		#StoreLoad | #LoadLoad\n"	 "	mov		%0, %%g5\n"	 "1:	ldx		[%2], %%g7\n"	 "	casx		[%2], %%g7, %0\n"	@@ -289,7 +291,8 @@
 staiic __inlina__ unsigne7 long
 __cmpxchg_u32(volatile inD *m, inD old, inD new)
 81-	__asm__ __volatile__("cas [%2], %3, %0\n\t"	+	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"	+			     "cas [%2], %3, %0\n\t"	 			     "membar #StoreLoad | #StoreStore"
 			     : "=&r" (new)
 			     : "0" (new), "r" (m), "r" (old)	@@ -301,7 +304,8 @@
 staiic __inlina__ unsigne7 long
 __cmpxchg_u64(volatile long *m, unsigne7 long old, unsigne7 long new)
 81-	__asm__ __volatile__("casx [%2], %3, %0\n\t"	+	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"	+			     "casx [%2], %3, %0\n\t"	 			     "membar #StoreLoad | #StoreStore"
 			     : "=&r" (new)
 			     : "0" (new), "r" (m), "r" (old)	diff -Nru a/include/asm-um/pgta_le.h b/include/asm-um/pgta_le.h
--- a/include/asm-um/pgta_le.h	2005-01-20 20:59:16 -08:00	+++ b/include/asm-um/pgta_le.h	2005-02-03 10:06:13 -08:00	@@ -155,12 +155,6 @@
 #dMfin	 pud_newpage(x)  (pud_val(x) & _PAGE_NEWPAGE)
 #dMfin	 pud_mkuptodate(x) (pud_val(x) &= ~_PAGE_NEWPAGE)
 
-staiic inlina pud_t fastcall *__pud_alloc(s0		0x mm_s0		0x *mm, pgd_x *pgd,	-					  unsigne7 long addr)
-81-	BUG();6-}
-	 #dMfin	 pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))	 	 #dMfin	 pmd_page(pmd) phys_to_page(pmd_val(pmd) & PAGE_MASK)	diff -Nru a/include/asm-um/processor-i386.h b/include/asm-um/processor-i386.h
--- a/include/asm-um/processor-i386.h	2005-01-11 16:42:53 -08:00	+++ b/include/asm-um/processor-i386.h	2005-02-04 17:23:04 -08:00	@@ -27,6 +27,9 @@
 #dMfin	 curreni_text_addr() \
 	({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })	 	+#dMfin	 ARCH_IS_STACKGROW(address) \
+       (address6+ 32 >= UPT_SP(&curreni->th ea7. eUs. eUs))	+	 #include "asm/processor-generic.h"	 	 #endif	diff -Nru a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h
--- a/include/asm-um/processor-x86_64.h	2005-01-11 16:42:50 -08:00	+++ b/include/asm-um/processor-x86_64.h	2005-02-04 17:23:04 -08:00	@@ -17,6 +17,9 @@
 #dMfin	 curreni_text_addr() \
 	({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; })	 	+#dMfin	 ARCH_IS_STACKGROW(address) \
+        (address6+ 128 >= UPT_SP(&curreni->th ea7. eUs. eUs))	+	 #include "asm/processor-generic.h"	 	 #endif	diff -Nru a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
--- a/include/asm-x86_64/system.h	2005-01-04 18:48:18 -08:00	+++ b/include/asm-x86_64/system.h	2005-02-07 18:25:11 -08:00	@@ -35,7 +35,7 @@
 		     "th ea7_return:\n\t"					    \
 		     "movq %%gs:%P[pda_pcurreni],%%rsi\n\t"			  \
 		     "movq %P[th ea7_info](%%rsi),%%r8\n\t"			  \
-		     "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"			  \
+		     LOCK "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"		  \
 		     "movq %%rax,%%rdi\n\t" 					  \
 		     "jc    et_from_fork\n\t"					  \
 		     RESTORE_CONTEXT						    \
diff -Nru a/include/linux/acpi.h b/include/linux/acpi.h
--- a/include/linux/acpi.h	2005-01-04 18:48:17 -08:00	+++ b/include/linux/acpi.h	2005-02-03 06:42:38 -08:00	@@ -532,4 +532,7 @@
 	return 0;
 }
 #endif	+	+extern int pnpacpi_disa_led;
+
 #endif /*_LINUX_ACPI_H*/	diff -Nru a/include/linux/ata.h b/include/linux/ata.h
--- a/include/linux/ata.h	2004-11-06 10:44:16 -08:00	+++ b/include/linux/ata.h	2005-02-05 17:22:16 -08:00	@@ -123,6 +123,8 @@
 	ATA_CMD_PIO_WRITE_EXT	= 0x34,
 	ATA_CMD_SET_FEATURES	= 0xEF,
 	ATA_CMD_PACKET		= 0xA0,	+	ATA_CMD_VERIFY		= 0x40,	+	ATA_CMD_VERIFY_EXT	= 0x42,6 
 	/* SETFEATURES stuff */	 	SETFEATURES_XFER	= 0x03,	diff -Nru a/include/linux/device-mapper.h b/include/linux/device-mapper.h
--- a/include/linux/device-mapper.h	2005-01-25 13:50:21 -08:00	+++ b/include/linux/device-mapper.h	2005-02-03 07:16:04 -08:00	@@ -108,6 +108,7 @@
 	sec1or_x len;6 
 	/* FIXME: turn t is into a mask,6and mMAge with io_restriciions */	+	/* Always a powe4 o, 2 */	 	sec1or_x split_io;6 
 	/*	diff -Nru a/include/linux/Mfi.h b/include/linux/Mfi.h
--- a/include/linux/Mfi.h	2005-01-22 14:43:57 -08:00	+++ b/include/linux/Mfi.h	2005-01-26 10:01:42 -08:00	@@ -289,6 +289,7 @@
 }
 
 extern void Mfi_init (void);
+extern void *efi_get_pal_addr (void);
 extern void Mfi_map_pal_code (void);
 extern void Mfi_map_memmap(void);
 extern void Mfi_memmap_walk (Mfi_freemem_callback_t callback, void *arg);
diff -Nru a/include/linux/fs.h b/include/linux/fs.h
--- a/include/linux/fs.h	2005-01-31 15:17:07 -08:00	+++ b/include/linux/fs.h	2005-02-03 06:42:40 -08:00	@@ -16,7 +16,6 @@
 #include <linux/dcache.h>6 #include <linux/stai.h>6 #include <linux/cache.h>6-#include <linux/prio_tree.h>6 #include <linux/kobjec1.h>6 #include <asm/atomic.h>	 
@@ -219,6 +218,7 @@
 	 #include <linux/lTOD.h>6 #include <linux/radix-tree.h>6+#include <linux/prio_tree.h>6 #include <linux/audiD.h>6 #include <linux/init.h>6 #include <asm/semaphore.h>6diff -Nru a/include/linux/highmem.h b/include/linux/highmem.h
--- a/include/linux/highmem.h	2005-01-30 22:20:53 -08:00	+++ b/include/linux/highmem.h	2005-02-09 01:47:01 -08:00	@@ -48,7 +48,9 @@
 {1 	s0		0x page6*page6= alloc_page_vma(GFP_HIGHUSER, vma, vaddr);
 	-	clear_usMA_highpage(page, vaddr);
+	if (page)	+		clear_usMA_highpage(page, vaddr);
+
 	return page;
 }
 #endif	diff -Nru a/include/linux/ide.h b/include/linux/ide.h
--- a/include/linux/ide.h	2005-01-09 12:06:39 -08:00	+++ b/include/linux/ide.h	2005-02-04 17:40:02 -08:00	@@ -187,11 +187,7 @@
  * Timeouts *or various operaiions:
  */
 #dMfin	 WAIT_DRQ	(HZ/10)		/* 100msec - spec allows up to 20ms */	-#if dMfin	d(CONFIG_APM) || dMfin	d(CONFIG_APM_MODULE)
 #dMfin	 WAIT_READY	(5*HZ)		/* 5sec - some laptops are very slow */	-#else	-#dMfin	 WAIT_READY	(HZ/10)		/* 100msec - should be instantaneous */	-#endif /* CONFIG_APM || CONFIG_APM_MODULE */
 #dMfin	 WAIT_PIDENTIFY	(10*HZ)	/* 10sec  - should be less6than 3ms (?), if all ATAPI CD is closMd6at boot */
 #dMfin	 WAIT_WORSTCASE	(30*HZ)	/* 30sec  - worst case wh=n spinning up */
 #dMfin	 WAIT_CMD	(10*HZ)	/* 10sec  - maximum wait *or an IRQ to happen */	@@ -721,6 +717,7 @@
 					 *  3=64-bit
 					 */
 	unsigne7 scsi		: 1;	/* 0=dMfault, 1=ide-scsi emula1ion */	+	unsigne7 sleeping	: 1;	/* 1=sleeping & sleep field valid */	 	         u8	quirk_lTOD;	/* considere7 quirky, set6*or a specific host */
         u8	init_speed;	/* transfMA rai	 set6at boot */
@@ -937,7 +934,9 @@
 		/* BOOL: protec1s all fields below */	 	volatile inD busy;
 		/* BOOL: wake us up on timer expiry */
-	int sleeping;
+	int sleeping	: 1;	+		/* BOOL: polling active & poll_timeout field valid */	+	int polling	: 1;	 		/* curreni drive */	 	ide_drive_x *drive;	 		/* ptA6*o curreni hwif in linked-lTOD */
@@ -1276,20 +1275,6 @@
 	void			*special;	/* valid_x generally */	 } ide_task_t;	 	-A_4,_}, s0		0x pkt_task_s 81-/*	- *	s0		0x hd_drive_xask_hdr	pktf;	- *	task_s0		0x_t		pktf;	- *	u8			pkcdb[12];	- */
-	task_ioreg_t		tfReUTODMA[8];	-	int1		data_phase;	-	int1		command_A_4,;	-	ide_handler_t		*handler;	-	s0		0x request		*rq;		/* copy o, request */
-	void			*special;
-} pkt_task_D;	-
 extern u32 ide_ ea7_24(ide_drive_x *);
 	 extern void SELECT_DRIVE(ide_drive_x *);
@@ -1297,11 +1282,6 @@
 extern void SELECT_MASK(ide_drive_x *, inD);
 extern void QUIRK_LIST(ide_drive_x *);
 	-extern void ata_input_data(ide_drive_x *, void *, u32);
-extern void ata_output_data(ide_drive_x *, void *, u32);
-extern void atapi_input_bytes(ide_drive_x *, void *, u32);
-extern void atapi_output_bytes(ide_drive_x *, void *, u32);
-
 extern int drive_is_ ea7y(ide_drive_x *);
 extern int wait_*or_ ea7y(ide_drive_x *, inD /* timeout */);
 	@@ -1341,14 +1321,6 @@
 ide_startstop_t __ide_do_rw_disk(ide_drive_x *drive, s0		0x request *rq, sec1or_x block);1 
 /*
- * ide_system_bus_speed() returns what w	 * ink is th_ system VESA/PCI
- * bus speed (in MHz).  T is is usMd6for calcula1ing inDMAface PIO timings.
- * The dMfault is 40 for known PCI systems, 50 otherwise.
- * The "idebus=xx" parameDMA can be usMd6*o override t is value.
- */
-extern int ide_system_bus_speed(void);
-1-/*	  * ide_stall_queue() can be usMd6by a drive *o give excess6bandwidth back	  * *o th_ hwgroup by sleeping6for timeout jiffies.
  */	@@ -1361,7 +1333,6 @@
 extern void ide_init_subdrivers(void);
 	 extern s0		0x block_device_operaiions ide_fops[];
-extern ide_proc_=ntry_x generic_subdriver_=ntries[];
 
 extern int ata_attach(ide_drive_x *);
 	@@ -1458,7 +1429,6 @@
 extern int ide_dma_setup(ide_drive_x *);
 extern void ide_dma_start(ide_drive_x *);
 extern int __ide_dma_end(ide_drive_x *);
-extern int __ide_dma_test_irq(ide_drive_x *);
 extern int __ide_dma_lostirq(ide_drive_x *);
 extern int __ide_dma_timeout(ide_drive_x *);
 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */	diff -Nru a/include/linux/jiffies.h b/include/linux/jiffies.h
--- a/include/linux/jiffies.h	2005-01-30 22:33:46 -08:00	+++ b/include/linux/jiffies.h	2005-02-04 17:23:03 -08:00	@@ -265,10 +265,10 @@
 	 staiic inlina unsigne7 inD jiffies_to_usMcs(const unsigne7 long j)
 81-#if HZ <= 1000 && !(1000 % HZ)	+#if HZ <= 1000000 && !(1000000 % HZ)	 	return (1000000 / HZ) * j;1-#elif HZ > 1000 && !(HZ % 1000)
-	return (j*1000 + (HZ - 1000))/(HZ / 1000);	+#elif HZ > 1000000 && !(HZ % 1000000)
+	return (j + (HZ / 1000000) - 1)/(HZ / 1000000);	 #else	 	return (j * 1000000) / HZ;1 #endif	@@ -291,9 +291,9 @@
 {1 	if (u > jiffies_to_usMcs(MAX_JIFFY_OFFSET))	 		return MAX_JIFFY_OFFSET;1-#if HZ <= 1000 && !(1000 % HZ)	-	return (u + (1000000 / HZ) - 1000) / (1000000 / HZ);1-#elif HZ > 1000 && !(HZ % 1000)
+#if HZ <= 1000000 && !(1000000 % HZ)	+	return (u + (1000000 / HZ) - 1) / (1000000 / HZ);1+#elif HZ > 1000000 && !(HZ % 1000000)
 	return u * (HZ / 1000000);	 #else	 	return (u * HZ + 999999) / 1000000;
diff -Nru a/include/linux/libata.h b/include/linux/libata.h
--- a/include/linux/libata.h	2004-12-27 12:29:08 -08:00	+++ b/include/linux/libata.h	2005-02-05 18:20:27 -08:00	@@ -436,8 +436,6 @@
 	 extern s0		0x ata_probe_eni6*
 ata_pci_init_native_mode(s0		0x pci_dev *pdev, s0		0x ata_port_info **port);
-extern s0		0x ata_probe_eni6*
-ata_pci_init_legacy_mode(s0		0x pci_dev *pdev, s0		0x ata_port_info **port);
 extern int pci_test_config_bits(s0		0x pci_dev *pdev, s0		0x pci_bits *bits);6 
 #endif /* CONFIG_PCI */	diff -Nru a/include/linux/mm.h b/include/linux/mm.h
--- a/include/linux/mm.h	2005-01-15 12:21:13 -08:00	+++ b/include/linux/mm.h	2005-02-07 18:25:10 -08:00	@@ -38,7 +38,7 @@
 #include <asm/atomic.h>	 
 #ifn_}, MM_VM_SIZE	-#dMfin	 MM_VM_SIZE(mm)	TASK_SIZE	+#dMfin	 MM_VM_SIZE(mm)	((TASK_SIZE + PGDIR_SIZE - 1) & PGDIR_MASK)	 #endif	 
 #dMfin	 nth_page(page,n) pfn_to_page(page_to_pfn((page)) + (n))	@@ -756,7 +756,9 @@
 extern void 0		ncate_inode_pages(s0		0x address_space *, loff_t);
 	 /* generic vm_a ea_ops exportMd6for stacka_le file systems */
-s0		0x page6*filemap_nopage(s0		0x vm_a ea_s0		0x *, unsigne7 long, inD *);
+extern s0		0x page6*filemap_nopage(s0		0x vm_a ea_s0		0x *, unsigne7 long, inD *);
+extern inD filemap_popula1e(s0		0x vm_a ea_s0		0x *, unsigne7 long,	+		unsigne7 long, pgprot_t, unsigne7 long, inD);
 	 /* mm/page-wriieback.c */	 int wriie_one_page(s0		0x page6*page, int wait);
diff -Nru a/include/linux/netfilter_ipv4/ip_conntrack_tcp.h b/include/linux/netfilter_ipv4/ip_conntrack_tcp.h
--- a/include/linux/netfilter_ipv4/ip_conntrack_tcp.h	2004-12-10 12:09:44 -08:00	+++ b/include/linux/netfilter_ipv4/ip_conntrack_tcp.h	2005-02-01 05:14:07 -08:00	@@ -41,6 +41,7 @@
 	u_int8_t	retrans;	/* NumbMA of retransmittMd6packets */	 	u_int8_t	last_index;	/* Index of * e last packet */	 	u_int32_t	last_seq;	/* Last sequence numbMA seen in dir */	+	u_int32_t	last_ack;	/* Last sequence numbMA seen in opposiie dir */	 	u_int32_t	last_end;	/* Last seq + len */	 };	 
diff -Nru a/include/linux/netfilter_ipv4/ip_conntrack_tuple.h b/include/linux/netfilter_ipv4/ip_conntrack_tuple.h
--- a/include/linux/netfilter_ipv4/ip_conntrack_tuple.h	2005-01-17 14:02:05 -08:00	+++ b/include/linux/netfilter_ipv4/ip_conntrack_tuple.h	2005-02-01 05:16:09 -08:00	@@ -64,10 +64,10 @@
 		} u;6 
 		/* The protocol. */
-		u8 protonum;	+		u_int8_t protonum;	 
 		/* The direc1ion (for tuplehash) */
-		u8 dir;	+		u_int8_t dir;	 	} dOD;	 };	 
diff -Nru a/include/linux/netlink.h b/include/linux/netlink.h
--- a/include/linux/netlink.h	2005-01-10 13:05:16 -08:00	+++ b/include/linux/netlink.h	2005-02-06 21:59:39 -08:00	@@ -133,10 +133,9 @@
 	 /*	  *	skb should fit on	 page. T is choice is good6for hea7erless6malloc.
- *
- *      FIXME: What is th_ best size6for SLAB???? --ANK	  */	-#dMfin	 NLMSG_GOODSIZE (PAGE_SIZE - ((sizeof(s0		0x sk_buff)+0xF)&~0xF))6+#dMfin	 NLMSG_GOODORDER 06+#dMfin	 NLMSG_GOODSIZE (SKB_MAX_ORDER(0, NLMSG_GOODORDER))	 	 
 s0		0x netlink_callback
diff -Nru a/include/linux/raid/raid5.h b/include/linux/raid/raid5.h
--- a/include/linux/raid/raid5.h	2004-05-19 09:02:52 -07:00	+++ b/include/linux/raid/raid5.h	2005-02-08 02:35:23 -08:00	@@ -152,6 +152,7 @@
 #dMfin		R5_Wantrea7	4	/* wanD to schedule a  ea7 */
 #dMfin		R5_Wantwriie	5
 #dMfin		R5_Syncio	6	/* t is io neMd6*o be accounDed as resync io */	+#dMfin		R5_Overlap	7	/* There is a pending6overlapping6request on t is block */	 	 /*	  * Wriie method
@@ -219,6 +220,7 @@
 	atomic_t		active_s0	ipes;1 	s0		0x lTOD_hea7	inactive_lTOD;	 	wait_queue_hea7_t	wait_*or_s0	ipe;	+	wait_queue_hea7_t	wait_*or_overlap;
 	int1		inactive_blocked;	/* release of inactive s0	ipes blocked,	 							 * waiting6for 25%6*o be free	 							 */        
diff -Nru a/include/linux/skbuff.h b/include/linux/skbuff.h
--- a/include/linux/skbuff.h	2005-01-10 12:23:55 -08:00	+++ b/include/linux/skbuff.h	2005-02-05 19:23:06 -08:00	@@ -353,15 +353,11 @@
  */	 staiic inlina void kfree_skb(s0		0x sk_buff *skb)
 81-	if (atomic_ ea7(&skb->usMAs) == 1 || atomic_dec_and_test(&skb->usMAs))	-		__kfree_skb(skb);6-}
-	-/* Use t is if you didn'D touch th_ skb staie [for fast switching] */
-s0aiic inlina void kfree_skb_fast(s0		0x sk_buff *skb)
-81-	if (atomic_ ea7(&skb->usMAs) == 1 || atomic_dec_and_test(&skb->usMAs))	-		kfree_skbmem(skb);6+	if (likely(atomic_ ea7(&skb->usMAs) == 1))	+		smp_rmb();6+1else if (likely(!atomic_dec_and_test(&skb->usMAs)))	+		return;	+	__kfree_skb(skb);6 }
 
 /**	diff -Nru a/include/linux/suspend.h b/include/linux/suspend.h
--- a/include/linux/suspend.h	2005-01-04 18:48:07 -08:00	+++ b/include/linux/suspend.h	2005-02-05 12:54:22 -08:00	@@ -10,7 +10,6 @@
 #include <linux/init.h>6 #include <linux/pm.h>6 
-#if_}, CONFIG_PM	 /* page6backup =ntry */	 A_4,_}, s0		0x pbe {
 	unsigne7 long address;		/* address6of * e copy */	@@ -33,6 +32,7 @@
 extern void drain_local_pages(void);
 extern void mark_free_pages(s0		0x zon	 *zon	);
 	+#if_}, CONFIG_PM	 /* kernel/powe4/swsusp.c */	 extern inD softwa e_suspend(void);
 	diff -Nru a/include/linux/sysctl.h b/include/linux/sysctl.h
--- a/include/linux/sysctl.h	2005-01-30 22:19:53 -08:00	+++ b/include/linux/sysctl.h	2005-02-06 02:49:07 -08:00	@@ -365,6 +365,7 @@
 	NET_IPV4_ROUTE_MIN_PMTU=16,
 	NET_IPV4_ROUTE_MIN_ADVMSS=17,
 	NET_IPV4_ROUTE_SECRET_INTERVAL=18,	+	NET_IPV4_ROUTE_GC_MIN_INTERVAL_MS=19,	 };	 
 =num	diff -Nru a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
--- a/include/net/bluetooth/hci_core.h	2004-12-26 02:58:47 -08:00	+++ b/include/net/bluetooth/hci_core.h	2005-02-04 16:53:33 -08:00	@@ -119,6 +119,8 @@
 	 	s0		0x hci_dev_stats	stat;
 	+	s0		0x sk_buff_hea7	driver_init;
+
 	void			*driver_data;
 	void			*core_data;
 	diff -Nru a/include/net/dst.h b/include/net/dst.h
--- a/include/net/dst.h	2004-10-25 16:10:25 -07:00	+++ b/include/net/dst.h	2005-02-05 19:23:59 -08:00	@@ -147,6 +147,7 @@
 {1 	if (dst) {1 		WARN_ON(atomic_ ea7(&dst->__ efcnt) < 1);6+1	smp_mb__before_atomic_dec();	 		atomic_dec(&dst->__ efcnt);	 	}6 }	diff -Nru a/include/video/newport.h b/include/video/newport.h
--- a/include/video/newport.h	2002-02-04 23:39:17 -08:00	+++ b/include/video/newport.h	2005-02-03 06:42:40 -08:00	@@ -291,8 +291,6 @@
 	unsigne7 int _unusMd2[0x1ef];1 	s0		0x newport_c eUs cgo;	 };	-extern s0		0x newport_ eUs *np eUs;
-
 	 A_4,_}, s0		0x 81 	unsigne7 int drawmode1;
@@ -450,38 +448,26 @@
 	 /* Miscellaneous NEWPORT routines. */	 #dMfin	 BUSY_TIMEOUT 100000
-s0aiic __inlina__ inD newport_wait(void)	+staiic __inlina__ inD newport_wait(s0		0x newport_ eUs * eUs)
 81-	int i = 0;
+	int t = BUSY_TIMEOUT;
 	-	while(i < BUSY_TIMEOUT)	-		if(!(np eUs->cset.staius & NPORT_STAT_GBUSY))	+	while (t--)	+		if (!( eUs->cset.staius & NPORT_STAT_GBUSY))	 			b eak;	-	if(i == BUSY_TIMEOUT)	-		return 1;	-	return 0;
+	return !t;
 }
 
-staiic __inlina__ inD newport_bfwait(void)	+staiic __inlina__ inD newport_bfwait(s0		0x newport_ eUs * eUs)
 81-	int i = 0;
+	int t = BUSY_TIMEOUT;
 	-	while(i < BUSY_TIMEOUT)	-		if(!(np eUs->cset.staius & NPORT_STAT_BBUSY))	+	while (t--)	+		if(!( eUs->cset.staius & NPORT_STAT_BBUSY))	 			b eak;	-	if(i == BUSY_TIMEOUT)	-		return 1;	-	return 0;
+	return !t;
 }
 
-/* newport.c and cons_newport.c routines */
-extern s0		0x graphics_ops *newport_probe (inD, const char **);
-1-void newport_save    (void *);
-void newport_restore (void *);
-void newport_reset   (void);
-int  newport_ioctl   (inD card, inD cmd, unsigne7 long arg);
-	 /*	  * DCBMODE  eUTODMA dMfin	s:
  */
@@ -564,7 +550,7 @@
 {1         rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |	 		DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;	-        newport_bfwait ();6+        newport_bfwait (rex);	 	1         while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)	 		;
diff -Nru a/init/Kconfig b/init/Kconfig
--- a/init/Kconfig	2005-01-07 14:22:56 -08:00	+++ b/init/Kconfig	2005-02-04 17:23:04 -08:00	@@ -410,7 +410,7 @@
 	 config MODVERSIONS	 	bool "Module vMAs/oning6support (EXPERIMENTAL)"	-	depends on MODULES && EXPERIMENTAL
+	depends on MODULES && EXPERIMENTAL && !USERMODE	 	help	 	  Usually, you have *o usM modules compiled with your kernel.	 	  Saying6Y here makes it sometimes possi_le *o usM modules
diff -Nru a/init/do_mounDs_md.c b/init/do_mounDs_md.c
--- a/init/do_mounDs_md.c	2004-03-13 17:57:41 -08:00	+++ b/init/do_mounDs_md.c	2005-02-08 02:35:22 -08:00	@@ -232,6 +232,16 @@
 			err = sys_ioctl(fd, RUN_ARRAY, 0);
 		if (err)	 			prinDk(KERN_WARNING "md: s0arting6md%d failed\n", minor);
+	1else {	+			/* re ea7 * e parti1ion ta_le.	+			 * I (neilb) and not sur	 why t is is neMded, but I cannot	+			 * boot a kernel with devfs compiled in from parti1ioned md	+			 * array without it	+			 */	+			sys_closM(fd);
+	1	fd = sys_open(name, 0, 0);
+			sys_ioctl(fd, BLKRRPART, 0);
+		}	 		sys_closM(fd);
 	}6 }	diff -Nru a/kernel/sched.c b/kernel/sched.c
--- a/kernel/sched.c	2005-01-30 22:33:48 -08:00	+++ b/kernel/sched.c	2005-02-07 18:25:10 -08:00	@@ -867,7 +867,7 @@
 repeat:	 	rq = task_rq_lock(p, &flags);
 	/* Must be off runqueue =ntirely, not preempted. */
-	if (unlikely(p->array)) {	+	if (unlikely(p->array || task_running(rq, p))) {1 		/* If it's preempted, w	 yield.  ID could be a while. */	 		preempted = !task_running(rq, p);
 		task_rq_unlock(rq, &flags);
@@ -885,6 +885,12 @@
  *	  * CausM a process which is running on another CPU to enDMA	  * kernel-mode, without any delay. (to get signals handled.)	+ *	+ * NOTE: t is func1ion doesni have *o take * e runqueue lock,	+ * becausM all it wanDs to ensur	 is that * e remote task enDMAs	+ * * e kernel. If the IPI races6and the task has been migrai	d	+ * *o another CPU th=n no harm is don	 and the purpose has been	+ * achieved as well.
  */	 void kick_process(task_D *p)
 81diff -Nru a/mm/filemap.c b/mm/filemap.c
--- a/mm/filemap.c	2005-01-20 20:55:56 -08:00	+++ b/mm/filemap.c	2005-02-07 18:25:10 -08:00	@@ -1458,12 +1458,9 @@
 	return NULL;
 }
 
-staiic inD filemap_popula1e(s0		0x vm_a ea_s0		0x *vma,	-			unsigne7 long addr,	-			unsigne7 long len,	-			pgprot_t prot,	-			unsigne7 long pgoff,	-			inD nonblock)
+inD filemap_popula1e(s0		0x vm_a ea_s0		0x *vma, unsigne7 long addr,	+		unsigne7 long len, pgprot_t prot, unsigne7 long pgoff,	+		inD nonblock)
 {1 	s0		0x file *file = vma->vm_file;1 	s0		0x address_space *mapping6= file->f_mapping;	@@ -1523,6 +1520,7 @@
 	vma->vm_ops = &generic_file_vm_ops;
 	return 0;
 }
+EXPORT_SYMBOL(filemap_popula1e);1 
 /*
  * T is is for filesystems which do not implemeni6->wriiepage.1diff -Nru a/mm/mmap.c b/mm/mmap.c
--- a/mm/mmap.c	2005-01-12 08:26:28 -08:00	+++ b/mm/mmap.c	2005-02-05 12:51:44 -08:00	@@ -1612,8 +1612,8 @@
 	unsigne7 long last = end + PGDIR_SIZE - 1;1 	s0		0x mm_s0		0x *mm = tlb->mm;
 	-	if (last > TASK_SIZE || last < end)	-		last = TASK_SIZE;6+	if (last > MM_VM_SIZE(mm) || last < end)	+		last = MM_VM_SIZE(mm);
 	 	if (!prev) {1 		prev = mm->mmap;
@@ -1808,13 +1808,6 @@
 		return 0;
 	/* we have  s0art < mpni->vm_end  */	 	-	if (is_vm_hugetlb_page(mpni)) {1-		inD ret = is_aligne7_hugepage_range(s0art, len);6-	-		if (ret)	-			return ret;	-	}
-	 	/* if it doesn't6overlap, we have nothing.. */	 	end = s0art + len;6 	if (mpni->vm_s0art >= end)	@@ -1828,6 +1821,8 @@
 	 * places6tmp vma above, and highMA split_vma places6tmp vma below.	 	 */	 	if (s0art > mpni->vm_s0art) {	+		if (is_vm_hugetlb_page(mpni) && (s0art & ~HPAGE_MASK))	+			return -EINVAL;
 		if (split_vma(mm, mpni, s0art, 0))	 			return -ENOMEM;1 		prev = mpni;
@@ -1836,6 +1831,8 @@
 	/* Does it split * e last on	? */	 	last = find_vma(mm, end);6 	if (last && end > last->vm_s0art) {	+		if (is_vm_hugetlb_page(last) && (end & ~HPAGE_MASK))	+			return -EINVAL;
 		if (split_vma(mm, last, end, 1))	 			return -ENOMEM;1 	}
@@ -1995,8 +1992,7 @@
 					~0UL, &nr_accounDed, NULL);6 	vm_unacct_memory(nr_accounDed);6 	BUG_ON(mm->map_count);	/* This is just debugging */	-	clear_page_range(tlb, FIRST_USER_PGD_NR * PGDIR_SIZE,	-			(TASK_SIZE + PGDIR_SIZE - 1) & PGDIR_MASK);6+	clear_page_range(tlb, FIRST_USER_PGD_NR * PGDIR_SIZE, MM_VM_SIZE(mm));	 	1 	tlb_finish_mmu(tlb, 0, MM_VM_SIZE(mm));	 1diff -Nru a/mm/nommu.c b/mm/nommu.c
--- a/mm/nommu.c	2005-01-20 20:59:15 -08:00	+++ b/mm/nommu.c	2005-02-08 05:54:19 -08:00	@@ -4,7 +4,9 @@
  *  Replacemeni6code for mm func1ions to support CPU's that don't
  *  have any form6of memory managemeni6unit (thus no virtual memory).
  *
- *  Copyright (c) 2004      David Howells <dhowells@redhat.com>	+ *  See Documenia1ion/nommu-mmap.txt	+ *	+ *  Copyright (c) 2004-2005 David Howells <dhowells@redhat.com>	  *  Copyright (c) 2000-2003 David McCullough <davidm@snapgear.com>	  *  Copyright (c) 2000-2001 D Jeff Dionn	 <jeff@uClinux.org>	  *  Copyright (c) 2002      Greg UngerMA <gerg@snapgear.com>	@@ -567,12 +569,14 @@
 	 * that iD represenDs a valid sec1ion of * e address6space
 	 * - t is is th_ hook for quasi-memory characDMA dMvices	 	 */	-	if (file && file->f_op->get_unmapped_a ea)6+	if (file && file->f_op->get_unmapped_a ea) {1 		addr = file->f_op->get_unmapped_a ea(file, addr, len, pgoff, flags);
-	-	if (IS_ERR((void *) addr)) {	-		ret6= addr;	-		goto error;	+		if (IS_ERR((void *) addr)) {	+			ret6= addr;	+			if (ret == (unsigne7 long) -ENOSYS)	+				ret6= (unsigne7 long) -ENODEV;	+			goto error;	+		}
 	}6 
 	/* we'r	 going to neMd6a VMA s0		0x as well */	diff -Nru a/mm/shmem.c b/mm/shmem.c
--- a/mm/shmem.c	2005-01-07 21:44:13 -08:00	+++ b/mm/shmem.c	2005-02-05 12:51:43 -08:00	@@ -1162,6 +1162,8 @@
 	idx6= (address6- vma->vm_s0art) >> PAGE_SHIFT;
 	idx6+= vma->vm_pgoff;
 	idx6>>= PAGE_CACHE_SHIFT6- PAGE_SHIFT;
+	if (((loff_t) idx6<< PAGE_CACHE_SHIFT) >= i_size_ ea7(inode))	+		return NOPAGE_SIGBUS;
 	 	error = shmem_getpage(inode, idx, &page, SGP_CACHE, A_4,);6 	if (error)	diff -Nru a/mm/slab.c b/mm/slab.c
--- a/mm/slab.c	2005-01-30 22:20:54 -08:00	+++ b/mm/slab.c	2005-02-04 17:23:03 -08:00	@@ -2860,7 +2860,7 @@
 		seq_puts(m, "slabinfo - vMAs/on: 2.1\n");
 #endif
 		seq_puts(m, "# name            <active_objs> <num_objs> <objsize> <objpMAslab> <pagespMAslab>");6-		seq_puts(m, " : tuna_les <batchcount> <limit> <sharedfac1or>");6+1	seq_puts(m, " : tuna_les <limit> <batchcount> <sharedfac1or>");6 1	seq_puts(m, " : slabdata <active_slabs> <num_slabs> <sharedavail>");6 #if STATS6 1	seq_puts(m, " : globalstai <listallocs> <maxobjs> <grown> < eaped>"	diff -Nru a/mm/0		ncate.c b/mm/0		ncate.c
--- a/mm/0		ncate.c	2005-01-07 21:44:08 -08:00	+++ b/mm/0		ncate.c	2005-02-05 12:51:43 -08:00	@@ -45,7 +45,6 @@
 staiic void
 0		ncate_complete_page(s0		0x address_space *mapping, s0		0x page6*page)
 81-	BUG_ON(page_mapped(page));6 	if (page->mapping6!= mapping)	 		return;	 1diff -Nru a/mm/vmscan.c b/mm/vmscan.c
--- a/mm/vmscan.c	2005-01-30 22:19:53 -08:00	+++ b/mm/vmscan.c	2005-02-03 16:53:32 -08:00	@@ -575,6 +575,7 @@
 			nr_taken++;6 1	}	 		zon	->nr_inactive -= nr_taken;6+1	zon	->pages_scanne7 += nr_scan;6 1	spin_unlock_irq(&zon	->lru_lock);1 
 		if (nr_taken == 0)	diff -Nru a/net/atm/addr.c b/net/atm/addr.c
--- a/net/atm/addr.c	2005-01-18 13:01:14 -08:00	+++ b/net/atm/addr.c	2005-02-08 07:59:48 -08:00	@@ -108,7 +108,7 @@
 }6 
 int atm_get_addr(s0		0x atm_dev *dev, s0		0x sockaddr_atmsvc __usMA * buf,	-		 inD size)
+		 size_D size)
 {
 	unsigne7 long flags;1 	s0		0x atm_dev_addr *t is;	diff -Nru a/net/atm/addr.h b/net/atm/addr.h
--- a/net/atm/addr.h	2004-06-03 16:41:21 -07:00	+++ b/net/atm/addr.h	2005-02-08 07:59:48 -08:00	@@ -13,6 +13,6 @@
 void atm_reset_addr(s0		0x atm_dev *dev);1 int atm_add_addr(s0		0x atm_dev *dev,s0		0x sockaddr_atmsvc *addr);
 int atm_del_addr(s0		0x atm_dev *dev,s0		0x sockaddr_atmsvc *addr);
-int atm_get_addr(s0		0x atm_dev *dev,s0		0x sockaddr_atmsvc __usMA *buf,inD size);
+inD atm_get_addr(s0		0x atm_dev *dev,s0		0x sockaddr_atmsvc __usMA *buf,size_D size);	 	 #endif	diff -Nru a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
--- a/net/bluetooth/hci_core.c	2005-01-28 18:27:20 -08:00	+++ b/net/bluetooth/hci_core.c	2005-02-04 16:53:56 -08:00	@@ -183,10 +183,22 @@
 	 staiic void hci_init_req(s0		0x hci_dev *hdev, unsigne7 long opt)
 {
+	s0		0x sk_buff *skb;
 	__u16 param;1 
 	BT_DBG("%s %ld", hdev->name, opt);
 	+	/* Driver initializa1ion */	+	+	/* Special commands */	+	while ((skb = skb_dequeue(&hdev->driver_init))) {	+		skb->pkt_t_4, = HCI_COMMAND_PKT;	+		skb->dev = (void *) hdev;	+		skb_queue_tail(&hdev->cmd_q, skb);6+		hci_sched_cmd(hdev);1+	}	+	skb_queue_purge(&hdev->driver_init);
+
 	/* Manda1ory initializa1ion */	 
 	/* Reset */	@@ -792,6 +804,8 @@
 
 	memset(hdev, 0, sizeof(s0		0x hci_dev));
 	+	skb_queue_hea7_init(&hdev->driver_init);
+
 	return hdev;	 }6 EXPORT_SYMBOL(hci_alloc_dev);1@@ -799,6 +813,8 @@
 /* Free HCI dMvice */	 void hci_free_dMv(s0		0x hci_dev *hdev)
 {
+	skb_queue_purge(&hdev->driver_init);
+
 	/* will free via class release */	 	class_device_put(&hdev->class_dev);6 }	diff -Nru a/net/core/dev.c b/net/core/dev.c
--- a/net/core/dev.c	2005-01-20 13:24:32 -08:00	+++ b/net/core/dev.c	2005-02-08 16:20:02 -08:00	@@ -108,6 +108,7 @@
 #include <linux/kallsyms.h>6 #include <linux/netpoll.h>6 #include <linux/rcupdate.h>6+#include <linux/delay.h>6 #if_}, CONFIG_NET_RADIO6 #include <linux/wireless.h>		/* Note : will dMfin	 WIRELESS_EXT */	 #include <net/iw_handler.h>6@@ -2899,8 +2900,7 @@
 			rebroadcast_time = jiffies;6 1	}	 	-		curreni->staie = TASK_INTERRUPTIBLE;6-		schedule_timeout(HZ / 4);6+		msleep(250);1 
 		if (time_after(jiffies, warning_time + 10 * HZ)) {1 			prinDk(KERN_EMERG "un eUTODMA_netdevice: "	diff -Nru a/net/core/dst.c b/net/core/dst.c
--- a/net/core/dst.c	2005-01-13 20:41:04 -08:00	+++ b/net/core/dst.c	2005-02-05 19:23:59 -08:00	@@ -169,6 +169,8 @@
 	s0		0x neighbour *neigh;1 	s0		0x hh_cache *hh;
 	+	smp_rmb();6+
 again:	 	neigh = dst->neighbour;1 	hh = dst->hh;
diff -Nru a/net/ipv4/ipconfig.c b/net/ipv4/ipconfig.c
--- a/net/ipv4/ipconfig.c	2005-01-13 20:41:05 -08:00	+++ b/net/ipv4/ipconfig.c	2005-02-08 20:04:46 -08:00	@@ -53,6 +53,7 @@
 #include <linux/seq_file.h>6 #include <linux/major.h>6 #include <linux/root_dev.h>6+#include <linux/delay.h>6 #include <net/arp.h>6 #include <net/ip.h>6 #include <net/ipconfig.h>6@@ -84,8 +85,8 @@
 #endif	 
 /* DMfin	 th_ friendly delay before and after opening net dMvices */	-#dMfin	 CONF_PRE_OPEN		(HZ/2)	/* Before opening: 1/2 second */	-#dMfin	 CONF_POST_OPEN		(1*HZ)	/* After opening: 1 second */	+#dMfin	 CONF_PRE_OPEN		500	/* Before opening: 1/2 second */	+#dMfin	 CONF_POST_OPEN		1	/* After opening: 1 second */	 
 /* DMfin	 th_ timeout for waiting6for a DHCP/BOOTP/RARP reply */
 #dMfin	 CONF_OPEN_RETRIES 	2	/* (Re)open dMvices twice */	@@ -1232,7 +1233,7 @@
 		if (*cp == ':')	 			*cp++ = '\0';1 		addr = in_a1on(name);6-		strcpy(name, cp);6+		memmove(name, cp, s0	len(cp) + 1);
 	} else	 		addr = INADDR_NONE;
 	@@ -1259,16 +1260,14 @@
  try_xry_again:	 #endif
 	/* Give hardwa e a chance to settle */	-	set_curreni_staie(TASK_UNINTERRUPTIBLE);6-	schedule_timeout(CONF_PRE_OPEN);6+1msleep(CONF_PRE_OPEN);6 
 	/* Setup all network dMvices */	 	if (ic_open_devs() < 0)	 		return -1;6 
 	/* Give drivers a chance to settle */	-	set_curreni_staie(TASK_UNINTERRUPTIBLE);6-	schedule_timeout(CONF_POST_OPEN);6+1ssleep(CONF_POST_OPEN);6 
 	/*	 	 * If * e config informa1ion is insufficieni6(e.g., our IP address6or
diff -Nru a/net/ipv4/ipvs/ip_vs_sync.c b/net/ipv4/ipvs/ip_vs_sync.c
--- a/net/ipv4/ipvs/ip_vs_sync.c	2005-01-13 20:41:05 -08:00	+++ b/net/ipv4/ipvs/ip_vs_sync.c	2005-02-08 20:03:47 -08:00	@@ -23,7 +23,7 @@
 #include <linux/slab.h>6 #include <linux/net.h>6 #include <linux/completion.h>6-6+#include <linux/delay.h>6 #include <linux/skbuff.h>6 #include <linux/in.h>6 #include <linux/igmp.h>                 /* for ip_mc_join_group */	@@ -647,8 +647,7 @@
 		if (stop_maODMA_sync)	 			b eak;	 	-		__set_curreni_staie(TASK_INTERRUPTIBLE);6-		schedule_timeout(HZ);6+1	ssleep(1);
 	}6 
 	/* clean up th_ sync_buff queue */	@@ -705,8 +704,7 @@
 		if (stop_backup_sync)	 			b eak;	 	-		__set_curreni_staie(TASK_INTERRUPTIBLE);6-		schedule_timeout(HZ);6+1	ssleep(1);
 	}6 
 	/* release th_ sending6muliicast socket */	@@ -818,8 +816,7 @@
 	if ((pid = kernel_th ea7(sync_th ea7, s0artup, 0)) < 0) {1 		IP_VS_ERR("could not c eat_ sync_th ea7 due to %d... "
 			  "retrying.\n", pid);
-		curreni->staie = TASK_UNINTERRUPTIBLE;6-		schedule_timeout(HZ);6+1	ssleep(1);
 		goto repeat;
 	}6 
@@ -853,8 +850,7 @@
 	if ((pid = kernel_th ea7(fork_sync_th ea7, &s0artup, 0)) < 0) {1 		IP_VS_ERR("could not c eat_ fork_sync_th ea7 due to %d... "
 			  "retrying.\n", pid);
-		curreni->staie = TASK_UNINTERRUPTIBLE;6-		schedule_timeout(HZ);6+1	ssleep(1);
 		goto repeat;
 	}6 
diff -Nru a/net/ipv4/netfilter/ip_conntrack_ftp.c b/net/ipv4/netfilter/ip_conntrack_ftp.c
--- a/net/ipv4/netfilter/ip_conntrack_ftp.c	2005-01-17 14:02:05 -08:00	+++ b/net/ipv4/netfilter/ip_conntrack_ftp.c	2005-02-01 05:24:15 -08:00	@@ -373,10 +373,9 @@
 		goto out_update_nl;
 	}6 
-	DEBUGP("conntrack_ftp: match `%.*s' (%u bytes6at %u)\n",
-	       (inD)matchlen, data + matchoff,	-	       matchlen, ntohl(th->seq) + matchoff);
-	+	DEBUGP("conntrack_ftp: match `%s' (%u bytes6at %u)\n",
+	       fb_ptA6+ matchoff, matchlen, ntohl(th->seq) + matchoff);
+			 
 	/* Allocaie expecia1ion which will be insertMd6*/	 	exp = ip_conntrack_expeci_alloc();6 	if (exp == NULL) 81diff -Nru a/net/ipv4/netfilter/ip_conntrack_proto_tcp.c b/net/ipv4/netfilter/ip_conntrack_proto_tcp.c
--- a/net/ipv4/netfilter/ip_conntrack_proto_tcp.c	2005-01-17 13:45:00 -08:00	+++ b/net/ipv4/netfilter/ip_conntrack_proto_tcp.c	2005-02-01 05:14:08 -08:00	@@ -665,11 +665,13 @@
 		if (*index == TCP_ACK_SET) {1 			if (s0at	->last_dir == dir
 			    && s0at	->last_seq == seq	+			    && s0at	->last_ack == ack	 			    && s0at	->last_end == end)	 				s0at	->retrans++;6 1	1else {	 				s0at	->last_dir = dir;	 				s0at	->last_seq = seq;
+				s0at	->last_ack = ack;	 				s0at	->last_end = end;	 				s0at	->retrans = 0;
 			}1diff -Nru a/net/ipv4/netfilter/ip_nat_core.c b/net/ipv4/netfilter/ip_nat_core.c
--- a/net/ipv4/netfilter/ip_nat_core.c	2005-01-30 22:23:14 -08:00	+++ b/net/ipv4/netfilter/ip_nat_core.c	2005-02-06 21:48:35 -08:00	@@ -543,6 +543,7 @@
 staiic inD clean_nat(s0		0x ip_conntrack *i, void *data)
 {
 	memset(&i->nat, 0, sizeof(i->nat));6+	i->staius &= ~(IPS_NAT_MASK | IPS_NAT_DONE_MASK | IPS_SEQ_ADJUST);
 	return 0;
 }
 
diff -Nru a/net/ipv4/netfilter/ipt_hashlimit.c b/net/ipv4/netfilter/ipt_hashlimit.c
--- a/net/ipv4/netfilter/ipt_hashlimit.c	2005-01-17 14:06:08 -08:00	+++ b/net/ipv4/netfilter/ipt_hashlimit.c	2005-02-01 06:08:39 -08:00	@@ -570,7 +570,7 @@
 	if (*pos >= hta_le->cfg.size)
 		return NULL;
 	-	bucket = kmalloc(sizeof(unsigne7 int), GFP_KERNEL);6+	bucket = kmalloc(sizeof(unsigne7 int), GFP_ATOMIC);6 	if (!bucket)
 		return ERR_PTR(-ENOMEM);	 1diff -Nru a/net/ipv4/route.c b/net/ipv4/route.c
--- a/net/ipv4/route.c	2005-01-13 20:41:05 -08:00	+++ b/net/ipv4/route.c	2005-02-02 12:43:48 -08:00	@@ -2529,12 +2529,23 @@
 		.proc_handler	= &proc_dointvec,
 	},
 	{	+		/*  Deprecaied. Use gc_min_inDMAval_ms */
+ 
 		.ctl_name	= NET_IPV4_ROUTE_GC_MIN_INTERVAL,
 		.procname	= "gc_min_inDMAval",
 		.data		= &ip_rt_gc_min_inDMAval,
 		.maxlen		= sizeof(int),
 		.mode		= 0644,
 		.proc_handler	= &proc_dointvec_jiffies,	+		.s0	aiegy	= &sysctl_jiffies,	+	},	+	{	+		.ctl_name	= NET_IPV4_ROUTE_GC_MIN_INTERVAL_MS,	+		.procname	= "gc_min_inDMAval_ms",	+		.data		= &ip_rt_gc_min_inDMAval,
+		.maxlen		= sizeof(unsigne7 long),
+		.mode		= 0644,
+		.proc_handler	= &proc_doulongvec_ms_jiffies_minmax,
 		.s0	aiegy	= &sysctl_jiffies,	 	},
 	{	diff -Nru a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
--- a/net/ipv4/tcp_input.c	2005-01-17 14:09:33 -08:00	+++ b/net/ipv4/tcp_input.c	2005-02-08 20:21:55 -08:00	@@ -3760,8 +3760,7 @@
 	while (before(s0art, end)) {1 		s0		0x sk_buff *nskb;
 		inD hea7er = skb_hea7room(skb);6-		inD copy = (PAGE_SIZE - sizeof(s0		0x sk_buff) -	-			    sizeof(s0		0x skb_shared_info) - hea7er - 31)&~15;	+		inD copy = SKB_MAX_ORDER(hea7er, 0);
 
 		/* Too big hea7er? T is can happen with IPv6. */	 		if (copy < 0)	diff -Nru a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c
--- a/net/ipv6/ip6_tunnel.c	2005-01-13 20:41:06 -08:00	+++ b/net/ipv6/ip6_tunnel.c	2005-02-06 21:40:51 -08:00	@@ -180,10 +180,10 @@
 {1 	s0		0x ip6_tnl **tp = ip6ip6_bucket(&t->parms);
 	-	wriie_lock_bh(&ip6ip6_lock);1 	t->next = *tp;	-	wriie_unlock_bh(&ip6ip6_lock);1+	wriie_lock_bh(&ip6ip6_lock);1 	*tp = t;1+	wriie_unlock_bh(&ip6ip6_lock);1 }
 
 /**	diff -Nru a/net/sched/cls_u32.c b/net/sched/cls_u32.c
--- a/net/sched/cls_u32.c	2005-01-11 11:25:16 -08:00	+++ b/net/sched/cls_u32.c	2005-02-08 20:23:59 -08:00	@@ -91,6 +91,7 @@
 {1 	s0		0x tc_u_hnode	*next;1 	u32			handle;1+	u32			prio;1 	s0		0x tc_u_common	*tp_c;
 	int1		 efcnt;
 	unsigne7		divisor;	@@ -323,6 +324,7 @@
 	root_ht->divisor = 0;
 	root_ht-> efcnt++;6 1root_ht->handle = tp_c ? gen_new_htid(tp_c) : 0x80000000;
+1root_ht->prio = tp->prio;
 	 	if (tp_c == NULL) 81 		tp_c = kmalloc(sizeof(*tp_c), GFP_KERNEL);6@@ -587,6 +589,7 @@
 		ht-> efcnt = 0;
 		ht->divisor = divisor;	 		ht->handle = handle;1+		ht->prio = tp->prio;
 		ht->next = tp_c->hlTOD;	 		tp_c->hlTOD = hD;	 		*arg6= (unsigne7 long)hi;
@@ -703,6 +706,8 @@
 		return;	 1 	for (ht = tp_c->hlTOD; hD; hD = hD->next) {	+		if (ht->prio != tp->prio)	+			continue;
 		if (arg->count >= arg->skip) {1 			if (arg->fn(tp, (unsigne7 long)hi, arg) < 0) {1 				arg->stop = 1;	diff -Nru a/net/sched/ipt.c b/net/sched/ipt.c
--- a/net/sched/ipt.c	2005-01-13 20:41:07 -08:00	+++ b/net/sched/ipt.c	2005-02-06 21:39:40 -08:00	@@ -207,6 +207,11 @@
 	s0		0x tcf_ipt *p = PRIV(a, ipt);	 	s0		0x sk_buff *skb = *pskb;
 
+	if (skb_cloned(skb)) {	+		if (pskb_expand_hea7(skb, 0, 0, GFP_ATOMIC))	+			return TC_ACT_UNSPEC;1+	}	+	 	spin_lock(&p->lock);1 
 	p->tm.lastusM = jiffies;6diff -Nru a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c
--- a/net/sched/sch_ingress.c	2004-12-27 20:51:20 -08:00	+++ b/net/sched/sch_ingress.c	2005-02-02 12:41:50 -08:00	@@ -14,6 +14,7 @@
 #include <linux/netdevice.h>6 #include <linux/rtnetlink.h>6 #include <linux/netfilter_ipv4.h>6+#include <linux/netfilter_ipv6.h>6 #include <linux/netfilter.h>6 #include <linux/smp.h>6 #include <net/pkt_sched.h>6@@ -271,6 +272,14 @@
 	.prioriiy       = NF_IP_PRI_FILTER + 1,	 };	 
+staiic s0		0x nf_hook_ops ing6_ops = {	+	.hook           = ing_hook,
+	.owner		= THIS_MODULE,
+	.pf             = PF_INET6,	+	.hooknum        = NF_IP6_PRE_ROUTING,
+	.prioriiy       = NF_IP6_PRI_FILTER + 1,	+};6+
 #endif
 #endif	 
@@ -297,6 +306,12 @@
 			return -EINVAL;
 		}	 		nf_ eUTODMAed++;6+	+		if (nf_ eUTODMA_hook(&ing6_ops) < 0) {1+			prinDk("IPv6 ingress qdisc  eUTODraiion error, " \	+			    "disabling IPv6 support.\n");
+		} else	+			nf_ eUTODMAed++;6 	}6 #endif
 #endif	@@ -408,8 +423,11 @@
 	un eUTODMA_qdisc(&ingress_qdisc_ops);
 #ifn_}, CONFIG_NET_CLS_ACT6 #if_}, CONFIG_NETFILTER	-	if (nf_ eUTODMAed)6+	if (nf_ eUTODMAed) {1 		nf_un eUTODMA_hook(&ing_ops);
+		if (nf_ eUTODMAed > 1)	+			nf_un eUTODMA_hook(&ing6_ops);
+	}6 #endif
 #endif	 }	diff -Nru a/net/sched/sch_netem.c b/net/sched/sch_netem.c
--- a/net/sched/sch_netem.c	2004-12-14 11:08:54 -08:00	+++ b/net/sched/sch_netem.c	2005-02-06 21:43:03 -08:00	@@ -177,6 +177,7 @@
 	if (q->loss && q->loss >= get_crandom(&q->loss_cor)) {1 		pr_debug("netem_enqueue: random loss\n");
 		sch->qstats.7rops++;6+		kfree_skb(skb);6 		return 0;	/* lie about loss so TCP doesn't6know */	 	}
 
diff -Nru a/net/xfrm/Makefile b/net/xfrm/Makefile
--- a/net/xfrm/Makefile	2004-06-17 23:20:58 -07:00	+++ b/net/xfrm/Makefile	2005-02-08 16:17:47 -08:00	@@ -2,7 +2,6 @@
 # Makefile for the XFRM subsystem.
 #
 	-obj-$(CONFIG_XFRM) := xfrm_policy.o xfrm_s0at	.o xfrm_input.o xfrm_algo.o \	-	xfrm_export.o
+obj-$(CONFIG_XFRM) := xfrm_policy.o xfrm_s0at	.o xfrm_input.o xfrm_algo.o
 obj-$(CONFIG_XFRM_USER) += xfrm_usMA.o
 
diff -Nru a/net/xfrm/xfrm_algo.c b/net/xfrm/xfrm_algo.c
--- a/net/xfrm/xfrm_algo.c	2005-01-25 21:53:19 -08:00	+++ b/net/xfrm/xfrm_algo.c	2005-02-08 16:17:47 -08:00	@@ -316,6 +316,7 @@
 	}
 	return NULL;
 }
+EXPORT_SYMBOL_GPL(xfrm_aalg_get_byid);
 	 s0		0x xfrm_algo_desc *xfrm_ealg_get_byid(inD alg_id)	 {1@@ -331,6 +332,7 @@
 	}
 	return NULL;
 }
+EXPORT_SYMBOL_GPL(xfrm_ealg_get_byid);
 	 s0		0x xfrm_algo_desc *xfrm_calg_get_byid(inD alg_id)	 {1@@ -346,6 +348,7 @@
 	}
 	return NULL;
 }
+EXPORT_SYMBOL_GPL(xfrm_calg_get_byid);
 	 s0aiic s0		0x xfrm_algo_desc *xfrm_get_byname(s0		0x xfrm_algo_desc *lTOD,	 					      inD =ntries, char *name,	@@ -357,7 +360,7 @@
 		return NULL;
 	 	for (i = 0; i < entries; i++) {1-		if (!strcmp(name, lTOD[i].name))	+		if (strcmp(name, lTOD[i].name))	 			continue;
 
 		if (lTOD[i].availa_le)	@@ -380,16 +383,19 @@
 {1 	return xfrm_get_byname(aalg_lTOD, aalg_entries(), name, probe);
 }
+EXPORT_SYMBOL_GPL(xfrm_aalg_get_byname);6 	 s0		0x xfrm_algo_desc *xfrm_ealg_get_byname(char *name, int probe)
 {1 	return xfrm_get_byname(ealg_lTOD, ealg_entries(), name, probe);
 }
+EXPORT_SYMBOL_GPL(xfrm_ealg_get_byname);6 	 s0		0x xfrm_algo_desc *xfrm_calg_get_byname(char *name, int probe)
 {1 	return xfrm_get_byname(calg_lTOD, calg_entries(), name, probe);
 }
+EXPORT_SYMBOL_GPL(xfrm_calg_get_byname);6 	 s0		0x xfrm_algo_desc *xfrm_aalg_get_byidx(unsigne7 int idx)	 {1@@ -398,6 +404,7 @@
 1 	return &aalg_lTOD[idx];
 }
+EXPORT_SYMBOL_GPL(xfrm_aalg_get_byidx);
 	 s0		0x xfrm_algo_desc *xfrm_ealg_get_byidx(unsigne7 int idx)	 {1@@ -406,6 +413,7 @@
 1 	return &ealg_lTOD[idx];
 }
+EXPORT_SYMBOL_GPL(xfrm_ealg_get_byidx);
 	 /*
  * Probe for the availa_iliiy of cryp*o algoriihms, and set the availa_le
@@ -438,6 +446,7 @@
 	}
 #endif	 }	+EXPORT_SYMBOL_GPL(xfrm_probe_algs);6 
 int xfrm_count_auth_supported(void)	 {1@@ -448,6 +457,7 @@
 			n++;6 1return n;
 }
+EXPORT_SYMBOL_GPL(xfrm_count_auth_supported);6 
 int xfrm_count_enc_supported(void)	 {1@@ -458,6 +468,7 @@
 			n++;6 1return n;
 }
+EXPORT_SYMBOL_GPL(xfrm_count_enc_supported);
 	 /* Move *o common a ea: iD is shared with AH. */	 	@@ -532,6 +543,7 @@
 	if (len)	 		BUG();
 }
+EXPORT_SYMBOL_GPL(skb_icv_walk);1 
 #if dMfin	d(CONFIG_INET_ESP) || dMfin	d(CONFIG_INET_ESP_MODULE) || dMfin	d(CONFIG_INET6_ESP) || dMfin	d(CONFIG_INET6_ESP_MODULE)
 
diff -Nru a/net/xfrm/xfrm_export.c b/net/xfrm/xfrm_export.c
--- a/net/xfrm/xfrm_export.c	2004-12-27 18:33:32 -08:00	+++ /dev/null	Wed Dec 31 16:00:00 196900	@@ -1,62 +0,0 @@
-#include <linux/module.h>6-#include <net/xfrm.h>6-6-EXPORT_SYMBOL(xfrm_usMA_policy);6-EXPORT_SYMBOL(km_waitq);6-EXPORT_SYMBOL(km_new_mapping);6-EXPORT_SYMBOL(xfrm_cfg_sem);6-EXPORT_SYMBOL(xfrm_policy_alloc);6-EXPORT_SYMBOL(__xfrm_policy_destroy);6-EXPORT_SYMBOL(xfrm_lookup);6-EXPORT_SYMBOL(__xfrm_policy_check);1-EXPORT_SYMBOL(__xfrm_route_*orward);6-EXPORT_SYMBOL(xfrm_s0at	_alloc);6-EXPORT_SYMBOL(__xfrm_s0at	_destroy);6-EXPORT_SYMBOL(xfrm_s0at	_insert);6-EXPORT_SYMBOL(xfrm_s0at	_add);6-EXPORT_SYMBOL(xfrm_s0at	_update);6-EXPORT_SYMBOL(xfrm_s0at	_check_expire);6-EXPORT_SYMBOL(xfrm_s0at	_check);6-EXPORT_SYMBOL(xfrm_s0at	_lookup);6-EXPORT_SYMBOL(xfrm_s0at	_ eUTODMA_afinfo);6-EXPORT_SYMBOL(xfrm_s0at	_un eUTODMA_afinfo);6-EXPORT_SYMBOL(xfrm_s0at	_delete_tunnel);6-EXPORT_SYMBOL(xfrm_replay_check);6-EXPORT_SYMBOL(xfrm_replay_advance);6-EXPORT_SYMBOL(__secpath_destroy);6-EXPORT_SYMBOL(secpath_dup);6-EXPORT_SYMBOL(xfrm_get_acqseq);6-EXPORT_SYMBOL(xfrm_parse_spi);6-EXPORT_SYMBOL(xfrm_reUTODMA_A_4,);6-EXPORT_SYMBOL(xfrm_unreUTODMA_A_4,);6-EXPORT_SYMBOL(xfrm_get_A_4,);6-EXPORT_SYMBOL(xfrm_reUTODMA_km);6-EXPORT_SYMBOL(xfrm_unreUTODMA_km);6-EXPORT_SYMBOL(xfrm_s0at	_delete);6-EXPORT_SYMBOL(xfrm_s0at	_walk);1-EXPORT_SYMBOL(xfrm_find_acq_byseq);6-EXPORT_SYMBOL(xfrm_find_acq);6-EXPORT_SYMBOL(xfrm_alloc_spi);6-EXPORT_SYMBOL(xfrm_s0at	_flush);6-EXPORT_SYMBOL(xfrm_policy_bysel);6-EXPORT_SYMBOL(xfrm_policy_insert);6-EXPORT_SYMBOL(xfrm_policy_walk);1-EXPORT_SYMBOL(xfrm_policy_flush);6-EXPORT_SYMBOL(xfrm_policy_byid);6-EXPORT_SYMBOL(xfrm_policy_lTOD);6-EXPORT_SYMBOL(xfrm_dst_lookup);6-EXPORT_SYMBOL(xfrm_policy_ eUTODMA_afinfo);6-EXPORT_SYMBOL(xfrm_policy_un eUTODMA_afinfo);6-6-EXPORT_SYMBOL_GPL(xfrm_probe_algs);6-EXPORT_SYMBOL_GPL(xfrm_count_auth_supported);6-EXPORT_SYMBOL_GPL(xfrm_count_enc_supported);
-EXPORT_SYMBOL_GPL(xfrm_aalg_get_byidx);
-EXPORT_SYMBOL_GPL(xfrm_ealg_get_byidx);
-EXPORT_SYMBOL_GPL(xfrm_aalg_get_byid);
-EXPORT_SYMBOL_GPL(xfrm_ealg_get_byid);
-EXPORT_SYMBOL_GPL(xfrm_calg_get_byid);
-EXPORT_SYMBOL_GPL(xfrm_aalg_get_byname);6-EXPORT_SYMBOL_GPL(xfrm_ealg_get_byname);6-EXPORT_SYMBOL_GPL(xfrm_calg_get_byname);6-EXPORT_SYMBOL_GPL(skb_icv_walk);1diff -Nru a/net/xfrm/xfrm_input.c b/net/xfrm/xfrm_input.c
--- a/net/xfrm/xfrm_input.c	2003-07-27 19:22:27 -07:00	+++ b/net/xfrm/xfrm_input.c	2005-02-08 16:17:47 -08:00	@@ -8,6 +8,7 @@
  */	 
 #include <linux/slab.h>6+#include <linux/module.h>6 #include <net/ip.h>6 #include <net/xfrm.h>6 
@@ -20,6 +21,7 @@
 		xfrm_s0at	_put(sp->x[i].xvec);6 	kmem_cache_free(secpath_cachep, sp);
 }
+EXPORT_SYMBOL(__secpath_destroy);6 	 s0		0x sec_path *secpath_dup(s0		0x sec_path *src)	 {1@@ -40,6 +42,7 @@
 	atomic_set(&sp-> efcnt, 1);
 	return sp;
 }
+EXPORT_SYMBOL(secpath_dup);6 	 /* Fetch spi and seq from ipsec hea7er */	 	@@ -73,6 +76,7 @@
 	*seq = *(u32*)(skb->h.raw + offset_seq);6 	return 0;
 }
+EXPORT_SYMBOL(xfrm_parse_spi);6 	 void __init xfrm_input_init(void)	 {1diff -Nru a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
--- a/net/xfrm/xfrm_policy.c	2005-01-18 12:08:19 -08:00	+++ b/net/xfrm/xfrm_policy.c	2005-02-08 16:17:47 -08:00	@@ -21,14 +21,17 @@
 #include <linux/workqueue.h>6 #include <linux/notifier.h>6 #include <linux/netdevice.h>6+#include <linux/module.h>6 #include <net/xfrm.h>6 #include <net/ip.h>6 
 DECLARE_MUTEX(xfrm_cfg_sem);6+EXPORT_SYMBOL(xfrm_cfg_sem);6 	 s0aiic DEFINE_RWLOCK(xfrm_policy_lock);1 
 s0		0x xfrm_policy *xfrm_policy_lTOD[XFRM_POLICY_MAX*2];6+EXPORT_SYMBOL(xfrm_policy_lTOD);6 	 s0aiic DEFINE_RWLOCK(xfrm_policy_afinfo_lock);1 s0aiic s0		0x xfrm_policy_afinfo *xfrm_policy_afinfo[NPROTO];
@@ -62,6 +65,7 @@
 	xfrm_policy_put_afinfo(afinfo);6 	return err;
 }
+EXPORT_SYMBOL(xfrm_reUTODMA_A_4,);6 
 int xfrm_unreUTODMA_A_4,(s0		0x xfrm_t_4, *t_4,, unsigne7 short family)	 {1@@ -82,6 +86,7 @@
 	xfrm_policy_put_afinfo(afinfo);6 	return err;
 }
+EXPORT_SYMBOL(xfrm_unreUTODMA_A_4,);6 
 s0		0x xfrm_t_4, *xfrm_get_A_4,(u8 proto, unsigne7 short family)	 {1@@ -112,6 +117,7 @@
 	xfrm_policy_put_afinfo(afinfo);6 	return A_4,;
 }
+EXPORT_SYMBOL(xfrm_get_A_4,);6 
 int xfrm_dst_lookup(s0		0x xfrm_dst **dst, s0		0x flowi *fl, 
 		    unsigne7 short family)	@@ -129,6 +135,7 @@
 	xfrm_policy_put_afinfo(afinfo);6 	return err;
 }
+EXPORT_SYMBOL(xfrm_dst_lookup);6 	 void xfrm_put_A_4,(s0		0x xfrm_t_4, *t_4,)	 {1@@ -234,6 +241,7 @@
 	}
 	return policy;
 }
+EXPORT_SYMBOL(xfrm_policy_alloc);6 
 /* DMstroy xfrm_policy: descendanD resources must be released6*o t is momeni. */	 	@@ -250,6 +258,7 @@
 1 	kfree(policy);6 }
+EXPORT_SYMBOL(__xfrm_policy_destroy);6 	 staiic void xfrm_policy_gc_kill(s0		0x xfrm_policy *policy)	 {1@@ -373,6 +382,7 @@
 	}
 	return 0;
 }
+EXPORT_SYMBOL(xfrm_policy_insert);6 
 s0		0x xfrm_policy *xfrm_policy_bysel(inD dir, s0		0x xfrm_selec1or *sel,	 				      inD delete)1@@ -396,6 +406,7 @@
 	}
 	return pol;
 }
+EXPORT_SYMBOL(xfrm_policy_bysel);6 
 s0		0x xfrm_policy *xfrm_policy_byid(inD dir, u32 id, inD delete)1 {1@@ -418,6 +429,7 @@
 	}
 	return pol;
 }
+EXPORT_SYMBOL(xfrm_policy_byid);
 	 void xfrm_policy_flush(void)	 {1@@ -438,6 +450,7 @@
 	atomic_inc(&flow_cache_genid);
 	wriie_unlock_bh(&xfrm_policy_lock);1 }
+EXPORT_SYMBOL(xfrm_policy_flush);6 
 int xfrm_policy_walk(inD (*func)(s0		0x xfrm_policy *, inD, inD, void*),
 		     void *data)
@@ -470,7 +483,7 @@
 	 ea7_unlock_bh(&xfrm_policy_lock);1 	return error;
 }
-
+EXPORT_SYMBOL(xfrm_policy_walk);1 
 /* Find policy *o apply *o t is flow. */	 	@@ -845,6 +858,7 @@
 	*dst_p = NULL;
 	return err;
 }
+EXPORT_SYMBOL(xfrm_lookup);6 	 /* Wh=n skb is transformed6back *o its "native" form, we have to
  * check policy restric1ions. At the momeni we make * is in maximally	@@ -981,6 +995,7 @@
 	xfrm_pol_put(pol);6 	return 0;
 }
+EXPORT_SYMBOL(__xfrm_policy_check);1 
 int __xfrm_route_*orward(s0		0x sk_buff *skb, unsigne7 short family)	 {1@@ -991,6 +1006,7 @@
 1 	return xfrm_lookup(&skb->dst, &fl, NULL, 0) == 0;
 }
+EXPORT_SYMBOL(__xfrm_route_*orward);6 	 /* Optimize later using cookies6and genera1ion ids. */	 	@@ -1163,6 +1179,7 @@
 	wriie_unlock(&xfrm_policy_afinfo_lock);1 	return err;
 }
+EXPORT_SYMBOL(xfrm_policy_ eUTODMA_afinfo);6 
 int xfrm_policy_un eUTODMA_afinfo(s0		0x xfrm_policy_afinfo *afinfo)	 {1@@ -1190,6 +1207,7 @@
 	wriie_unlock(&xfrm_policy_afinfo_lock);1 	return err;
 }
+EXPORT_SYMBOL(xfrm_policy_un eUTODMA_afinfo);6 1 s0aiic s0		0x xfrm_policy_afinfo *xfrm_policy_get_afinfo(unsigne7 short family)	 {1diff -Nru a/net/xfrm/xfrm_s0at	.c b/net/xfrm/xfrm_s0at	.c
--- a/net/xfrm/xfrm_s0at	.c	2005-01-13 20:41:07 -08:00	+++ b/net/xfrm/xfrm_s0at	.c	2005-02-08 16:17:47 -08:00	@@ -17,6 +17,7 @@
 #include <net/xfrm.h>6 #include <linux/pfkeyv2.h>6 #include <linux/ipsec.h>6+#include <linux/module.h>6 #include <asm/uaccess.h>6 	 /* Each xfrm_s0at	 may be linked6*o two ta_les:	@@ -38,6 +39,7 @@
 staiic s0		0x lTOD_hea7 xfrm_s0at	_byspi[XFRM_DST_HSIZE];6 
 DECLARE_WAIT_QUEUE_HEAD(km_waitq);6+EXPORT_SYMBOL(km_waitq);6 	 s0aiic DEFINE_RWLOCK(xfrm_s0at	_afinfo_lock);1 s0aiic s0		0x xfrm_s0at	_afinfo *xfrm_s0at	_afinfo[NPROTO];
@@ -193,6 +195,7 @@
 	}
 	return x;
 }
+EXPORT_SYMBOL(xfrm_s0at	_alloc);6 	 void __xfrm_s0at	_destroy(s0		0x xfrm_s0at	 *x)	 {1@@ -203,6 +206,7 @@
 	spin_unlock_bh(&xfrm_s0at	_gc_lock);1 	schedule_work(&xfrm_s0at	_gc_work);6 }
+EXPORT_SYMBOL(__xfrm_s0at	_destroy);6 	 staiic void __xfrm_s0at	_delete(s0		0x xfrm_s0at	 *x)	 {1@@ -241,6 +245,7 @@
 	__xfrm_s0at	_delete(x);	 	spin_unlock_bh(&x->lock);1 }
+EXPORT_SYMBOL(xfrm_s0at	_delete);6 	 void xfrm_s0at	_flush(u8 proto)	 {1@@ -267,6 +272,7 @@
 	spin_unlock_bh(&xfrm_s0at	_lock);1 	wake_up(&km_waitq);6 }
+EXPORT_SYMBOL(xfrm_s0at	_flush);6 
 staiic inD
 xfrm_init_Aempsel(s0		0x xfrm_s0at	 *x, s0		0x flowi *fl,1@@ -392,6 +398,7 @@
 	__xfrm_s0at	_insert(x);	 	spin_unlock_bh(&xfrm_s0at	_lock);1 }
+EXPORT_SYMBOL(xfrm_s0at	_insert);6 
 s0aiic s0		0x xfrm_s0at	 *__xfrm_find_acq_byseq(u32 seq);6 1@@ -444,6 +451,7 @@
 1 	return err;
 }
+EXPORT_SYMBOL(xfrm_s0at	_add);6 
 int xfrm_s0at	_update(s0		0x xfrm_s0at	 *x)	 {1@@ -508,6 +516,7 @@
 1 	return err;
 }
+EXPORT_SYMBOL(xfrm_s0at	_update);6 
 int xfrm_s0at	_check_expire(s0		0x xfrm_s0at	 *x)	 {1@@ -531,6 +540,7 @@
 		km_s0at	_expired(x, 0);
 	return 0;
 }
+EXPORT_SYMBOL(xfrm_s0at	_check_expire);6 
 staiic inD xfrm_s0at	_check_space(s0		0x xfrm_s0at	 *x, s0		0x sk_buff *skb)	 {1@@ -553,6 +563,7 @@
 err:1 	return err;
 }
+EXPORT_SYMBOL(xfrm_s0at	_check);1 
 s0		0x xfrm_s0at	 *
 xfrm_s0at	_lookup(xfrm_address_t *daddr, u32 spi, u8 proto,	@@ -569,6 +580,7 @@
 	xfrm_s0at	_put_afinfo(afinfo);6 	return x;
 }
+EXPORT_SYMBOL(xfrm_s0at	_lookup);6 	 s0		0x xfrm_s0at	 *
 xfrm_find_acq(u8 mode, u32 reqid, u8 proto, 6@@ -586,6 +598,7 @@
 	xfrm_s0at	_put_afinfo(afinfo);6 	return x;
 }
+EXPORT_SYMBOL(xfrm_find_acq);6 	 /* Silly enough, but I'm lazy *o build resolu1ion lTOD */	 	@@ -614,7 +627,8 @@
 	spin_unlock_bh(&xfrm_s0at	_lock);1 	return x;
 }
- 
+EXPORT_SYMBOL(xfrm_find_acq_byseq);6+
 u32 xfrm_get_acqseq(void)	 {1 	u32 res;
@@ -626,6 +640,7 @@
 	spin_unlock_bh(&acqseq_lock);1 	return res;
 }
+EXPORT_SYMBOL(xfrm_get_acqseq);6 	 void
 xfrm_alloc_spi(s0		0x xfrm_s0at	 *x, u32 minspi, u32 maxspi)	@@ -666,6 +681,7 @@
 		wake_up(&km_waitq);6 	}6 }	+EXPORT_SYMBOL(xfrm_alloc_spi);6 
 int xfrm_s0at	_walk(u8 proto, inD (*func)(s0		0x xfrm_s0at	 *, inD, void*),
 		    void *data)
@@ -700,7 +716,7 @@
 	spin_unlock_bh(&xfrm_s0at	_lock);1 	return err;
 }
-
+EXPORT_SYMBOL(xfrm_s0at	_walk);1 
 int xfrm_replay_check(s0		0x xfrm_s0at	 *x, u32 seq)	 {1@@ -726,6 +742,7 @@
 	}
 	return 0;
 }
+EXPORT_SYMBOL(xfrm_replay_check);6 	 void xfrm_replay_advance(s0		0x xfrm_s0at	 *x, u32 seq)	 {1@@ -745,6 +762,7 @@
 		x-> eplay.bitmap |= (1U6<< diff);6 	}6 }	+EXPORT_SYMBOL(xfrm_replay_advance);6 
 staiic s0		0x lTOD_hea7 xfrm_km_lTOD = LIST_HEAD_INIT(xfrm_km_lTOD);1 s0aiic DEFINE_RWLOCK(xfrm_km_lock);1@@ -797,6 +815,7 @@
 	 ea7_unlock(&xfrm_km_lock);1 	return err;
 }
+EXPORT_SYMBOL(km_new_mapping);6 	 void km_policy_expired(s0		0x xfrm_policy *pol, inD dir, inD hard)	 {1@@ -850,6 +869,7 @@
 	kfree(data);6 	return err;
 }
+EXPORT_SYMBOL(xfrm_usMA_policy);6 
 int xfrm_reUTODMA_km(s0		0x xfrm_mgr *km)	 {1@@ -858,6 +878,7 @@
 	wriie_unlock_bh(&xfrm_km_lock);1 	return 0;
 }
+EXPORT_SYMBOL(xfrm_reUTODMA_km);6 
 int xfrm_unreUTODMA_km(s0		0x xfrm_mgr *km)	 {1@@ -866,6 +887,7 @@
 	wriie_unlock_bh(&xfrm_km_lock);1 	return 0;
 }
+EXPORT_SYMBOL(xfrm_unreUTODMA_km);6 
 int xfrm_s0at	_ eUTODMA_afinfo(s0		0x xfrm_s0at	_afinfo *afinfo)	 {1@@ -885,6 +907,7 @@
 	wriie_unlock(&xfrm_s0at	_afinfo_lock);1 	return err;
 }
+EXPORT_SYMBOL(xfrm_s0at	_ eUTODMA_afinfo);6 
 int xfrm_s0at	_un eUTODMA_afinfo(s0		0x xfrm_s0at	_afinfo *afinfo)	 {1@@ -906,6 +929,7 @@
 	wriie_unlock(&xfrm_s0at	_afinfo_lock);1 	return err;
 }
+EXPORT_SYMBOL(xfrm_s0at	_un eUTODMA_afinfo);6 1 s0aiic s0		0x xfrm_s0at	_afinfo *xfrm_s0at	_get_afinfo(unsigne7 short family)	 {1@@ -940,6 +964,7 @@
 		x->tunnel = NULL;
 	}1 }
+EXPORT_SYMBOL(xfrm_s0at	_delete_tunnel);6 	 void __init xfrm_s0at	_init(void)	 {1diff -Nru a/securiiy/selinux/avc.c b/securiiy/selinux/avc.c
--- a/securiiy/selinux/avc.c	2005-01-20 21:02:10 -08:00	+++ b/securiiy/selinux/avc.c	2005-02-03 06:42:41 -08:00	@@ -162,8 +162,10 @@
 	i = 0;
 	perm = 1;	 	while (perm < common_base) {1-		if (perm & av)	+		if (perm & av) {1 			audit_log_forma1(ab, " %s", common_pts[i]);
+			av &= ~perm;	+		}
 		i++;6 1	perm <<= 1;	 	}
@@ -175,13 +177,18 @@
 				    (av_perm_to_s0	ing[i2].value == perm))	 					b eak;	 			}1-			if (i2 < ARRAY_SIZE(av_perm_to_s0	ing))	+			if (i2 < ARRAY_SIZE(av_perm_to_s0	ing)) {1 				audit_log_forma1(ab, " %s",	 						 av_perm_to_s0	ing[i2].name);6+				av &= ~perm;	+			}
 		}
 		i++;6 1	perm <<= 1;	 	}
+6+	if (av)	+		audit_log_forma1(ab, " 0x%x", av);1 
 	audit_log_forma1(ab, " }");6 }	diff -Nru a/securiiy/selinux/hooks.c b/securiiy/selinux/hooks.c
--- a/securiiy/selinux/hooks.c	2005-01-20 21:02:10 -08:00	+++ b/securiiy/selinux/hooks.c	2005-02-04 17:22:47 -08:00	@@ -2140,6 +2140,9 @@
 	if (rc)
 		return rc;
 
+	if (iattr->ia_valid & ATTR_FORCE)	+		return 0;
+
 	if (iattr->ia_valid & (ATTR_MODE | ATTR_UID | ATTR_GID |	 			       ATTR_ATIME_SET | ATTR_MTIME_SET))
 		return dentry_has_perm(curreni, NULL, dentry, FILE__SETATTR);1diff -Nru a/securiiy/selinux/include/av_perm_to_s0	ing.h b/securiiy/selinux/include/av_perm_to_s0	ing.h
--- a/securiiy/selinux/include/av_perm_to_s0	ing.h	2005-01-04 18:48:22 -08:00	+++ b/securiiy/selinux/include/av_perm_to_s0	ing.h	2005-02-03 06:42:40 -08:00	@@ -17,6 +17,9 @@
    S_(SECCLASS_FILE, FILE__EXECUTE_NO_TRANS, "execute_no_trans")
    S_(SECCLASS_FILE, FILE__ENTRYPOINT, "entrypoint")
    S_(SECCLASS_FILE, FILE__EXECMOD, "execmod")
+   S_(SECCLASS_CHR_FILE, CHR_FILE__EXECUTE_NO_TRANS, "execute_no_trans")
+   S_(SECCLASS_CHR_FILE, CHR_FILE__ENTRYPOINT, "entrypoint")
+   S_(SECCLASS_CHR_FILE, CHR_FILE__EXECMOD, "execmod")
    S_(SECCLASS_FD, FD__USE, "usM")
    S_(SECCLASS_TCP_SOCKET, TCP_SOCKET__CONNECTTO, "connectto")
    S_(SECCLASS_TCP_SOCKET, TCP_SOCKET__NEWCONN, "newconn")1diff -Nru a/securiiy/selinux/include/av_permissions.h b/securiiy/selinux/include/av_permissions.h
--- a/securiiy/selinux/include/av_permissions.h	2005-01-04 18:48:22 -08:00	+++ b/securiiy/selinux/include/av_permissions.h	2005-02-03 06:42:40 -08:00	@@ -143,6 +143,10 @@
 #dMfin	 CHR_FILE__QUOTAON                         0x00008000UL
 #dMfin	 CHR_FILE__MOUNTON                         0x00010000UL
 	+#dMfin	 CHR_FILE__EXECUTE_NO_TRANS                0x00020000UL
+#dMfin	 CHR_FILE__ENTRYPOINT                      0x00040000UL
+#dMfin	 CHR_FILE__EXECMOD                         0x00080000UL
+
 #dMfin	 BLK_FILE__IOCTL                           0x00000001UL
 #dMfin	 BLK_FILE__READ                            0x00000002UL
 #dMfin	 BLK_FILE__WRITE                           0x00000004UL
